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 A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
 
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 <img src="/doc/ciic_harness.png" width="75%" height="75%"> 
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 This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10).  See [the Caravel  premliminary datasheet](doc/caravel_datasheet.pdf) for details.
 The repository contains a [sample user project](/verilog/rtl/user_proj_example.v) that contains a binary 32-bit up counter.  </br>
 
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 <img src="/doc/counter_32.png" width="50%" height="50%">
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