diff --git a/openlane/mgmt_core/config.tcl b/openlane/mgmt_core/config.tcl
index 8931d38..e91ab41 100644
--- a/openlane/mgmt_core/config.tcl
+++ b/openlane/mgmt_core/config.tcl
@@ -30,7 +30,7 @@
 set ::env(FP_CONTEXT_DEF) $script_dir/../caravel/runs/caravel/tmp/floorplan/verilog2def_openroad.def.macro_placement.def
 set ::env(FP_CONTEXT_LEF) $script_dir/../caravel/runs/caravel/tmp/merged_unpadded.lef
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 2150 850"
+set ::env(DIE_AREA) "0 0 2150 900"
 
 
 set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
diff --git a/openlane/mgmt_core/macro_placement.cfg b/openlane/mgmt_core/macro_placement.cfg
index 1863d9e..e8a3c3a 100644
--- a/openlane/mgmt_core/macro_placement.cfg
+++ b/openlane/mgmt_core/macro_placement.cfg
@@ -1,2 +1,2 @@
 pll 1686.845 10.880 N
-soc.soc_mem.mem.SRAM 302.695 136.400 N
+soc.soc_mem.mem.SRAM 302.695 156.400 N
diff --git a/openlane/mgmt_protect/config.tcl b/openlane/mgmt_protect/config.tcl
index c1ffd39..f0b1e80 100755
--- a/openlane/mgmt_protect/config.tcl
+++ b/openlane/mgmt_protect/config.tcl
@@ -35,17 +35,47 @@
 # there is $not...
 # set ::env(SYNTH_TOP_LEVEL) 1
 
-# set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-set ::env(FP_CONTEXT_DEF) $script_dir/../caravel/runs/caravel/tmp/floorplan/verilog2def_openroad.def.macro_placement.def
-set ::env(FP_CONTEXT_LEF) $script_dir/../caravel/runs/caravel/tmp/merged_unpadded.lef
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+# set ::env(FP_CONTEXT_DEF) $script_dir/../caravel/runs/caravel/tmp/floorplan/verilog2def_openroad.def.macro_placement.def
+# set ::env(FP_CONTEXT_LEF) $script_dir/../caravel/runs/caravel/tmp/merged_unpadded.lef
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 850 65"
-set ::env(BOTTOM_MARGIN_MULT) 1
-set ::env(TOP_MARGIN_MULT) 1
-set ::env(LEFT_MARGIN_MULT) 4
-set ::env(RIGHT_MARGIN_MULT) 4
+set ::env(DIE_AREA) "0 0 1000 55"
+set ::env(BOTTOM_MARGIN_MULT) 2
+set ::env(TOP_MARGIN_MULT) 2
+set ::env(LEFT_MARGIN_MULT) 12
+set ::env(RIGHT_MARGIN_MULT) 12
+
+set ::env(FP_IO_VEXTEND) 2
+set ::env(FP_IO_HEXTEND) 2
+
+
+set ::env(PDN_CFG) $script_dir/pdn.tcl
+set ::env(FP_PDN_AUTO_ADJUST) 0
+set ::env(FP_PDN_CORE_RING) 1
+set ::env(FP_PDN_CORE_RING_VSPACING) 0.4
+set ::env(FP_PDN_CORE_RING_HSPACING) 0.4
+set ::env(FP_PDN_VOFFSET) 15
+set ::env(FP_PDN_HOFFSET) 32.88
+set ::env(FP_PDN_CORE_RING_VWIDTH) 0.3
+set ::env(FP_PDN_CORE_RING_HWIDTH) 0.3
+set ::env(FP_PDN_CORE_RING_VOFFSET) 7
+set ::env(FP_PDN_CORE_RING_HOFFSET) 7
+set ::env(FP_PDN_VWIDTH) 0.3
+set ::env(FP_PDN_HWIDTH) 0.3
+set ::env(FP_PDN_VPITCH) 200
+set ::env(FP_PDN_HPITCH) 5.44
+
+set ::env(FP_PDN_LOWER_LAYER) met4
+set ::env(FP_PDN_UPPER_LAYER) met3
+set ::env(GLB_RT_MAXLAYER) 5
+set ::env(GLB_RT_OBS) "met5 $::env(DIE_AREA)"
+
+set ::env(FP_VERTICAL_HALO) 0
+
+set ::env(PL_TARGET_DENSITY) 0.55
 
 set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
-set ::env(GLB_RT_ALLOW_CONGESTION) 1
-set ::env(DIODE_INSERTION_STRATEGY) 1
+set ::env(GLB_RT_ALLOW_CONGESTION) 0
+set ::env(DIODE_INSERTION_STRATEGY) 3
diff --git a/openlane/mgmt_protect/macro_placement.cfg b/openlane/mgmt_protect/macro_placement.cfg
index 7dbbf89..efae4a1 100644
--- a/openlane/mgmt_protect/macro_placement.cfg
+++ b/openlane/mgmt_protect/macro_placement.cfg
@@ -1 +1 @@
-powergood_check 475.310 5.605 N
+powergood_check 783.050 15.180 N
diff --git a/openlane/mgmt_protect/pdn.tcl b/openlane/mgmt_protect/pdn.tcl
new file mode 100644
index 0000000..9ab2011
--- /dev/null
+++ b/openlane/mgmt_protect/pdn.tcl
@@ -0,0 +1,102 @@
+# Power nets
+
+if { ! [info exists ::env(VDD_NET)] } {
+	set ::env(VDD_NET) $::env(VDD_PIN)
+}
+
+if { ! [info exists ::env(GND_NET)] } {
+	set ::env(GND_NET) $::env(GND_PIN)
+}
+
+set ::power_nets $::env(VDD_NET)
+set ::ground_nets $::env(GND_NET)
+
+if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } {
+    if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } {
+        # to parameterize -- needs a PDNGEN fix
+        set pdngen::global_connections {
+            VPWR {
+                {inst_name .* pin_name VPWR}
+                {inst_name .* pin_name VPB}
+            }
+            VGND {
+                {inst_name .* pin_name VGND}
+                {inst_name .* pin_name VNB}
+            }
+        }
+    }
+}
+
+# Used if the design is the core of the chip
+set stdcell_core {
+    name grid
+    straps {
+	    $::env(FP_PDN_LOWER_LAYER) {width $::env(FP_PDN_VWIDTH) pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+    }
+    connect {{$::env(FP_PDN_UPPER_LAYER) $::env(FP_PDN_LOWER_LAYER)}}
+}
+
+# Used if the design is a macro in the core
+set stdcell_macro {
+    name grid
+    straps {
+	    $::env(FP_PDN_LOWER_LAYER) {width $::env(FP_PDN_VWIDTH) pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+    }
+    connect {}
+}
+
+# Assesses whether the deisgn is the core of the chip or not based on the value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
+if { [info exists ::env(DESIGN_IS_CORE)] } {
+    if { $::env(DESIGN_IS_CORE) == 1 } {
+        set stdcell $stdcell_core
+    } else {
+        set stdcell $stdcell_macro
+    }
+} else {
+    set stdcell $stdcell_core
+}
+
+# Adds the core ring if enabled.
+if { [info exists ::env(FP_PDN_CORE_RING)] } {
+    if { $::env(FP_PDN_CORE_RING) == 1 } {
+        dict append stdcell core_ring {
+                $::env(FP_PDN_LOWER_LAYER) {width $::env(FP_PDN_CORE_RING_VWIDTH) spacing $::env(FP_PDN_CORE_RING_VSPACING) core_offset $::env(FP_PDN_CORE_RING_VOFFSET)}
+                $::env(FP_PDN_UPPER_LAYER) {width $::env(FP_PDN_CORE_RING_HWIDTH) spacing $::env(FP_PDN_CORE_RING_HSPACING) core_offset $::env(FP_PDN_CORE_RING_HOFFSET)}
+            }
+    }
+}
+
+# Adds the core ring if enabled.
+if { [info exists ::env(FP_PDN_ENABLE_RAILS)] } {
+    if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
+		dict append stdcell rails {
+			$::env(FP_PDN_RAILS_LAYER) {width $::env(FP_PDN_RAIL_WIDTH) pitch $::env(PLACE_SITE_HEIGHT) offset $::env(FP_PDN_RAIL_OFFSET)}
+		}
+		dict update stdcell connect current_connect {
+			append current_connect { {$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)}}
+		}
+    } else {
+		dict append stdcell rails {}
+	}
+}
+
+pdngen::specify_grid stdcell $stdcell
+
+# A general macro that follows the premise of the set heirarchy. You may want to modify this or add other macro configs
+pdngen::specify_grid macro {
+    orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
+    power_pins $::env(VDD_NET)
+    ground_pins $::env(GND_NET)
+    blockages "met3"
+    straps {
+    }
+    connect {{$::env(FP_PDN_UPPER_LAYER)_PIN_hor $::env(FP_PDN_LOWER_LAYER)}}
+}
+
+set ::halo [expr min($::env(FP_HORIZONTAL_HALO), $::env(FP_VERTICAL_HALO))]
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/mgmt_protect/pin_order.cfg b/openlane/mgmt_protect/pin_order.cfg
index 5892fef..eaebf80 100644
--- a/openlane/mgmt_protect/pin_order.cfg
+++ b/openlane/mgmt_protect/pin_order.cfg
@@ -1,18 +1,17 @@
+#BUS_SORT
 #S
-la_.*_mprj\[.*
-mprj_.*
-
+la_data_out_mprj.*
+la_data_in_mprj.*
+la_oen_mprj.*
 .*_o_core.*
-.*_mprj.*
-.*power.*
+.*powergood.*
 
 #N
-la_.*_core\[.*
-
-.*_user.*
-.*_core.*
+user_.*
+la_data_in_core.*
+la_data_out_core.*
+la_oen_core.*
+.*_o_user.*
 
 #W
-user.*
 caravel_.*
-user_clock.*
diff --git a/openlane/mgmt_protect_hv/config.tcl b/openlane/mgmt_protect_hv/config.tcl
index 700e213..b151739 100644
--- a/openlane/mgmt_protect_hv/config.tcl
+++ b/openlane/mgmt_protect_hv/config.tcl
@@ -19,6 +19,15 @@
 
 set ::env(STD_CELL_LIBRARY) sky130_fd_sc_hvl
 
+set ::env(DESIGN_IS_CORE) 1
+set ::env(FP_PDN_LOWER_LAYER) met2
+set ::env(FP_PDN_UPPER_LAYER) met3
+set ::env(FP_PDN_VWIDTH) 0.3
+set ::env(FP_PDN_HWIDTH) 0.3
+
+set ::env(GLB_RT_MAXLAYER) 4
+# set ::env(FP_PDN_CORE_RING) 1
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
 set ::env(VERILOG_FILES) "\
 	$script_dir/../../verilog/rtl/defines.v\
 	$script_dir/../../verilog/rtl/mgmt_protect_hv.v"
@@ -28,7 +37,9 @@
 set ::env(SYNTH_TOP_LEVEL) 1
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 25 25"
+set ::env(DIE_AREA) "0 0 200 30"
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
 
 set ::env(CLOCK_TREE_SYNTH) 0
 
@@ -38,8 +49,8 @@
 
 set ::env(BOTTOM_MARGIN_MULT) 1
 set ::env(TOP_MARGIN_MULT) 1
-set ::env(LEFT_MARGIN_MULT) 1
-set ::env(RIGHT_MARGIN_MULT) 1
+set ::env(LEFT_MARGIN_MULT) 10
+set ::env(RIGHT_MARGIN_MULT) 0
 
 set ::env(PLACE_SITE) "unithv"
 set ::env(PLACE_SITE_WIDTH) 0.480
diff --git a/openlane/mgmt_protect_hv/pin_order.cfg b/openlane/mgmt_protect_hv/pin_order.cfg
new file mode 100644
index 0000000..ed44b17
--- /dev/null
+++ b/openlane/mgmt_protect_hv/pin_order.cfg
@@ -0,0 +1,2 @@
+#W
+.*