Notice 0: Reading LEF file:  /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/DFFRAM/runs/DFFRAM/results/routing/DFFRAM.def
Notice 0: Design: DFFRAM
Notice 0:     Created 80 pins.
Notice 0:     Created 40233 components and 211486 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 12163 nets and 60270 connections.
Notice 0: Finished DEF file: /project/openlane/DFFRAM/runs/DFFRAM/results/routing/DFFRAM.def
Top-level design name: DFFRAM
Found port VPWR of type SIGNAL
Found port VGND of type SIGNAL
Power net:  VPWR
Ground net: VGND
Modified power connections of 40233 cells (Remaining: 0 ).