Notice 0: Reading LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/floorplan/verilog2def_openroad.def
Notice 0: Design: mgmt_core
Notice 0:     Created 959 pins.
Notice 0:     Created 34964 components and 252770 component-terminals.
Notice 0:     Created 35505 nets and 112904 connections.
Notice 0: Finished DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/floorplan/verilog2def_openroad.def
Top-level design name: mgmt_core
Warning: Some pins weren't matched by the config file
Those are: ['porb']
Assigning random sides to the above pins
Block boundaries: 0 0 2150000 850000
Writing /project/openlane/mgmt_core/runs/mgmt_core/tmp/floorplan/ioPlacer.def