Notice 0: Reading LEF file:  /project/openlane/user_project_wrapper_empty/runs/user_project_wrapper/tmp/merged.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/user_project_wrapper_empty/runs/user_project_wrapper/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/user_project_wrapper_empty/runs/user_project_wrapper/tmp/floorplan/verilog2def_openroad.def
Notice 0: Design: user_project_wrapper
Notice 0:     Created 636 pins.
Notice 0:     Created 1 components and 606 component-terminals.
Notice 0:     Created 636 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper_empty/runs/user_project_wrapper/tmp/floorplan/verilog2def_openroad.def
Top-level design name: user_project_wrapper
Block boundaries: 0 0 2920000 3520000
Writing /project/openlane/user_project_wrapper_empty/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def