tree d3162c56fab70f20f264202df8469db34871d76a
parent c86f63de91adf00bd1409a025a08a6f26acdcd5d
author Tim Edwards <tim@opencircuitdesign.com> 1606503365 -0500
committer Tim Edwards <tim@opencircuitdesign.com> 1606503365 -0500

Corrected the simple_por layout to avoid overlapping the capacitor
plate of the top capacitor with the vias on the bottom capacitor.
This corresponds to an update in the magic techfile in open_pdks
to enforce the contact overlap prohibition.  Also updated the LVS
run script to account for the change in directory path to the POR
netlist.  Corrected the POR netlist to correct the dummy resistor
size (they were specified in series instead of in parallel).  Re-
extracted the POR and ran LVS.