diff --git a/verilog/rtl/simpleuart.v b/verilog/rtl/simpleuart.v
index 51e95c7..54a3cb4 100644
--- a/verilog/rtl/simpleuart.v
+++ b/verilog/rtl/simpleuart.v
@@ -20,7 +20,8 @@
 module simpleuart_wb # (
     parameter BASE_ADR = 32'h 2000_0000,
     parameter CLK_DIV = 8'h00,
-    parameter DATA = 8'h04
+    parameter DATA = 8'h04,
+    parameter CONFIG = 8'h08
 ) (
     input wb_clk_i,
     input wb_rst_i,
@@ -35,26 +36,33 @@
     output wb_ack_o,
     output [31:0] wb_dat_o,
 
+    output uart_enabled,
     output ser_tx,
     input  ser_rx
 
 );
     wire [31:0] simpleuart_reg_div_do;
     wire [31:0] simpleuart_reg_dat_do;
+    wire [31:0] simpleuart_reg_cfg_do;
 
     wire resetn = ~wb_rst_i;
     wire valid = wb_stb_i && wb_cyc_i; 
     wire simpleuart_reg_div_sel = valid && (wb_adr_i == (BASE_ADR | CLK_DIV));
     wire simpleuart_reg_dat_sel = valid && (wb_adr_i == (BASE_ADR | DATA));
+    wire simpleuart_reg_cfg_sel = valid && (wb_adr_i == (BASE_ADR | CONFIG));
 
-    wire [3:0] reg_div_we = simpleuart_reg_div_sel ? (wb_sel_i & {4{wb_we_i}}): 4'b 0000; // simpleuart_reg_div_sel ? mem_wstrb : 4'b 0000), // sel: depends on address buss
+    wire [3:0] reg_div_we = simpleuart_reg_div_sel ? (wb_sel_i & {4{wb_we_i}}): 4'b 0000; 
     wire reg_dat_we = simpleuart_reg_dat_sel ? (wb_sel_i[0] & wb_we_i): 1'b 0;      // simpleuart_reg_dat_sel ? mem_wstrb[0] : 1'b 0
+    wire reg_cfg_we = simpleuart_reg_cfg_sel ? (wb_sel_i[0] & wb_we_i): 1'b 0; 
 
     wire [31:0] mem_wdata = wb_dat_i;
     wire reg_dat_re = simpleuart_reg_dat_sel && !wb_sel_i && ~wb_we_i; // read_enable
 
-    assign wb_dat_o = simpleuart_reg_div_sel ? simpleuart_reg_div_do: simpleuart_reg_dat_do;
-    assign wb_ack_o = (simpleuart_reg_div_sel || simpleuart_reg_dat_sel) && (!reg_dat_wait);
+    assign wb_dat_o = simpleuart_reg_div_sel ? simpleuart_reg_div_do:
+		      simpleuart_reg_cfg_sel ? simpleuart_reg_cfg_do:
+					       simpleuart_reg_dat_do;
+    assign wb_ack_o = (simpleuart_reg_div_sel || simpleuart_reg_dat_sel
+			|| simpleuart_reg_cfg_sel) && (!reg_dat_wait);
     
     simpleuart simpleuart (
         .clk    (wb_clk_i),
@@ -62,11 +70,16 @@
 
         .ser_tx      (ser_tx),
         .ser_rx      (ser_rx),
+	.enabled     (uart_enabled),
 
         .reg_div_we  (reg_div_we), 
         .reg_div_di  (mem_wdata),
         .reg_div_do  (simpleuart_reg_div_do),
 
+        .reg_cfg_we  (reg_cfg_we), 
+        .reg_cfg_di  (mem_wdata),
+        .reg_cfg_do  (simpleuart_reg_cfg_do),
+
         .reg_dat_we  (reg_dat_we),
         .reg_dat_re  (reg_dat_re),
         .reg_dat_di  (mem_wdata),
@@ -80,6 +93,7 @@
     input clk,
     input resetn,
 
+    output enabled,
     output ser_tx,
     input  ser_rx,
 
@@ -87,6 +101,10 @@
     input  [31:0] reg_div_di,         
     output [31:0] reg_div_do,         
 
+    input   	  reg_cfg_we,         
+    input  [31:0] reg_cfg_di,         
+    output [31:0] reg_cfg_do,         
+
     input         reg_dat_we,         
     input         reg_dat_re,         
     input  [31:0] reg_dat_di,
@@ -94,6 +112,7 @@
     output        reg_dat_wait
 );
     reg [31:0] cfg_divider;
+    reg        enabled;
 
     reg [3:0] recv_state;
     reg [31:0] recv_divcnt;
@@ -107,6 +126,7 @@
     reg send_dummy;
 
     assign reg_div_do = cfg_divider;
+    assign reg_ena_do = {31'd0, enabled};
 
     assign reg_dat_wait = reg_dat_we && (send_bitcnt || send_dummy);
     assign reg_dat_do = recv_buf_valid ? recv_buf_data : ~0;
@@ -114,11 +134,13 @@
     always @(posedge clk) begin
         if (!resetn) begin
             cfg_divider <= 1;
+	    enabled <= 1'b0;
         end else begin
             if (reg_div_we[0]) cfg_divider[ 7: 0] <= reg_div_di[ 7: 0];
             if (reg_div_we[1]) cfg_divider[15: 8] <= reg_div_di[15: 8];
             if (reg_div_we[2]) cfg_divider[23:16] <= reg_div_di[23:16];
             if (reg_div_we[3]) cfg_divider[31:24] <= reg_div_di[31:24];
+            if (reg_cfg_we) enabled <= reg_div_di[0];
         end
     end
 
@@ -135,7 +157,7 @@
                 recv_buf_valid <= 0;
             case (recv_state)
                 0: begin
-                    if (!ser_rx)
+                    if (!ser_rx && enabled)
                         recv_state <= 1;
                     recv_divcnt <= 0;
                 end
@@ -166,7 +188,7 @@
     assign ser_tx = send_pattern[0];
 
     always @(posedge clk) begin
-        if (reg_div_we)
+        if (reg_div_we && enabled)
             send_dummy <= 1;
         send_divcnt <= send_divcnt + 1;
         if (!resetn) begin