)]}'
{
  "commit": "c18c474118be6020a759267525f5df7c62ce7ee4",
  "tree": "8e1508d62f69603062b7454bd78eda908bf30bb5",
  "parents": [
    "04ba17f7ad1e0fd5ea56b89a6bb64d61d6fe1923"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sat Oct 03 11:26:39 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sat Oct 03 11:26:39 2020 -0400"
  },
  "message": "Fixed the syntactical loose ends from yesterday.  There are\nstill additional functional issues that need to be addressed,\nbut this is progress.\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "06fe61ef416b905605434a6451be84011ef3642c",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio.vcd"
    },
    {
      "type": "modify",
      "old_id": "f8cd3ca9c3d77f1ad1bd672a0a69e441103e2dec",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v",
      "new_id": "f82373741eeff382e768d407cc3b915c37850f63",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v"
    },
    {
      "type": "modify",
      "old_id": "beced01ea0eed3dbd3ff99de3cd7313b85e340f2",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "abcbd8ad85103016f3d59a3a023ddb85e50f82a8",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_soc.v",
      "new_id": "5162a9bb35967f8102b87ce9ea55f5ae41167d76",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_soc.v"
    },
    {
      "type": "modify",
      "old_id": "66250cbeff4c2f302c111e40c8e47c4ab36cbbce",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mprj_ctrl.v",
      "new_id": "8970c41cae96a9edb7d6f53f21d17536966eaa7f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mprj_ctrl.v"
    }
  ]
}