,design,design_name,config,runtime,DIEAREA_mm^2,CellPer_mm^2,(Cell/mm^2)/Core_Util,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
0,/project/openlane/user_proj_example,user_proj_example,16-12_10-43,2h52m33s,7.75,24171.483870967742,48342.967741935485,-1,5582.41,187329,0,0,0,0,0,0,0,17,56,13819851,1657614,0.0,-0.26,0.0,0.0,0.0,0.0,-0.5,0.0,0.0,0.0,11420932923,0.0,29.91,43.6,1.37,9.54,-1,187108,187696,26865,27453,0,0,0,187329,2085,365,1229,1791,5938,1481,455,60114,26865,27478,44,2262,100264,0,102526,50.0,20.0,20,2,5,50,1,153.6,153.18,0.38,0,sky130_fd_sc_hd,8,0