# General config
set ::env(PDK) "sky130A"
set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
set ::env(PDK_ROOT) "/mnt/data/workspace/pdk"
set ::env(CELL_PAD) "8"
set ::env(MERGED_LEF) "/project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged.lef"
set ::env(MERGED_LEF_UNPADDED) "/project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef"
set ::env(TRACKS_INFO_FILE) "/project/openlane/user_proj_example/runs/16-12_10-43/tmp/tracks_copy.info"
set ::env(TECH_LEF) "/mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef"
# Design config
set ::env(CLOCK_PERIOD) "20"
set ::env(DESIGN_NAME) "user_proj_example"
set ::env(DESIGN_DIR) "/project/openlane/user_proj_example"
set ::env(CLOCK_PORT) "wb_clk_i"
# Synthesis config
set ::env(LIB_SYNTH) "/project/openlane/user_proj_example/runs/16-12_10-43/tmp/trimmed.lib"
set ::env(LIB_SYNTH_COMPLETE) "/mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
set ::env(SYNTH_CAP_LOAD) "17.65"
set ::env(SYNTH_MAX_FANOUT) "5"
set ::env(SYNTH_NO_FLAT) "0"
set ::env(SYNTH_MAX_TRAN) "[expr {0.1*20}]"
set ::env(LIB_FASTEST) "/mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
set ::env(LIB_SLOWEST) "/mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
set ::env(LIB_TYPICAL) "/mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
set ::env(SYNTH_SCRIPT) "/openLANE_flow/scripts/synth.tcl"
set ::env(SYNTH_STRATEGY) "2"
set ::env(CLOCK_BUFFER_FANOUT) "16"
set ::env(BASE_SDC_FILE) "/openLANE_flow/scripts/base.sdc"
# Floorplan config
set ::env(FP_CORE_UTIL) "50"
set ::env(FP_ASPECT_RATIO) "1"
set ::env(FP_CORE_MARGIN) "0"
set ::env(FP_IO_HMETAL) "4"
set ::env(FP_IO_VMETAL) "3"
set ::env(FP_WELLTAP_CELL) "sky130_fd_sc_hd__tapvpwrvgnd_1"
set ::env(FP_ENDCAP_CELL) "sky130_fd_sc_hd__decap_3"
set ::env(FP_PDN_VOFFSET) "16.32"
set ::env(FP_PDN_VPITCH) "153.6"
set ::env(FP_PDN_HOFFSET) "16.65"
set ::env(FP_PDN_HPITCH) "153.18"
set ::env(FP_TAPCELL_DIST) "14"
set ::env(CELL_PAD_EXCLUDE) "sky130_fd_sc_hd__tap* sky130_fd_sc_hd__decap* sky130_fd_sc_hd__fill*"
# Placement config
set ::env(PL_TARGET_DENSITY) "0.38"
set ::env(PL_TIME_DRIVEN) "0"
set ::env(PL_LIB) "/mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
set ::env(PL_BASIC_PLACEMENT) "0"
set ::env(PL_SKIP_INITIAL_PLACEMENT) "0"
set ::env(PL_RANDOM_GLB_PLACEMENT) "0"
set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) "1"
set ::env(PSN_ENABLE_RESIZING) "1"
set ::env(PSN_ENABLE_PIN_SWAP) "1"
set ::env(PL_RESIZER_OVERBUFFER) "0"
# CTS config
set ::env(CTS_TARGET_SKEW) "200"
set ::env(CTS_ROOT_BUFFER) "sky130_fd_sc_hd__clkbuf_16"
set ::env(CTS_TECH_DIR) "N/A"
set ::env(CTS_TOLERANCE) "100"
# Routing config
set ::env(GLB_RT_MAXLAYER) "5"
set ::env(GLB_RT_ADJUSTMENT) "0"
set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
set ::env(GLB_RT_L2_ADJUSTMENT) "0"
set ::env(GLB_RT_MINLAYER) "1"
set ::env(GLB_RT_MAXLAYER) "5"
set ::env(GLB_RT_UNIDIRECTIONAL) "1"
set ::env(GLB_RT_ALLOW_CONGESTION) "0"
set ::env(GLB_RT_OVERFLOW_ITERS) "50"
set ::env(GLB_RT_TILES) "15"
set ::env(GLB_RT_ESTIMATE_PARASITICS) "1"
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) "1"
set ::env(DIODE_PADDING) "2"
set ::env(SPEF_WIRE_MODEL) "L"
set ::env(SPEF_EDGE_CAP_FACTOR) "1"
# Flow control config
set ::env(RUN_SIMPLE_CTS) "0"
set ::env(RUN_ROUTING_DETAILED) "1"
set ::env(CLOCK_TREE_SYNTH) "1"
set ::env(LEC_ENABLE) "0"
set ::env(FILL_INSERTION) "1"
set ::env(DIODE_INSERTION_STRATEGY) "0"
set ::env(CHECK_ASSIGN_STATEMENTS) "0"
set ::env(CHECK_UNMAPPED_CELLS) "1"
set ::env(USE_ARC_ANTENNA_CHECK) "1"
set ::env(RUN_SPEF_EXTRACTION) "1"
set ::env(CURRENT_DEF) /project/openlane/user_proj_example/runs/16-12_10-43/results/routing/user_proj_example.def
set ::env(CURRENT_NETLIST) /project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v
set ::env(PREV_NETLIST) /project/openlane/user_proj_example/runs/16-12_10-43/results/synthesis/user_proj_example.synthesis_preroute.v