diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 3e92b15..5fc90d4 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -17,7 +17,8 @@
 `define functional
 `define UNIT_DELAY #1
 
-`define MPRJ_IO_PADS 32
+`define MPRJ_IO_PADS 37
+`define MPRJ_PWR_PADS 4		/* vdda1, vccd1, vdda2, vccd2 */
 
 `include "pads.v"
 
@@ -58,9 +59,21 @@
 `endif
 
 module caravel (
-    inout vdd3v3,
-    inout vdd1v8,
-    inout vss,
+    inout vddio,	// Common 3.3V padframe/ESD power
+    inout vssio,	// Common padframe/ESD ground
+    inout vdda,		// Management 3.3V power
+    inout vssa,		// Common analog ground
+    inout vccd,		// Management/Common 1.8V power
+    inout vssd,		// Common digital ground
+    inout vdda1,	// User area 1 3.3V power
+    inout vdda2,	// User area 2 3.3V power
+    inout vssa1,	// User area 1 analog ground
+    inout vssa2,	// User area 2 analog ground
+    inout vccd1,	// User area 1 1.8V power
+    inout vccd2,	// User area 2 1.8V power
+    inout vssd1,	// User area 1 digital ground
+    inout vssd2,	// User area 2 digital ground
+
     inout gpio,			// Used for external LDO control
     inout [`MPRJ_IO_PADS-1:0] mprj_io,
     input clock,	    	// CMOS core clock input, not a crystal
@@ -186,14 +199,26 @@
     // To be considered:  Master hold signal on all user pads (?)
     // For now, set holdh_n to 1 (NOTE:  This is in the 3.3V domain)
     // and setting enh to porb_h.
-    assign mprj_io_hldh_n = {`MPRJ_IO_PADS{vdd3v3}};
+    assign mprj_io_hldh_n = {`MPRJ_IO_PADS{vddio}};
     assign mprj_io_enh = {`MPRJ_IO_PADS{porb_h}};
 
     chip_io padframe(
 	// Package Pins
-	.vdd3v3(vdd3v3),
-	.vdd1v8(vdd1v8),
-	.vss(vss),
+	.vddio(vddio),
+	.vssio(vssio),
+	.vdda(vdda),
+	.vssa(vssa),
+	.vccd(vccd),
+	.vssd(vssd),
+	.vdda1(vdda1),
+	.vdda2(vdda2),
+	.vssa1(vssa1),
+	.vssa2(vssa2),
+	.vccd1(vccd1),
+	.vccd2(vccd2),
+	.vssd1(vssd1),
+	.vssd2(vssd2),
+
 	.gpio(gpio),
 	.mprj_io(mprj_io),
 	.clock(clock),
@@ -279,10 +304,13 @@
     // Mask revision
     wire [31:0] mask_rev;
 
-    mgmt_core soc (
+    mgmt_core #(
+	.MPRJ_IO_PADS(`MPRJ_IO_PADS),
+	.MPRJ_PWR_PADS(`MPRJ_PWR_PADS)
+    ) soc (
 	`ifdef LVS
-		.vdd1v8(vdd1v8),
-		.vss(vss),
+		.vdd(vccd),
+		.vss(vssa),
 	`endif
 		// GPIO (1 pin)
 		.gpio_out_pad(gpio_out_core),
@@ -360,7 +388,20 @@
 	/* User project is instantiated  here	*/
 	/*--------------------------------------*/
 
-	user_proj_example mprj ( 
+	user_proj_example #(
+	    .IO_PADS(`MPRJ_IO_PADS),
+	    .PWR_PADS(`MPRJ_PWR_PADS)
+	) mprj ( 
+	    `ifdef LVS
+		vdda1,	// User area 1 3.3V power
+		vdda2,	// User area 2 3.3V power
+		vssa1,	// User area 1 analog ground
+		vssa2,	// User area 2 analog ground
+		vccd1,	// User area 1 1.8V power
+		vccd2,	// User area 2 1.8V power
+		vssa1,	// User area 1 digital ground
+		vssa2,	// User area 2 digital ground
+	    `endif
     		.wb_clk_i(caravel_clk),
     		.wb_rst_i(!caravel_rstn),
 		// MGMT SoC Wishbone Slave 
@@ -474,11 +515,11 @@
 
     sky130_fd_sc_hvl__lsbufhv2lv porb_level (
 	`ifdef LVS
-		.vpwr(vdd3v3),
-		.vpb(vdd3v3),
-		.lvpwr(vdd1v8),
-		.vnb(vss),
-		.vgnd(vss),
+		.vpwr(vddio),
+		.vpb(vddio),
+		.lvpwr(vccd),
+		.vnb(vssio),
+		.vgnd(vssio),
 	`endif
 		.A(porb_h),
 		.X(porb_l)
@@ -492,19 +533,19 @@
 
     // Power-on-reset circuit
     simple_por por (
-		.vdd3v3(vdd3v3),
-		.vss(vss),
+		.vdd3v3(vddio),
+		.vss(vssio),
 		.porb_h(porb_h)
     );
 
     // XRES (chip input pin reset) reset level converter
     sky130_fd_sc_hvl__lsbufhv2lv rstb_level (
 	`ifdef LVS
-		.vpwr(vdd3v3),
-		.vpb(vdd3v3),
+		.vpwr(vddio),
+		.vpb(vddio),
 		.lvpwr(vdd1v8),
-		.vnb(vss),
-		.vgnd(vss),
+		.vnb(vssio),
+		.vgnd(vssio),
 	`endif
 		.A(rstb_h),
 		.X(rstb_l)
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index d34cfec..ebe0234 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -1,8 +1,20 @@
 module chip_io(
 	// Package Pins
-	inout  vdd3v3,
-    	inout  vdd1v8,
-    	inout  vss,
+	inout  vddio,		// Common padframe/ESD supply
+	inout  vssio,		// Common padframe/ESD ground
+	inout  vccd,		// Common 1.8V supply
+	inout  vssd,		// Common digital ground
+	inout  vdda,		// Management analog 3.3V supply
+	inout  vssa,		// Management analog ground
+	inout  vdda1,		// User area 1 3.3V supply
+	inout  vdda2,		// User area 2 3.3V supply
+	inout  vssa1,		// User area 1 analog ground
+	inout  vssa2,		// User area 2 analog ground
+	inout  vccd1,		// User area 1 1.8V supply
+	inout  vccd2,		// User area 2 1.8V supply
+	inout  vssd1,		// User area 1 digital ground
+	inout  vssd2,		// User area 2 digital ground
+
 	inout  gpio,
 	input  clock,
 	input  resetb,
@@ -56,78 +68,141 @@
 
 	wire analog_a, analog_b;
 	wire vddio_q, vssio_q;
-	// Instantiate power cells for VDD3V3 domain (8 total; 4 high clamps and
-    	// 4 low clamps)
-    	s8iom0_vdda_hvc_pad vdd3v3hclamp [1:0] (
-		`ABUTMENT_PINS
-		.drn_hvc(),
-		.src_bdy_hvc()
+
+	// Instantiate power and ground pads for management domain
+	// 12 pads:  vddio, vssio, vdda, vssa, vccd, vssd
+	// One each HV and LV clamp.
+
+    	s8iom0_vddio_hvc_pad mgmt_vddio_hvclamp_pad (
+		`MGMT_ABUTMENT_PINS
+		`HVCLAMP_PINS
+    	);
+    	s8iom0_vddio_lvc_pad mgmt_vddio_lvclamp_pad (
+		`MGMT_ABUTMENT_PINS
+		`LVCLAMP_PINS
     	);
 
-    	s8iom0_vddio_hvc_pad vddiohclamp [1:0] (
-		`ABUTMENT_PINS
-		.drn_hvc(),
-		.src_bdy_hvc()
+    	s8iom0_vdda_hvc_pad mgmt_vdda_hvclamp_pad (
+		`MGMT_ABUTMENT_PINS
+		`HVCLAMP_PINS
     	);
-	
-    	s8iom0_vdda_lvc_pad vdd3v3lclamp [3:0] (
-		`ABUTMENT_PINS
-		.bdy2_b2b(),
-		.drn_lvc1(),
-		.drn_lvc2(),
-		.src_bdy_lvc1(),
-		.src_bdy_lvc2()
+    	s8iom0_vdda_lvc_pad mgmt_vdda_lvclamp_pad (
+		`MGMT_ABUTMENT_PINS
+		`LVCLAMP_PINS
     	);
 
-    	// Instantiate the core voltage supply (since it is not generated on-chip)
-    	// (1.8V) (4 total, 2 high and 2 low clamps)
-    	s8iom0_vccd_hvc_pad vdd1v8hclamp [1:0] (
-		`ABUTMENT_PINS
-		.drn_hvc(),
-		.src_bdy_hvc()
+    	s8iom0_vccd_hvc_pad mgmt_vccd_hvclamp_pad (
+		`MGMT_ABUTMENT_PINS
+		`HVCLAMP_PINS
+    	);
+    	s8iom0_vccd_lvc_pad mgmt_vccd_lvclamp_pad (
+		`MGMT_ABUTMENT_PINS
+		`LVCLAMP_PINS
     	);
 
-    	s8iom0_vccd_lvc_pad vdd1v8lclamp [1:0] (
-		`ABUTMENT_PINS
-		.bdy2_b2b(),
-		.drn_lvc1(),
-		.drn_lvc2(),
-		.src_bdy_lvc1(),
-		.src_bdy_lvc2()
+    	s8iom0_vssio_hvc_pad mgmt_vssio_hvclamp_pad (
+		`MGMT_ABUTMENT_PINS
+		`HVCLAMP_PINS
+    	);
+    	s8iom0_vssio_lvc_pad mgmt_vssio_lvclamp_pad (
+		`MGMT_ABUTMENT_PINS
+		`LVCLAMP_PINS
     	);
 
-    	// Instantiate ground cells (7 total, 4 high clamps and 3 low clamps)
-    	s8iom0_vssa_hvc_pad vsshclamp [3:0] (
-		`ABUTMENT_PINS
-		.drn_hvc(),
-		.src_bdy_hvc()
+    	s8iom0_vssa_hvc_pad mgmt_vssa_hvclamp_pad (
+		`MGMT_ABUTMENT_PINS
+		`HVCLAMP_PINS
+    	);
+    	s8iom0_vssa_lvc_pad mgmt_vssa_lvclamp_pad (
+		`MGMT_ABUTMENT_PINS
+		`LVCLAMP_PINS
     	);
 
-    	s8iom0_vssa_lvc_pad vssalclamp (
-		`ABUTMENT_PINS
-		.bdy2_b2b(),
-		.drn_lvc1(),
-		.drn_lvc2(),
-		.src_bdy_lvc1(),
-		.src_bdy_lvc2()
+    	s8iom0_vssd_hvc_pad mgmt_vssd_hvclamp_pad (
+		`MGMT_ABUTMENT_PINS
+		`HVCLAMP_PINS
+    	);
+    	s8iom0_vssd_lvc_pad mgmt_vssd_lvclmap_pad (
+		`MGMT_ABUTMENT_PINS
+		`LVCLAMP_PINS
     	);
 
-    	s8iom0_vssd_lvc_pad vssdlclamp (
-		`ABUTMENT_PINS
-		.bdy2_b2b(),
-		.drn_lvc1(),
-		.drn_lvc2(),
-		.src_bdy_lvc1(),
-		.src_bdy_lvc2()
+	// Instantiate power and ground pads for user 1 domain
+	// 8 pads:  vdda, vssa, vccd, vssd;  One each HV and LV clamp.
+
+    	s8iom0_vdda_hvc_pad user1_vdda_hvclamp_pad (
+		`USER1_ABUTMENT_PINS
+		`HVCLAMP_PINS
+    	);
+    	s8iom0_vdda_lvc_pad user1_vdda_lvclamp_pad (
+		`USER1_ABUTMENT_PINS
+		`LVCLAMP_PINS
     	);
 
-    	s8iom0_vssio_lvc_pad vssiolclamp (
-		`ABUTMENT_PINS
-		.bdy2_b2b(),
-		.drn_lvc1(),
-		.drn_lvc2(),
-		.src_bdy_lvc1(),
-		.src_bdy_lvc2()
+    	s8iom0_vccd_hvc_pad user1_vccd_hvclamp_pad (
+		`USER1_ABUTMENT_PINS
+		`HVCLAMP_PINS
+    	);
+    	s8iom0_vccd_lvc_pad user1_vccd_lvclamp_pad (
+		`USER1_ABUTMENT_PINS
+		`LVCLAMP_PINS
+    	);
+
+    	s8iom0_vssa_hvc_pad user1_vssa_hvclamp_pad (
+		`USER1_ABUTMENT_PINS
+		`HVCLAMP_PINS
+    	);
+    	s8iom0_vssa_lvc_pad user1_vssa_lvclamp_pad (
+		`USER1_ABUTMENT_PINS
+		`LVCLAMP_PINS
+    	);
+
+    	s8iom0_vssd_hvc_pad user1_vssd_hvclamp_pad (
+		`USER1_ABUTMENT_PINS
+		`HVCLAMP_PINS
+    	);
+    	s8iom0_vssd_lvc_pad user1_vssd_lvclmap_pad (
+		`USER1_ABUTMENT_PINS
+		`LVCLAMP_PINS
+    	);
+
+	// Instantiate power and ground pads for user 2 domain
+	// 8 pads:  vdda, vssa, vccd, vssd;  One each HV and LV clamp.
+
+    	s8iom0_vdda_hvc_pad user2_vdda_hvclamp_pad (
+		`USER2_ABUTMENT_PINS
+		`HVCLAMP_PINS
+    	);
+    	s8iom0_vdda_lvc_pad user2_vdda_lvclamp_pad (
+		`USER2_ABUTMENT_PINS
+		`LVCLAMP_PINS
+    	);
+
+    	s8iom0_vccd_hvc_pad user2_vccd_hvclamp_pad (
+		`USER2_ABUTMENT_PINS
+		`HVCLAMP_PINS
+    	);
+    	s8iom0_vccd_lvc_pad user2_vccd_lvclamp_pad (
+		`USER2_ABUTMENT_PINS
+		`LVCLAMP_PINS
+    	);
+
+    	s8iom0_vssa_hvc_pad user2_vssa_hvclamp_pad (
+		`USER2_ABUTMENT_PINS
+		`HVCLAMP_PINS
+    	);
+    	s8iom0_vssa_lvc_pad user2_vssa_lvclamp_pad (
+		`USER2_ABUTMENT_PINS
+		`LVCLAMP_PINS
+    	);
+
+    	s8iom0_vssd_hvc_pad user2_vssd_hvclamp_pad (
+		`USER2_ABUTMENT_PINS
+		`HVCLAMP_PINS
+    	);
+    	s8iom0_vssd_lvc_pad user2_vssd_lvclmap_pad (
+		`USER2_ABUTMENT_PINS
+		`LVCLAMP_PINS
     	);
 
 	wire [2:0] dm_all =
@@ -137,12 +212,15 @@
 	wire[2:0] flash_io1_mode = 
 		{flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core};
 
-    	// GPIO pad
+	// Management clock input pad
+	`INPUT_PAD(clock, clock_core); 	    
+
+    	// Management GPIO pad
 	`INOUT_PAD(
 		gpio, gpio_in_core, gpio_out_core,
 		gpio_inenb_core, gpio_outenb_core, dm_all);
 	
-	// Flash pads
+	// Management Flash SPI pads
 	`INOUT_PAD(
 		flash_io0, flash_io0_di_core, flash_io0_do_core,
 		flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode);
@@ -150,19 +228,16 @@
 		flash_io1, flash_io1_di_core, flash_io1_do_core,
 		flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode);
 
-	`INPUT_PAD(clock, clock_core); 	    
-
-	// Output Pads
 	`OUTPUT_PAD(flash_csb, flash_csb_core, flash_csb_ieb_core, flash_csb_oeb_core);  
 	`OUTPUT_PAD(flash_clk, flash_clk_core, flash_clk_ieb_core, flash_clk_oeb_core);
 
-
 	// NOTE:  The analog_out pad from the raven chip has been replaced by
     	// the digital reset input resetb on caravel due to the lack of an on-board
     	// power-on-reset circuit.  The XRES pad is used for providing a glitch-
     	// free reset.
+
 	s8iom0s8_top_xres4v2 resetb_pad (
-		`ABUTMENT_PINS 
+		`MGMT_ABUTMENT_PINS 
 		`ifndef	TOP_ROUTING
 		    .pad(resetb),
 		`endif
@@ -171,38 +246,76 @@
 		.tie_lo_esd(),
 		.pad_a_esd_h(xresloop),
 		.xres_h_n(resetb_core_h),
-		.disable_pullup_h(vss),	    // 0 = enable pull-up on reset pad
-		.enable_h(vdd3v3),	    // Power-on-reset to the power-on-reset input??
-		.en_vddio_sig_h(vss),	    // No idea.
-		.inp_sel_h(vss),	    // 1 = use filt_in_h else filter the pad input
-		.filt_in_h(vss),	    // Alternate input for glitch filter
-		.pullup_h(vss),		    // Pullup connection for alternate filter input
-		.enable_vddio(vdd1v8)
+		.disable_pullup_h(vssio),    // 0 = enable pull-up on reset pad
+		.enable_h(porb_h),	    // Power-on-reset
+		.en_vddio_sig_h(vssio),	    // No idea.
+		.inp_sel_h(vssio),	    // 1 = use filt_in_h else filter the pad input
+		.filt_in_h(vssio),	    // Alternate input for glitch filter
+		.pullup_h(vssio),	    // Pullup connection for alternate filter input
+		.enable_vddio(vccd)
     	);
 
 	// Corner cells (These are overlay cells;  it is not clear what is normally
-    	// supposed to go under them.)
+    	// supposed to go under them.)  
+
 	`ifndef TOP_ROUTING   
-	    s8iom0_corner_pad corner [3:0] (
-		.vssio(vss),
-		.vddio(vdd3v3),
+	    s8iom0_corner_pad mgmt_corner [1:0] (
+		.vssio(vssio),
+		.vddio(vddio),
 		.vddio_q(vddio_q),
 		.vssio_q(vssio_q),
 		.amuxbus_a(analog_a),
 		.amuxbus_b(analog_b),
-		.vssd(vss),
-		.vssa(vss),
-		.vswitch(vdd3v3),
-		.vdda(vdd3v3),
-		.vccd(vdd1v8),
-		.vcchib(vdd1v8)
+		.vssd(vssio),
+		.vssa(vssio),
+		.vswitch(vddio),
+		.vdda(vdda),
+		.vccd(vccd),
+		.vcchib(vccd)
+    	    );
+	    s8iom0_corner_pad user1_corner (
+		.vssio(vssio),
+		.vddio(vddio),
+		.vddio_q(vddio_q),
+		.vssio_q(vssio_q),
+		.amuxbus_a(analog_a),
+		.amuxbus_b(analog_b),
+		.vssd(vssd1),
+		.vssa(vssa1),
+		.vswitch(vddio),
+		.vdda(vdda1),
+		.vccd(vccd1),
+		.vcchib(vccd)
+    	    );
+	    s8iom0_corner_pad user2_corner (
+		.vssio(vssio),
+		.vddio(vddio),
+		.vddio_q(vddio_q),
+		.vssio_q(vssio_q),
+		.amuxbus_a(analog_a),
+		.amuxbus_b(analog_b),
+		.vssd(vssd2),
+		.vssa(vssa2),
+		.vswitch(vddio),
+		.vdda(vdda2),
+		.vccd(vccd2),
+		.vcchib(vccd)
     	    );
 	`endif
 
 	mprj_io mprj_pads(
-		.vdd3v3(vdd3v3),
-		.vdd1v8(vdd1v8),
-		.vss(vss),
+		.vddio(vddio),
+		.vssio(vssio),
+		.vccd(vccd),
+		.vssd(vssd),
+		.vdda1(vdda1),
+		.vdda2(vdda2),
+		.vssa1(vssa1),
+		.vssa2(vssa2),
+		.vccd1(vccd1),
+		.vccd2(vccd2),
+		.vssd1(vssd1),
+		.vssd2(vssd2),
 		.vddio_q(vddio_q),
 		.vssio_q(vssio_q),
 		.analog_a(analog_a),
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index 032d2f5..49b29cd 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -1,4 +1,7 @@
-module mgmt_core(
+module mgmt_core #(
+	parameter MPRJ_IO_PADS = 32,
+	parameter MPRJ_PWR_PADS = 32
+) (
 `ifdef LVS
 	inout vdd1v8,	   
 	inout vss,
@@ -41,8 +44,8 @@
 	output jtag_out,
 	output jtag_outenb,
 	// Mega-Project Control Signals
-	input [`MPRJ_IO_PADS-1:0] mgmt_in_data,
-	output [`MPRJ_IO_PADS-1:0] mgmt_out_data,
+	input [MPRJ_IO_PADS-1:0] mgmt_in_data,
+	output [MPRJ_IO_PADS-1:0] mgmt_out_data,
 	output mprj_io_loader_resetn,
 	output mprj_io_loader_clock,
 	output mprj_io_loader_data,
@@ -110,7 +113,11 @@
 	// the pad.  All others have OEB controlled by the configuration bit
 	// in the control block.
 
-	mgmt_soc soc (
+	mgmt_soc #(
+	    .MPRJ_IO_PADS(MPRJ_IO_PADS),
+	    .MPRJ_PWR_PADS(MPRJ_PWR_PADS)
+	) soc (
+	
     	    `ifdef LVS
         	.vdd1v8(vdd1v8),
         	.vss(vss),
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 0de30f2..f6cf0f6 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -42,7 +42,10 @@
 `include "mprj_ctrl.v"
 `include "convert_gpio_sigs.v"
 
-module mgmt_soc (
+module mgmt_soc #(
+    parameter MPRJ_IO_PADS = 32,
+    parameter MPRJ_PWR_PADS = 32
+) (
 `ifdef LVS
     inout vdd1v8,	    /* 1.8V domain */
     inout vss,
@@ -194,10 +197,6 @@
     parameter LA_ENA_2  = 8'h18;
     parameter LA_ENA_3  = 8'h1c;
     
-    // Mega-Project Control
-    parameter MPRJ_IO_PADS  = 32;
-    parameter MPRJ_PWR_PADS = 32;
-   
     // System Control Registers
     parameter PLL_OUT       = 8'h00;
     parameter TRAP_OUT      = 8'h04;
@@ -639,7 +638,7 @@
     wire mprj_ctrl_stb_i;
     wire mprj_ctrl_ack_o;
     wire [31:0] mprj_ctrl_dat_o;
-    wire [31:0] mgmt_out_pre;
+    wire [MPRJ_IO_PADS-1:0] mgmt_out_pre;
 
     // Bits assigned to specific functions as outputs prevent the
     // mprj GPIO-as-output from applying data when that function
diff --git a/verilog/rtl/mprj_ctrl.v b/verilog/rtl/mprj_ctrl.v
index 117fcfe..ff04158 100644
--- a/verilog/rtl/mprj_ctrl.v
+++ b/verilog/rtl/mprj_ctrl.v
@@ -4,7 +4,7 @@
     parameter XFER   = 8'h 04,
     parameter CONFIG = 8'h 08,
     parameter IO_PADS = 32,   // Number of IO control registers
-    parameter PWR_PADS = 32   // Number of power control registers
+    parameter PWR_PADS = 32  // Number of power control registers
 )(
     input wb_clk_i,
     input wb_rst_i,
@@ -98,10 +98,14 @@
 `define XBYTE	2'b10
 `define LOAD	2'b11
 
-    localparam IO_BASE_ADR = (BASE_ADR | CONFIG);
-    localparam PWR_BASE_ADR = (BASE_ADR | CONFIG) + IO_PADS*4;
+    localparam IO_WORDS = 1 + (IO_PADS / 32);
+    localparam PWR_WORDS = 1 + (PWR_PADS / 32);
+
+    localparam IO_BASE_ADR = (BASE_ADR | CONFIG) + ((IO_WORDS + PWR_WORDS - 2) * 4);
+    localparam PWR_BASE_ADR = IO_BASE_ADR + (IO_PADS * 4);
     localparam OEB = 1;			// Offset of output enable in shift register.
     localparam INP_DIS = 3;		// Offset of input disable in shift register. 
+    localparam XFER_ADJ = XFER + ((IO_WORDS + PWR_WORDS - 2) * 4);
 
     reg [IO_CTRL_BITS-1:0] io_ctrl[IO_PADS-1:0];  // I/O control, 1 word per gpio pad
     reg [PWR_CTRL_BITS-1:0] pwr_ctrl[PWR_PADS-1:0]; // Power control, 1 word per power pad
@@ -109,16 +113,22 @@
     wire [IO_PADS-1:0] mgmt_gpio_out;	 // I/O write data output when input disabled
     reg xfer_ctrl;			// Transfer control (1 bit)
 
-    wire [IO_PADS-1:0] io_ctrl_sel;	// wishbone selects
-    wire [PWR_PADS-1:0] pwr_ctrl_sel;
-    wire io_data_sel;
+    wire [IO_WORDS-1:0] io_data_sel;	// wishbone selects
     wire xfer_sel;
+    wire [IO_PADS-1:0] io_ctrl_sel;
+    wire [PWR_PADS-1:0] pwr_ctrl_sel;
     wire [IO_PADS-1:0] mgmt_gpio_in;
 
-    assign xfer_sel = (iomem_addr[7:0] == XFER);
-    assign io_data_sel = (iomem_addr[7:0] == DATA); 
+    assign xfer_sel = (iomem_addr[7:0] == XFER_ADJ);
 
     genvar i;
+
+    generate
+        for (i=0; i<IO_WORDS; i=i+1) begin
+    	    assign io_data_sel[i] = (iomem_addr[7:0] == (DATA + i*4)); 
+	end
+    endgenerate
+
     generate
         for (i=0; i<IO_PADS; i=i+1) begin
             assign io_ctrl_sel[i] = (iomem_addr[7:0] == (IO_BASE_ADR[7:0] + i*4)); 
@@ -133,25 +143,17 @@
         end
     endgenerate
 
-    // I/O transfer of xfer bit and gpio data to/from user project region under
-    // management SoC control
+    // I/O transfer of xfer bit.  Also handles iomem_ready signal.
 
     always @(posedge clk) begin
 	if (!resetn) begin
 	    xfer_ctrl <= 0;
-	    mgmt_gpio_outr <= 'd0;
 	end else begin
 	    iomem_ready <= 0;
 	    if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
 		iomem_ready <= 1'b 1;
 
-		if (io_data_sel) begin
-		    iomem_rdata <= mgmt_gpio_in;
-		    if (iomem_wstrb[0]) begin
-			mgmt_gpio_outr[IO_PADS-1:0] <= iomem_wdata[IO_PADS-1:0];
-		    end
-
-		end else if (xfer_sel) begin
+		if (xfer_sel) begin
 		    iomem_rdata <= {31'd0, busy};
 		    if (iomem_wstrb[0]) xfer_ctrl <= iomem_wdata[0];
 		end
@@ -161,6 +163,33 @@
 	end
     end
 
+    // I/O transfer of gpio data to/from user project region under management
+    // SoC control
+
+    `define wtop (((i+1)*32 > IO_PADS) ? IO_PADS-1 : (i+1)*32-1)
+    `define wbot (i*32)
+    `define rtop (`wtop - `wbot + 1)
+
+    generate 
+        for (i=0; i<IO_WORDS; i=i+1) begin
+	    always @(posedge clk) begin
+		if (!resetn) begin
+		    mgmt_gpio_outr[`wtop:`wbot] <= 'd0;
+		end else begin
+		    if (iomem_valid && !iomem_ready && iomem_addr[31:8] ==
+					BASE_ADR[31:8]) begin
+			if (io_data_sel[i]) begin
+			    iomem_rdata[`rtop:0] <= mgmt_gpio_in[`wtop:`wbot];
+			    if (iomem_wstrb[0]) begin
+				mgmt_gpio_outr[`wtop:`wbot] <= iomem_wdata[`rtop:0];
+			    end
+			end
+		    end
+		end
+	    end
+	end
+    endgenerate
+
     generate 
         for (i=0; i<IO_PADS; i=i+1) begin
              always @(posedge clk) begin
diff --git a/verilog/rtl/mprj_io.v b/verilog/rtl/mprj_io.v
index 32ae628..90f8400 100644
--- a/verilog/rtl/mprj_io.v
+++ b/verilog/rtl/mprj_io.v
@@ -1,7 +1,22 @@
-module mprj_io(
-    inout vdd3v3,
-    inout vdd1v8,
-    inout vss,
+module mprj_io #(
+    parameter AREA1PADS = 18	// Highest numbered pad in area 1
+) (
+    inout vddio,
+    inout vssio,
+    inout vdda,
+    inout vssa,
+    inout vccd,
+    inout vssd,
+
+    inout vdda1,
+    inout vdda2,
+    inout vssa1,
+    inout vssa2,
+    inout vccd1,
+    inout vccd2,
+    inout vssd1,
+    inout vssd2,
+
     input vddio_q,
     input vssio_q,
     input analog_a,
@@ -24,9 +39,69 @@
     input [`MPRJ_IO_PADS*3-1:0] dm,
     output [`MPRJ_IO_PADS-1:0] io_in
 );
-    `MPRJ_IO_PAD_V(io, io_in, io_out, `MPRJ_IO_PADS, 
-    		oeb, hldh_n, enh, inp_dis, ib_mode_sel,
-    		vtrip_sel, slow_sel, holdover,
-    		analog_en, analog_sel, analog_pol, dm);
+
+    wire [`MPRJ_IO_PADS-1:0] loop1_io;
+
+    s8iom0_gpiov2_pad  area1_io_pad [AREA1PADS - 1:0] (
+	`USER1_ABUTMENT_PINS
+	`ifndef	TOP_ROUTING
+	    .pad(io[AREA1PADS - 1:0]),
+	`endif
+	    .out(io_out[AREA1PADS - 1:0]),
+	    .oe_n(oeb[AREA1PADS - 1:0]),
+	    .hld_h_n(hldh_n[AREA1PADS - 1:0]),
+	    .enable_h(enh[AREA1PADS - 1:0]),
+	    .enable_inp_h(loop1_io[AREA1PADS - 1:0]),
+	    .enable_vdda_h(porb_h),
+	    .enable_vswitch_h(vssa),
+	    .enable_vddio(vccd),
+	    .inp_dis(inp_dis[AREA1PADS - 1:0]),
+	    .ib_mode_sel(ib_mode_sel[AREA1PADS - 1:0]),
+	    .vtrip_sel(vtrip_sel[AREA1PADS - 1:0]),
+	    .slow(slow_sel[AREA1PADS - 1:0]),
+	    .hld_ovr(holdover[AREA1PADS - 1:0]),
+	    .analog_en(analog_en[AREA1PADS - 1:0]),
+	    .analog_sel(analog_sel[AREA1PADS - 1:0]),
+	    .analog_pol(analog_pol[AREA1PADS - 1:0]),
+	    .dm(dm[AREA1PADS*3 - 1:0]),
+	    .pad_a_noesd_h(),
+	    .pad_a_esd_0_h(),
+	    .pad_a_esd_1_h(),
+	    .in(io_in[AREA1PADS - 1:0]),
+	    .in_h(),
+	    .tie_hi_esd(),
+	    .tie_lo_esd(loop1_io[AREA1PADS - 1:0])
+    );
+
+    s8iom0_gpiov2_pad area2_io_pad [`MPRJ_IO_PADS - AREA1PADS - 1:0] (
+	`USER2_ABUTMENT_PINS
+	`ifndef	TOP_ROUTING
+	    .pad(io[`MPRJ_IO_PADS - AREA1PADS - 1:0]),
+	`endif
+	    .out(io_out[`MPRJ_IO_PADS - 1:AREA1PADS]),
+	    .oe_n(oeb[`MPRJ_IO_PADS - 1:AREA1PADS]),
+	    .hld_h_n(hldh_n[`MPRJ_IO_PADS - 1:AREA1PADS]),
+	    .enable_h(enh[`MPRJ_IO_PADS - 1:AREA1PADS]),
+	    .enable_inp_h(loop1_io[`MPRJ_IO_PADS - 1:AREA1PADS]),
+	    .enable_vdda_h(porb_h),
+	    .enable_vswitch_h(vssa),
+	    .enable_vddio(vccd),
+	    .inp_dis(inp_dis[`MPRJ_IO_PADS - 1:AREA1PADS]),
+	    .ib_mode_sel(ib_mode_sel[`MPRJ_IO_PADS - 1:AREA1PADS]),
+	    .vtrip_sel(vtrip_sel[`MPRJ_IO_PADS - 1:AREA1PADS]),
+	    .slow(slow_sel[`MPRJ_IO_PADS - 1:AREA1PADS]),
+	    .hld_ovr(holdover[`MPRJ_IO_PADS - 1:AREA1PADS]),
+	    .analog_en(analog_en[`MPRJ_IO_PADS - 1:AREA1PADS]),
+	    .analog_sel(analog_sel[`MPRJ_IO_PADS - 1:AREA1PADS]),
+	    .analog_pol(analog_pol[`MPRJ_IO_PADS - 1:AREA1PADS]),
+	    .dm(dm[`MPRJ_IO_PADS*3 - 1:AREA1PADS*3]),
+	    .pad_a_noesd_h(),
+	    .pad_a_esd_0_h(),
+	    .pad_a_esd_1_h(),
+	    .in(io_in[`MPRJ_IO_PADS - 1:AREA1PADS]),
+	    .in_h(),
+	    .tie_hi_esd(),
+	    .tie_lo_esd(loop1_io[`MPRJ_IO_PADS - 1:AREA1PADS])
+    );
 
 endmodule
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index 472f6ec..b17bf1d 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -1,45 +1,86 @@
 `ifndef TOP_ROUTING 
-	`define ABUTMENT_PINS \
+	`define USER1_ABUTMENT_PINS \
 	.amuxbus_a(analog_a),\
 	.amuxbus_b(analog_b),\
-	.vssa(vss),\
-	.vdda(vdd3v3),\
-	.vswitch(vdd3v3),\
+	.vssa(vssa1),\
+	.vdda(vdda1),\
+	.vswitch(vddio),\
 	.vddio_q(vddio_q),\
-	.vcchib(vdd1v8),\
-	.vddio(vdd3v3),\
-	.vccd(vdd1v8),\
-	.vssio(vss),\
-	.vssd(vss),\
+	.vcchib(vccd),\
+	.vddio(vddio),\
+	.vccd(vccd1),\
+	.vssio(vssio),\
+	.vssd(vssd1),\
+	.vssio_q(vssio_q),
+
+	`define USER2_ABUTMENT_PINS \
+	.amuxbus_a(analog_a),\
+	.amuxbus_b(analog_b),\
+	.vssa(vssa2),\
+	.vdda(vdda2),\
+	.vswitch(vddio),\
+	.vddio_q(vddio_q),\
+	.vcchib(vccd),\
+	.vddio(vddio),\
+	.vccd(vccd2),\
+	.vssio(vssio),\
+	.vssd(vssd2),\
+	.vssio_q(vssio_q),
+
+	`define MGMT_ABUTMENT_PINS \
+	.amuxbus_a(analog_a),\
+	.amuxbus_b(analog_b),\
+	.vssa(vssa),\
+	.vdda(vdda),\
+	.vswitch(vddio),\
+	.vddio_q(vddio_q),\
+	.vcchib(vccd),\
+	.vddio(vddio),\
+	.vccd(vccd),\
+	.vssio(vssio),\
+	.vssd(vssa),\
 	.vssio_q(vssio_q),
 `else 
-	`define ABUTMENT_PINS 
+	`define USER1_ABUTMENT_PINS 
+	`define USER2_ABUTMENT_PINS 
+	`define MGMT_ABUTMENT_PINS 
 `endif
 
+`define HVCLAMP_PINS \
+	.drn_hvc(), \
+	.src_bdy_hvc()
+
+`define LVCLAMP_PINS \
+	.bdy2_b2b(), \
+	.drn_lvc1(), \
+	.drn_lvc2(), \
+	.src_bdy_lvc1(), \
+	.src_bdy_lvc2()
+
 `define INPUT_PAD(X,Y) \
 	wire loop_``X; \
 	s8iom0_gpiov2_pad X``_pad ( \
-	`ABUTMENT_PINS \
+	`MGMT_ABUTMENT_PINS \
 	`ifndef	TOP_ROUTING \
 		.pad(X), \
 	`endif	\
-		.out(vss),	\
-		.oe_n(vdd1v8), \
-		.hld_h_n(vdd3v3),	\
+		.out(vssa),	\
+		.oe_n(vccd), \
+		.hld_h_n(vddio),	\
 		.enable_h(porb_h), \
 		.enable_inp_h(loop_``X), \
 		.enable_vdda_h(porb_h), \
-		.enable_vswitch_h(vss), \
-		.enable_vddio(vdd1v8), \
+		.enable_vswitch_h(vssa), \
+		.enable_vddio(vccd), \
 		.inp_dis(por), \
-		.ib_mode_sel(vss), \
-		.vtrip_sel(vss), \
-		.slow(vss),	\
-		.hld_ovr(vss), \
-		.analog_en(vss), \
-		.analog_sel(vss), \
-		.analog_pol(vss), \
-		.dm({vss, vss, vdd1v8}), \
+		.ib_mode_sel(vssa), \
+		.vtrip_sel(vssa), \
+		.slow(vssa),	\
+		.hld_ovr(vssa), \
+		.analog_en(vssa), \
+		.analog_sel(vssa), \
+		.analog_pol(vssa), \
+		.dm({vssa, vssa, vccd}), \
 		.pad_a_noesd_h(), \
 		.pad_a_esd_0_h(), \
 		.pad_a_esd_1_h(), \
@@ -48,94 +89,30 @@
 		.tie_hi_esd(), \
 		.tie_lo_esd(loop_``X) ) 
 
-`define INPUT_PAD_ANALOG(X,SEL,POL) \
-	wire loop_``X; \
-	s8iom0_gpiov2_pad X``_pad ( \
-	`ABUTMENT_PINS \
-	`ifndef	TOP_ROUTING \
-		.pad(X), \
-	`endif	\
-		.out(vss),	\
-		.oe_n(vdd1v8), \
-		.hld_h_n(vdd3v3),	\
-		.enable_h(porb_h), \
-		.enable_inp_h(loop_``X), \
-		.enable_vdda_h(porb_h), \
-		.enable_vswitch_h(vss), \
-		.enable_vddio(vdd1v8), \
-		.inp_dis(vdd1v8), \
-		.ib_mode_sel(vss), \
-		.vtrip_sel(vss), \
-		.slow(vss),	\
-		.hld_ovr(vss), \
-		.analog_en(vdd1v8), \
-		.analog_sel(SEL), \
-		.analog_pol(POL), \
-		.dm({vss, vss, vss}), \
-		.pad_a_noesd_h(), \
-		.pad_a_esd_0_h(), \
-		.pad_a_esd_1_h(), \
-		.in(), \
-		.in_h(), \
-		.tie_hi_esd(), \
-		.tie_lo_esd() ) 
-
-`define INPUT_PAD_V(X,Y,V) \
-	wire [V-1:0] loop_``X; \
-	s8iom0_gpiov2_pad X``_pad [V-1:0] ( \
-	`ABUTMENT_PINS \
-	`ifndef	TOP_ROUTING \
-		.pad(X),\
-	`endif	\
-		.out(),	\
-		.oe_n(vdd1v8), \
-		.hld_h_n(vdd3v3),	\
-		.enable_h(vdd3v3), \
-		.enable_inp_h(loop_``X), \
-		.enable_vdda_h(vdd3v3), \
-		.enable_vswitch_h(vss), \
-		.enable_vddio(vdd1v8), \
-		.inp_dis(por), \
-		.ib_mode_sel(vss), \
-		.vtrip_sel(vss), \
-		.slow(vss),	\
-		.hld_ovr(vss), \
-		.analog_en(vss), \
-		.analog_sel(vss), \
-		.analog_pol(vss), \
-		.dm({vss, vss, vdd1v8}), \
-		.pad_a_noesd_h(), \
-		.pad_a_esd_0_h(), \
-		.pad_a_esd_1_h(), \
-		.in(Y),  \
-		.in_h(), \
-		.tie_hi_esd(), \
-		.tie_lo_esd(loop_``X) )
-	
 `define OUTPUT_PAD(X,Y,INP_DIS,OUT_EN_N) \
 	wire loop_``X; \
 	s8iom0_gpiov2_pad X``_pad ( \
-	`ABUTMENT_PINS \
+	`MGMT_ABUTMENT_PINS \
 	`ifndef	TOP_ROUTING \
 		.pad(X), \
 	`endif \
 		.out(Y), \
 		.oe_n(OUT_EN_N), \
-		.hld_h_n(vdd3v3), \
+		.hld_h_n(vddio), \
 		.enable_h(porb_h),	\
 		.enable_inp_h(loop_``X), \
 		.enable_vdda_h(porb_h), \
-		.enable_vswitch_h(vss), \
-		.enable_vddio(vdd1v8), \
+		.enable_vswitch_h(vssa), \
+		.enable_vddio(vccd), \
 		.inp_dis(INP_DIS), \
-		.ib_mode_sel(vss), \
-		.vtrip_sel(vss), \
-		.slow(vss),	\
-		.hld_ovr(vss), \
-		.analog_en(vss), \
-		.analog_sel(vss), \
-		.analog_pol(vss), \
-		.dm({vdd1v8, vdd1v8, vss}),	\
+		.ib_mode_sel(vssa), \
+		.vtrip_sel(vssa), \
+		.slow(vssa),	\
+		.hld_ovr(vssa), \
+		.analog_en(vssa), \
+		.analog_sel(vssa), \
+		.analog_pol(vssa), \
+		.dm({vccd, vccd, vssa}),	\
 		.pad_a_noesd_h(), \
 		.pad_a_esd_0_h(), \
 		.pad_a_esd_1_h(), \
@@ -144,60 +121,28 @@
 		.tie_hi_esd(), \
 		.tie_lo_esd(loop_``X)) 
 
-`define INOUT_PAD_V(X,Y,Y_OUT,V,INP_DIS,OUT_EN_N,MODE) \
-	wire [V-1:0] loop_``X; \
-	s8iom0_gpiov2_pad X``_pad [V-1:0] ( \
-	`ABUTMENT_PINS \
-	`ifndef	TOP_ROUTING \
-		.pad(X),\
-	`endif	\
-		.out(Y_OUT),	\
-		.oe_n(OUT_EN_N), \
-		.hld_h_n(vdd3v3),	\
-		.enable_h(porb_h), \
-		.enable_inp_h(loop_``X), \
-		.enable_vdda_h(porb_h), \
-		.enable_vswitch_h(vss), \
-		.enable_vddio(vdd1v8), \
-		.inp_dis(INP_DIS), \
-		.ib_mode_sel(vss), \
-		.vtrip_sel(vss), \
-		.slow(vss),	\
-		.hld_ovr(vss), \
-		.analog_en(vss), \
-		.analog_sel(vss), \
-		.analog_pol(vss), \
-		.dm(MODE), \
-		.pad_a_noesd_h(), \
-		.pad_a_esd_0_h(), \
-		.pad_a_esd_1_h(), \
-		.in(Y),  \
-		.in_h(), \
-		.tie_hi_esd(), \
-		.tie_lo_esd(loop_``X) )
-
 `define INOUT_PAD(X,Y,Y_OUT,INP_DIS,OUT_EN_N,MODE) \
 	s8iom0_gpiov2_pad X``_pad ( \
-	`ABUTMENT_PINS \
+	`MGMT_ABUTMENT_PINS \
 	`ifndef	TOP_ROUTING \
 		.pad(X),\
 	`endif	\
 		.out(Y_OUT),	\
 		.oe_n(OUT_EN_N), \
-		.hld_h_n(vdd3v3),	\
+		.hld_h_n(vddio),	\
 		.enable_h(porb_h), \
 		.enable_inp_h(loop_``X), \
 		.enable_vdda_h(porb_h), \
-		.enable_vswitch_h(vss), \
-		.enable_vddio(vdd1v8), \
+		.enable_vswitch_h(vssa), \
+		.enable_vddio(vccd), \
 		.inp_dis(INP_DIS), \
-		.ib_mode_sel(vss), \
-		.vtrip_sel(vss), \
-		.slow(vss),	\
-		.hld_ovr(vss), \
-		.analog_en(vss), \
-		.analog_sel(vss), \
-		.analog_pol(vss), \
+		.ib_mode_sel(vssa), \
+		.vtrip_sel(vssa), \
+		.slow(vssa),	\
+		.hld_ovr(vssa), \
+		.analog_en(vssa), \
+		.analog_sel(vssa), \
+		.analog_pol(vssa), \
 		.dm(MODE), \
 		.pad_a_noesd_h(), \
 		.pad_a_esd_0_h(), \
@@ -207,34 +152,3 @@
 		.tie_hi_esd(), \
 		.tie_lo_esd(loop_``X) )
 
-`define MPRJ_IO_PAD_V(X,Y,Y_OUT,V,OUT_EN_N,HLD_N, ENH, INP_DIS, MODE_SEL, VTRIP_SEL, SLOW_SEL, HOLD_SEL, AN_EN, AN_SEL, AN_POL, MODE) \
-	wire [V-1:0] loop_``X; \
-	s8iom0_gpiov2_pad  X``_pad [V-1:0] ( \
-	`ABUTMENT_PINS \
-	`ifndef	TOP_ROUTING \
-		.pad(X),\
-	`endif	\
-		.out(Y_OUT),	\
-		.oe_n(OUT_EN_N), \
-		.hld_h_n(HLD_N),	\
-		.enable_h(ENH), \
-		.enable_inp_h(loop_``X), \
-		.enable_vdda_h(porb_h), \
-		.enable_vswitch_h(vss), \
-		.enable_vddio(vdd1v8), \
-		.inp_dis(INP_DIS), \
-		.ib_mode_sel(MODE_SEL), \
-		.vtrip_sel(VTRIP_SEL), \
-		.slow(SLOW_SEL),	\
-		.hld_ovr(HOLD_SEL), \
-		.analog_en(AN_EN), \
-		.analog_sel(AN_SEL), \
-		.analog_pol(AN_POL), \
-		.dm(MODE), \
-		.pad_a_noesd_h(), \
-		.pad_a_esd_0_h(), \
-		.pad_a_esd_1_h(), \
-		.in(Y),  \
-		.in_h(), \
-		.tie_hi_esd(), \
-		.tie_lo_esd(loop_``X) )
diff --git a/verilog/rtl/test.v b/verilog/rtl/test.v
new file mode 100644
index 0000000..25a3197
--- /dev/null
+++ b/verilog/rtl/test.v
@@ -0,0 +1,63 @@
+`define MPRJ1_IO_PAD_V(X,Y,Y_OUT,V,OUT_EN_N,HLD_N, ENH, INP_DIS, MODE_SEL, VTRIP_SEL, SLOW_SEL, HOLD_SEL, AN_EN, AN_SEL, AN_POL, MODE) \
+	wire [V-1:0] loop1_``X; \
+	s8iom0_gpiov2_pad  X``_pad [V-1:0] ( \
+	`USER1_ABUTMENT_PINS \
+	`ifndef	TOP_ROUTING \
+		.pad(X),\
+	`endif	\
+		.out(Y_OUT),	\
+		.oe_n(OUT_EN_N), \
+		.hld_h_n(HLD_N),	\
+		.enable_h(ENH), \
+		.enable_inp_h(loop1_``X), \
+		.enable_vdda_h(porb_h), \
+		.enable_vswitch_h(vssa), \
+		.enable_vddio(vccd), \
+		.inp_dis(INP_DIS), \
+		.ib_mode_sel(MODE_SEL), \
+		.vtrip_sel(VTRIP_SEL), \
+		.slow(SLOW_SEL),	\
+		.hld_ovr(HOLD_SEL), \
+		.analog_en(AN_EN), \
+		.analog_sel(AN_SEL), \
+		.analog_pol(AN_POL), \
+		.dm(MODE), \
+		.pad_a_noesd_h(), \
+		.pad_a_esd_0_h(), \
+		.pad_a_esd_1_h(), \
+		.in(Y),  \
+		.in_h(), \
+		.tie_hi_esd(), \
+		.tie_lo_esd(loop1_``X) )
+
+`define MPRJ2_IO_PAD_V(X,Y,Y_OUT,V,OUT_EN_N,HLD_N, ENH, INP_DIS, MODE_SEL, VTRIP_SEL, SLOW_SEL, HOLD_SEL, AN_EN, AN_SEL, AN_POL, MODE) \
+	wire [V-1:0] loop2_``X; \
+	s8iom0_gpiov2_pad  X``_pad [V-1:0] ( \
+	`USER2_ABUTMENT_PINS \
+	`ifndef	TOP_ROUTING \
+		.pad(X),\
+	`endif	\
+		.out(Y_OUT),	\
+		.oe_n(OUT_EN_N), \
+		.hld_h_n(HLD_N),	\
+		.enable_h(ENH), \
+		.enable_inp_h(loop2_``X), \
+		.enable_vdda_h(porb_h), \
+		.enable_vswitch_h(vssa), \
+		.enable_vddio(vccd), \
+		.inp_dis(INP_DIS), \
+		.ib_mode_sel(MODE_SEL), \
+		.vtrip_sel(VTRIP_SEL), \
+		.slow(SLOW_SEL),	\
+		.hld_ovr(HOLD_SEL), \
+		.analog_en(AN_EN), \
+		.analog_sel(AN_SEL), \
+		.analog_pol(AN_POL), \
+		.dm(MODE), \
+		.pad_a_noesd_h(), \
+		.pad_a_esd_0_h(), \
+		.pad_a_esd_1_h(), \
+		.in(Y),  \
+		.in_h(), \
+		.tie_hi_esd(), \
+		.tie_lo_esd(loop2_``X) )
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index af198c4..742977c 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -20,9 +20,21 @@
  */
 
 module user_proj_example #(
-    parameter IO_PADS = 32,
+    parameter IO_PADS = 37,
+    parameter PWR_PADS = 4,
     parameter BITS = 32
 )(
+`ifdef LVS
+    inout vdda1,	// User area 1 3.3V supply
+    inout vdda2,	// User area 2 3.3V supply
+    inout vssa1,	// User area 1 analog ground
+    inout vssa2,	// User area 2 analog ground
+    inout vccd1,	// User area 1 1.8V supply
+    inout vccd2,	// User area 2 1.8v supply
+    inout vssd1,	// User area 1 digital ground
+    inout vssd2,	// User area 2 digital ground
+`endif
+
     // Wishbone Slave ports (WB MI A)
     input wb_clk_i,
     input wb_rst_i,