diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index bd359b9..82df32d 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -4,12 +4,12 @@
     	inout  vdd1v8,
     	inout  vss,
 	inout  gpio,
-	inout  clock,
-	inout  resetb,
+	input  clock,
+	input  resetb,
 	output flash_csb,
 	output flash_clk,
-	output flash_io0,
-	output flash_io1,
+	inout  flash_io0,
+	inout  flash_io1,
 	// Chip Core Interface
 	output porb_h,
 	output clock_core,
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index ad2ac30..472f6ec 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -7,7 +7,7 @@
 	.vswitch(vdd3v3),\
 	.vddio_q(vddio_q),\
 	.vcchib(vdd1v8),\
-	.vddio(vdd),\
+	.vddio(vdd3v3),\
 	.vccd(vdd1v8),\
 	.vssio(vss),\
 	.vssd(vss),\