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agorararmarde5780bf2020-12-09 21:27:56 +00001// Copyright 2020 Efabless Corporation
2//
3// Licensed under the Apache License, Version 2.0 (the "License");
4// you may not use this file except in compliance with the License.
5// You may obtain a copy of the License at
6//
7// http://www.apache.org/licenses/LICENSE-2.0
8//
9// Unless required by applicable law or agreed to in writing, software
10// distributed under the License is distributed on an "AS IS" BASIS,
11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12// See the License for the specific language governing permissions and
13// limitations under the License.
14
Matt Venn08cd6eb2020-11-16 12:01:14 +010015`default_nettype none
Tim Edwards21a9aac2020-10-12 22:05:18 -040016`timescale 1 ns / 1 ps
17
Tim Edwardsf51dd082020-10-05 16:30:24 -040018module simple_por(
Ahmed Ghazy27200e92020-11-25 22:07:02 +020019`ifdef USE_POWER_PINS
Ahmed Ghazy69663c72020-11-18 20:15:53 +020020 inout vdd3v3,
21 inout vdd1v8,
22 inout vss,
Ahmed Ghazy27200e92020-11-25 22:07:02 +020023`endif
Ahmed Ghazy69663c72020-11-18 20:15:53 +020024 output porb_h,
25 output porb_l,
26 output por_l
Tim Edwardsf51dd082020-10-05 16:30:24 -040027);
28
29 wire mid, porb_h;
30 reg inode;
31
32 // This is a behavioral model! Actual circuit is a resitor dumping
33 // current (slowly) from vdd3v3 onto a capacitor, and this fed into
34 // two schmitt triggers for strong hysteresis/glitch tolerance.
35
36 initial begin
Tim Edwards21a9aac2020-10-12 22:05:18 -040037 inode <= 1'b0;
Tim Edwardsf51dd082020-10-05 16:30:24 -040038 end
39
40 // Emulate current source on capacitor as a 500ns delay either up or
Tim Edwards10708322020-11-20 13:55:57 -050041 // down. Note that this is sped way up for verilog simulation; the
42 // actual circuit is set to a 15ms delay.
Tim Edwardsf51dd082020-10-05 16:30:24 -040043
44 always @(posedge vdd3v3) begin
45 #500 inode <= 1'b1;
46 end
47 always @(negedge vdd3v3) begin
48 #500 inode <= 1'b0;
49 end
50
51 // Instantiate two shmitt trigger buffers in series
52
Ahmed Ghazy69663c72020-11-18 20:15:53 +020053 sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
54`ifdef USE_POWER_PINS
Tim Edwardsf51dd082020-10-05 16:30:24 -040055 .VPWR(vdd3v3),
56 .VGND(vss),
57 .VPB(vdd3v3),
58 .VNB(vss),
Ahmed Ghazy69663c72020-11-18 20:15:53 +020059`endif
Tim Edwardsf51dd082020-10-05 16:30:24 -040060 .A(inode),
61 .X(mid)
62 );
63
Ahmed Ghazy69663c72020-11-18 20:15:53 +020064 sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
65`ifdef USE_POWER_PINS
Tim Edwardsf51dd082020-10-05 16:30:24 -040066 .VPWR(vdd3v3),
67 .VGND(vss),
68 .VPB(vdd3v3),
69 .VNB(vss),
Ahmed Ghazy69663c72020-11-18 20:15:53 +020070`endif
Tim Edwardsf51dd082020-10-05 16:30:24 -040071 .A(mid),
72 .X(porb_h)
73 );
74
Ahmed Ghazy69663c72020-11-18 20:15:53 +020075 sky130_fd_sc_hvl__lsbufhv2lv_1 porb_level (
76`ifdef USE_POWER_PINS
77 .VPWR(vdd3v3),
78 .VPB(vdd3v3),
79 .LVPWR(vdd1v8),
80 .VNB(vss),
81 .VGND(vss),
82`endif
83 .A(porb_h),
84 .X(porb_l)
85 );
86
87 // since this is behavioral anyway, but this should be
88 // replaced by a proper inverter
Tim Edwards581068f2020-11-19 12:45:25 -050089 assign por_l = ~porb_l;
Tim Edwardsf51dd082020-10-05 16:30:24 -040090endmodule
Tim Edwards581068f2020-11-19 12:45:25 -050091`default_nettype wire