agorararmard | e5780bf | 2020-12-09 21:27:56 +0000 | [diff] [blame^] | 1 | // Copyright 2020 Efabless Corporation |
| 2 | // |
| 3 | // Licensed under the Apache License, Version 2.0 (the "License"); |
| 4 | // you may not use this file except in compliance with the License. |
| 5 | // You may obtain a copy of the License at |
| 6 | // |
| 7 | // http://www.apache.org/licenses/LICENSE-2.0 |
| 8 | // |
| 9 | // Unless required by applicable law or agreed to in writing, software |
| 10 | // distributed under the License is distributed on an "AS IS" BASIS, |
| 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 12 | // See the License for the specific language governing permissions and |
| 13 | // limitations under the License. |
| 14 | |
Matt Venn | 08cd6eb | 2020-11-16 12:01:14 +0100 | [diff] [blame] | 15 | `default_nettype none |
Tim Edwards | 21a9aac | 2020-10-12 22:05:18 -0400 | [diff] [blame] | 16 | `timescale 1 ns / 1 ps |
| 17 | |
Tim Edwards | f51dd08 | 2020-10-05 16:30:24 -0400 | [diff] [blame] | 18 | module simple_por( |
Ahmed Ghazy | 27200e9 | 2020-11-25 22:07:02 +0200 | [diff] [blame] | 19 | `ifdef USE_POWER_PINS |
Ahmed Ghazy | 69663c7 | 2020-11-18 20:15:53 +0200 | [diff] [blame] | 20 | inout vdd3v3, |
| 21 | inout vdd1v8, |
| 22 | inout vss, |
Ahmed Ghazy | 27200e9 | 2020-11-25 22:07:02 +0200 | [diff] [blame] | 23 | `endif |
Ahmed Ghazy | 69663c7 | 2020-11-18 20:15:53 +0200 | [diff] [blame] | 24 | output porb_h, |
| 25 | output porb_l, |
| 26 | output por_l |
Tim Edwards | f51dd08 | 2020-10-05 16:30:24 -0400 | [diff] [blame] | 27 | ); |
| 28 | |
| 29 | wire mid, porb_h; |
| 30 | reg inode; |
| 31 | |
| 32 | // This is a behavioral model! Actual circuit is a resitor dumping |
| 33 | // current (slowly) from vdd3v3 onto a capacitor, and this fed into |
| 34 | // two schmitt triggers for strong hysteresis/glitch tolerance. |
| 35 | |
| 36 | initial begin |
Tim Edwards | 21a9aac | 2020-10-12 22:05:18 -0400 | [diff] [blame] | 37 | inode <= 1'b0; |
Tim Edwards | f51dd08 | 2020-10-05 16:30:24 -0400 | [diff] [blame] | 38 | end |
| 39 | |
| 40 | // Emulate current source on capacitor as a 500ns delay either up or |
Tim Edwards | 1070832 | 2020-11-20 13:55:57 -0500 | [diff] [blame] | 41 | // down. Note that this is sped way up for verilog simulation; the |
| 42 | // actual circuit is set to a 15ms delay. |
Tim Edwards | f51dd08 | 2020-10-05 16:30:24 -0400 | [diff] [blame] | 43 | |
| 44 | always @(posedge vdd3v3) begin |
| 45 | #500 inode <= 1'b1; |
| 46 | end |
| 47 | always @(negedge vdd3v3) begin |
| 48 | #500 inode <= 1'b0; |
| 49 | end |
| 50 | |
| 51 | // Instantiate two shmitt trigger buffers in series |
| 52 | |
Ahmed Ghazy | 69663c7 | 2020-11-18 20:15:53 +0200 | [diff] [blame] | 53 | sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 ( |
| 54 | `ifdef USE_POWER_PINS |
Tim Edwards | f51dd08 | 2020-10-05 16:30:24 -0400 | [diff] [blame] | 55 | .VPWR(vdd3v3), |
| 56 | .VGND(vss), |
| 57 | .VPB(vdd3v3), |
| 58 | .VNB(vss), |
Ahmed Ghazy | 69663c7 | 2020-11-18 20:15:53 +0200 | [diff] [blame] | 59 | `endif |
Tim Edwards | f51dd08 | 2020-10-05 16:30:24 -0400 | [diff] [blame] | 60 | .A(inode), |
| 61 | .X(mid) |
| 62 | ); |
| 63 | |
Ahmed Ghazy | 69663c7 | 2020-11-18 20:15:53 +0200 | [diff] [blame] | 64 | sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 ( |
| 65 | `ifdef USE_POWER_PINS |
Tim Edwards | f51dd08 | 2020-10-05 16:30:24 -0400 | [diff] [blame] | 66 | .VPWR(vdd3v3), |
| 67 | .VGND(vss), |
| 68 | .VPB(vdd3v3), |
| 69 | .VNB(vss), |
Ahmed Ghazy | 69663c7 | 2020-11-18 20:15:53 +0200 | [diff] [blame] | 70 | `endif |
Tim Edwards | f51dd08 | 2020-10-05 16:30:24 -0400 | [diff] [blame] | 71 | .A(mid), |
| 72 | .X(porb_h) |
| 73 | ); |
| 74 | |
Ahmed Ghazy | 69663c7 | 2020-11-18 20:15:53 +0200 | [diff] [blame] | 75 | sky130_fd_sc_hvl__lsbufhv2lv_1 porb_level ( |
| 76 | `ifdef USE_POWER_PINS |
| 77 | .VPWR(vdd3v3), |
| 78 | .VPB(vdd3v3), |
| 79 | .LVPWR(vdd1v8), |
| 80 | .VNB(vss), |
| 81 | .VGND(vss), |
| 82 | `endif |
| 83 | .A(porb_h), |
| 84 | .X(porb_l) |
| 85 | ); |
| 86 | |
| 87 | // since this is behavioral anyway, but this should be |
| 88 | // replaced by a proper inverter |
Tim Edwards | 581068f | 2020-11-19 12:45:25 -0500 | [diff] [blame] | 89 | assign por_l = ~porb_l; |
Tim Edwards | f51dd08 | 2020-10-05 16:30:24 -0400 | [diff] [blame] | 90 | endmodule |
Tim Edwards | 581068f | 2020-11-19 12:45:25 -0500 | [diff] [blame] | 91 | `default_nettype wire |