diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 0bd8ab0..5cdd271 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -82,23 +82,10 @@
 
     vdp_lite_user_proj mprj (
 `ifdef USE_POWER_PINS
-    .vdda1(vdda1),  // User area 1 3.3V power
-    .vdda2(vdda2),  // User area 2 3.3V power
-    .vssa1(vssa1),  // User area 1 analog ground
-    .vssa2(vssa2),  // User area 2 analog ground
-    .vccd1(vccd1),  // User area 1 1.8V power
-    .vccd2(vccd2),  // User area 2 1.8V power
-    .vssd1(vssd1),  // User area 1 digital ground
-    .vssd2(vssd2),  // User area 2 digital ground
+    .VPWR(vccd1),
+    .VGND(vssd1),
 `endif
-
-    // This is just a convenience for sim to "power" the sky130 models
-    // It's expected that the common PDN config in openlane will configure for synth
-`ifdef GL_SIM
-    .VPWR(1'b1),
-    .VGND(1'b0),
-`endif
-    
+ 
     // MGMT core clock and reset
 
     .wb_clk_i(wb_clk_i),