diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 20eb097..ca6d3e9 100644
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -6,6 +6,7 @@
 	$script_dir/../../verilog/rtl/defines.v \
 	$script_dir/../../verilog/rtl/user_proj_example.v"
 
+set ::env(CLOCK_PORT) ""
 set ::env(CLOCK_NET) "counter.clk"
 set ::env(CLOCK_PERIOD) "10"
 
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
index a1b085c..394f62b 100644
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -10,15 +10,40 @@
 
 place_io_ol
 
+set ::env(FP_DEF_TEMPATE) $script_dir/../../def/user_project_wrapper_empty.def
+
+apply_def_template
+
 add_macro_placement mprj 1150 1700 N
 
 manual_macro_placement f
 
-set ::env(PDN_CFG) $script_dir/pdn1.tcl
-gen_pdn
+set ::env(_SPACING) 1.6
+set ::env(_WIDTH) 3
 
-set ::env(PDN_CFG) $script_dir/pdn2.tcl
-gen_pdn
+set power_domains [list {vccd1 vssd1} {vccd2 vssd2} {vdda1 vssa1} {vdda2 vssa2}]
+
+set ::env(_VDD_NET_NAME) vccd1
+set ::env(_GND_NET_NAME) vssd1
+set ::env(_V_OFFSET) 14
+set ::env(_H_OFFSET) $::env(_V_OFFSET)
+set ::env(_V_PITCH) 180
+set ::env(_H_PITCH) 180
+set ::env(_V_PDN_OFFSET) 0
+set ::env(_H_PDN_OFFSET) 0
+
+foreach domain $power_domains {
+	set ::env(_VDD_NET_NAME) [lindex $domain 0]
+	set ::env(_GND_NET_NAME) [lindex $domain 1]
+	gen_pdn
+
+	set ::env(_V_OFFSET) \
+	[expr $::env(_V_OFFSET) + 2*($::env(_WIDTH)+$::env(_SPACING))]
+	set ::env(_H_OFFSET) \
+	[expr $::env(_H_OFFSET) + 2*($::env(_WIDTH)+$::env(_SPACING))]
+	set ::env(_V_PDN_OFFSET) [expr $::env(_V_PDN_OFFSET)+6*$::env(_WIDTH)]
+	set ::env(_H_PDN_OFFSET) [expr $::env(_H_PDN_OFFSET)+6*$::env(_WIDTH)]
+}
 
 global_routing_or
 detailed_routing