)]}'
{
  "commit": "fc7e6ae4b87cf45a6f4a19cc980013efee9b2c13",
  "tree": "0e0d2ad8bf71955df81452320e7366feea43d48e",
  "parents": [
    "0565c08c1c1adaad2893fe2ba11aed657f0aff37"
  ],
  "author": {
    "name": "Mohamed Shalan",
    "email": "mshalan@aucegypt.edu",
    "time": "Wed Jan 20 15:14:01 2021 +0200"
  },
  "committer": {
    "name": "Mohamed Shalan",
    "email": "mshalan@aucegypt.edu",
    "time": "Wed Jan 20 15:14:01 2021 +0200"
  },
  "message": "Fixed a typo\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1b65721381a0243306010ce505207509ef41d851",
      "old_mode": 33188,
      "old_path": "verilog/rtl/RAM_6Kx32.v",
      "new_id": "c054ec19cc8136abd3176a678975fc456d1e9a0e",
      "new_mode": 33188,
      "new_path": "verilog/rtl/RAM_6Kx32.v"
    }
  ]
}