)]}'
{
  "commit": "e2a3da9ae85991c46eb7dbe972aa1302e7f091ad",
  "tree": "af12dbe629af3dc1b41cf7cc975b5643ef7a3709",
  "parents": [
    "fc7e6ae4b87cf45a6f4a19cc980013efee9b2c13"
  ],
  "author": {
    "name": "Mohamed Shalan",
    "email": "mshalan@aucegypt.edu",
    "time": "Wed Jan 20 15:56:20 2021 +0200"
  },
  "committer": {
    "name": "Mohamed Shalan",
    "email": "mshalan@aucegypt.edu",
    "time": "Wed Jan 20 15:56:20 2021 +0200"
  },
  "message": "Changed the number of columns to 4\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a218d2aeeb34d3b19d4f59ec9dc4eb7d9f73daa8",
      "old_mode": 33188,
      "old_path": "verilog/rtl/RAM_2x4KB.v",
      "new_id": "41d5a2e4fb64156a588cc00b35d6eddb46d7bf05",
      "new_mode": 33188,
      "new_path": "verilog/rtl/RAM_2x4KB.v"
    }
  ]
}