)]}'
{
  "commit": "bd68154bca67f977f0ab4eacb0452633a2dfad6d",
  "tree": "bf3d58008208161358c07b79a85fd1981d57d524",
  "parents": [
    "ceeee462c77216e87181802a8bc28587e522e96d"
  ],
  "author": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Wed Jan 20 17:37:24 2021 +0200"
  },
  "committer": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Wed Jan 20 17:37:24 2021 +0200"
  },
  "message": "Added power pins (needed for sim)\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "73ad0ad3f31c7ea9cd72d14c4533a0970ea8fabe",
      "old_mode": 33188,
      "old_path": "verilog/rtl/DFFRAM.v",
      "new_id": "8c314c94ccc31ebb226478427e7f7e698bad4fed",
      "new_mode": 33188,
      "new_path": "verilog/rtl/DFFRAM.v"
    },
    {
      "type": "modify",
      "old_id": "41da41dc7c18464521eacc75dd6b1be3e9328052",
      "old_mode": 33188,
      "old_path": "verilog/rtl/DFFRAMBB.v",
      "new_id": "554325dcc3f179367701d04d75420b99890dfa18",
      "new_mode": 33188,
      "new_path": "verilog/rtl/DFFRAMBB.v"
    },
    {
      "type": "modify",
      "old_id": "1b7636236132cbf7300eae0465ea44f7d3d75372",
      "old_mode": 33188,
      "old_path": "verilog/rtl/DFFRAM_4KB-.v",
      "new_id": "4b14729b65ac13adee4fd3cb508dbd1254654d08",
      "new_mode": 33188,
      "new_path": "verilog/rtl/DFFRAM_4KB-.v"
    },
    {
      "type": "modify",
      "old_id": "e70cbd1943fd71c5c9738f3b0564d443051971ad",
      "old_mode": 33188,
      "old_path": "verilog/rtl/DFFRAM_4KB.v",
      "new_id": "fef79a6cbf961a0f3282eaed33d1d9cbcbf0e7bf",
      "new_mode": 33188,
      "new_path": "verilog/rtl/DFFRAM_4KB.v"
    },
    {
      "type": "modify",
      "old_id": "41d5a2e4fb64156a588cc00b35d6eddb46d7bf05",
      "old_mode": 33188,
      "old_path": "verilog/rtl/RAM_2x4KB.v",
      "new_id": "4481cd6fe858a263031b23f4178c3af942e73ff5",
      "new_mode": 33188,
      "new_path": "verilog/rtl/RAM_2x4KB.v"
    }
  ]
}
