diff --git a/def/RAM_2x4KB.def.gz b/def/RAM_2x4KB.def.gz
new file mode 100644
index 0000000..60943b2
--- /dev/null
+++ b/def/RAM_2x4KB.def.gz
Binary files differ
diff --git a/gds/RAM_2x4KB.gds.gz.00.split b/gds/RAM_2x4KB.gds.gz.00.split
new file mode 100644
index 0000000..4ab7a64
--- /dev/null
+++ b/gds/RAM_2x4KB.gds.gz.00.split
Binary files differ
diff --git a/gds/RAM_2x4KB.gds.gz.01.split b/gds/RAM_2x4KB.gds.gz.01.split
new file mode 100644
index 0000000..ccafead
--- /dev/null
+++ b/gds/RAM_2x4KB.gds.gz.01.split
Binary files differ
diff --git a/lef/RAM_2x4KB.lef b/lef/RAM_2x4KB.lef
new file mode 100644
index 0000000..266e3d6
--- /dev/null
+++ b/lef/RAM_2x4KB.lef
@@ -0,0 +1,863 @@
+VERSION 5.7 ;
+  NOWIREEXTENSIONATPIN ON ;
+  DIVIDERCHAR "/" ;
+  BUSBITCHARS "[]" ;
+MACRO RAM_2x4KB
+  CLASS BLOCK ;
+  FOREIGN RAM_2x4KB ;
+  ORIGIN 0.000 0.000 ;
+  SIZE 950.000 BY 3100.000 ;
+  PIN A[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 755.870 0.000 756.150 4.000 ;
+    END
+  END A[0]
+  PIN A[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 873.170 0.000 873.450 4.000 ;
+    END
+  END A[10]
+  PIN A[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 767.830 0.000 768.110 4.000 ;
+    END
+  END A[1]
+  PIN A[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 779.330 0.000 779.610 4.000 ;
+    END
+  END A[2]
+  PIN A[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 791.290 0.000 791.570 4.000 ;
+    END
+  END A[3]
+  PIN A[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 802.790 0.000 803.070 4.000 ;
+    END
+  END A[4]
+  PIN A[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 814.750 0.000 815.030 4.000 ;
+    END
+  END A[5]
+  PIN A[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 826.250 0.000 826.530 4.000 ;
+    END
+  END A[6]
+  PIN A[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 838.210 0.000 838.490 4.000 ;
+    END
+  END A[7]
+  PIN A[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 849.710 0.000 849.990 4.000 ;
+    END
+  END A[8]
+  PIN A[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 861.670 0.000 861.950 4.000 ;
+    END
+  END A[9]
+  PIN CLK
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 885.130 0.000 885.410 4.000 ;
+    END
+  END CLK
+  PIN Di[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 380.510 0.000 380.790 4.000 ;
+    END
+  END Di[0]
+  PIN Di[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 497.810 0.000 498.090 4.000 ;
+    END
+  END Di[10]
+  PIN Di[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 509.770 0.000 510.050 4.000 ;
+    END
+  END Di[11]
+  PIN Di[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 521.270 0.000 521.550 4.000 ;
+    END
+  END Di[12]
+  PIN Di[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 533.230 0.000 533.510 4.000 ;
+    END
+  END Di[13]
+  PIN Di[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 544.730 0.000 545.010 4.000 ;
+    END
+  END Di[14]
+  PIN Di[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 556.690 0.000 556.970 4.000 ;
+    END
+  END Di[15]
+  PIN Di[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 568.190 0.000 568.470 4.000 ;
+    END
+  END Di[16]
+  PIN Di[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 580.150 0.000 580.430 4.000 ;
+    END
+  END Di[17]
+  PIN Di[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 591.650 0.000 591.930 4.000 ;
+    END
+  END Di[18]
+  PIN Di[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 603.610 0.000 603.890 4.000 ;
+    END
+  END Di[19]
+  PIN Di[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 392.470 0.000 392.750 4.000 ;
+    END
+  END Di[1]
+  PIN Di[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 615.110 0.000 615.390 4.000 ;
+    END
+  END Di[20]
+  PIN Di[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 627.070 0.000 627.350 4.000 ;
+    END
+  END Di[21]
+  PIN Di[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 638.570 0.000 638.850 4.000 ;
+    END
+  END Di[22]
+  PIN Di[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 650.530 0.000 650.810 4.000 ;
+    END
+  END Di[23]
+  PIN Di[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 662.030 0.000 662.310 4.000 ;
+    END
+  END Di[24]
+  PIN Di[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 673.990 0.000 674.270 4.000 ;
+    END
+  END Di[25]
+  PIN Di[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 685.490 0.000 685.770 4.000 ;
+    END
+  END Di[26]
+  PIN Di[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 697.450 0.000 697.730 4.000 ;
+    END
+  END Di[27]
+  PIN Di[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 708.950 0.000 709.230 4.000 ;
+    END
+  END Di[28]
+  PIN Di[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 720.910 0.000 721.190 4.000 ;
+    END
+  END Di[29]
+  PIN Di[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 403.970 0.000 404.250 4.000 ;
+    END
+  END Di[2]
+  PIN Di[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 732.410 0.000 732.690 4.000 ;
+    END
+  END Di[30]
+  PIN Di[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 744.370 0.000 744.650 4.000 ;
+    END
+  END Di[31]
+  PIN Di[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 415.930 0.000 416.210 4.000 ;
+    END
+  END Di[3]
+  PIN Di[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 427.430 0.000 427.710 4.000 ;
+    END
+  END Di[4]
+  PIN Di[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 439.390 0.000 439.670 4.000 ;
+    END
+  END Di[5]
+  PIN Di[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 450.890 0.000 451.170 4.000 ;
+    END
+  END Di[6]
+  PIN Di[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 462.850 0.000 463.130 4.000 ;
+    END
+  END Di[7]
+  PIN Di[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 474.350 0.000 474.630 4.000 ;
+    END
+  END Di[8]
+  PIN Di[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 486.310 0.000 486.590 4.000 ;
+    END
+  END Di[9]
+  PIN Do[0]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 5.610 0.000 5.890 4.000 ;
+    END
+  END Do[0]
+  PIN Do[10]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 122.450 0.000 122.730 4.000 ;
+    END
+  END Do[10]
+  PIN Do[11]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 134.410 0.000 134.690 4.000 ;
+    END
+  END Do[11]
+  PIN Do[12]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 145.910 0.000 146.190 4.000 ;
+    END
+  END Do[12]
+  PIN Do[13]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 157.870 0.000 158.150 4.000 ;
+    END
+  END Do[13]
+  PIN Do[14]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 169.370 0.000 169.650 4.000 ;
+    END
+  END Do[14]
+  PIN Do[15]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 181.330 0.000 181.610 4.000 ;
+    END
+  END Do[15]
+  PIN Do[16]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 192.830 0.000 193.110 4.000 ;
+    END
+  END Do[16]
+  PIN Do[17]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 204.790 0.000 205.070 4.000 ;
+    END
+  END Do[17]
+  PIN Do[18]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 216.290 0.000 216.570 4.000 ;
+    END
+  END Do[18]
+  PIN Do[19]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 228.250 0.000 228.530 4.000 ;
+    END
+  END Do[19]
+  PIN Do[1]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 17.110 0.000 17.390 4.000 ;
+    END
+  END Do[1]
+  PIN Do[20]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 239.750 0.000 240.030 4.000 ;
+    END
+  END Do[20]
+  PIN Do[21]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 251.710 0.000 251.990 4.000 ;
+    END
+  END Do[21]
+  PIN Do[22]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 263.210 0.000 263.490 4.000 ;
+    END
+  END Do[22]
+  PIN Do[23]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 275.170 0.000 275.450 4.000 ;
+    END
+  END Do[23]
+  PIN Do[24]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 286.670 0.000 286.950 4.000 ;
+    END
+  END Do[24]
+  PIN Do[25]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 298.630 0.000 298.910 4.000 ;
+    END
+  END Do[25]
+  PIN Do[26]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 310.130 0.000 310.410 4.000 ;
+    END
+  END Do[26]
+  PIN Do[27]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 322.090 0.000 322.370 4.000 ;
+    END
+  END Do[27]
+  PIN Do[28]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 333.590 0.000 333.870 4.000 ;
+    END
+  END Do[28]
+  PIN Do[29]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 345.550 0.000 345.830 4.000 ;
+    END
+  END Do[29]
+  PIN Do[2]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 28.610 0.000 28.890 4.000 ;
+    END
+  END Do[2]
+  PIN Do[30]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 357.050 0.000 357.330 4.000 ;
+    END
+  END Do[30]
+  PIN Do[31]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 369.010 0.000 369.290 4.000 ;
+    END
+  END Do[31]
+  PIN Do[3]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 40.570 0.000 40.850 4.000 ;
+    END
+  END Do[3]
+  PIN Do[4]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 52.070 0.000 52.350 4.000 ;
+    END
+  END Do[4]
+  PIN Do[5]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 64.030 0.000 64.310 4.000 ;
+    END
+  END Do[5]
+  PIN Do[6]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 75.530 0.000 75.810 4.000 ;
+    END
+  END Do[6]
+  PIN Do[7]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 87.490 0.000 87.770 4.000 ;
+    END
+  END Do[7]
+  PIN Do[8]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 98.990 0.000 99.270 4.000 ;
+    END
+  END Do[8]
+  PIN Do[9]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 110.950 0.000 111.230 4.000 ;
+    END
+  END Do[9]
+  PIN EN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 943.550 0.000 943.830 4.000 ;
+    END
+  END EN
+  PIN WE[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 896.630 0.000 896.910 4.000 ;
+    END
+  END WE[0]
+  PIN WE[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 908.590 0.000 908.870 4.000 ;
+    END
+  END WE[1]
+  PIN WE[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 920.090 0.000 920.370 4.000 ;
+    END
+  END WE[2]
+  PIN WE[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 932.050 0.000 932.330 4.000 ;
+    END
+  END WE[3]
+  PIN VPWR
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER met4 ;
+        RECT 789.040 10.640 790.640 3087.440 ;
+    END
+  END VPWR
+  PIN VPWR
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER met4 ;
+        RECT 635.440 10.640 637.040 3087.440 ;
+    END
+  END VPWR
+  PIN VPWR
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER met4 ;
+        RECT 481.840 10.640 483.440 3087.440 ;
+    END
+  END VPWR
+  PIN VPWR
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER met4 ;
+        RECT 328.240 10.640 329.840 3087.440 ;
+    END
+  END VPWR
+  PIN VPWR
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER met4 ;
+        RECT 174.640 10.640 176.240 3087.440 ;
+    END
+  END VPWR
+  PIN VPWR
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER met4 ;
+        RECT 21.040 10.640 22.640 3087.440 ;
+    END
+  END VPWR
+  PIN VGND
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER met4 ;
+        RECT 865.840 10.640 867.440 3087.440 ;
+    END
+  END VGND
+  PIN VGND
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER met4 ;
+        RECT 712.240 10.640 713.840 3087.440 ;
+    END
+  END VGND
+  PIN VGND
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER met4 ;
+        RECT 558.640 10.640 560.240 3087.440 ;
+    END
+  END VGND
+  PIN VGND
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER met4 ;
+        RECT 405.040 10.640 406.640 3087.440 ;
+    END
+  END VGND
+  PIN VGND
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER met4 ;
+        RECT 251.440 10.640 253.040 3087.440 ;
+    END
+  END VGND
+  PIN VGND
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER met4 ;
+        RECT 97.840 10.640 99.440 3087.440 ;
+    END
+  END VGND
+  OBS
+      LAYER li1 ;
+        RECT 5.520 10.795 949.755 3087.285 ;
+      LAYER met1 ;
+        RECT 0.530 10.240 949.830 3087.440 ;
+      LAYER met2 ;
+        RECT 0.550 4.280 949.810 3087.440 ;
+        RECT 0.550 4.000 5.330 4.280 ;
+        RECT 6.170 4.000 16.830 4.280 ;
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+        RECT 41.130 4.000 51.790 4.280 ;
+        RECT 52.630 4.000 63.750 4.280 ;
+        RECT 64.590 4.000 75.250 4.280 ;
+        RECT 76.090 4.000 87.210 4.280 ;
+        RECT 88.050 4.000 98.710 4.280 ;
+        RECT 99.550 4.000 110.670 4.280 ;
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+        RECT 838.770 4.000 849.430 4.280 ;
+        RECT 850.270 4.000 861.390 4.280 ;
+        RECT 862.230 4.000 872.890 4.280 ;
+        RECT 873.730 4.000 884.850 4.280 ;
+        RECT 885.690 4.000 896.350 4.280 ;
+        RECT 897.190 4.000 908.310 4.280 ;
+        RECT 909.150 4.000 919.810 4.280 ;
+        RECT 920.650 4.000 931.770 4.280 ;
+        RECT 932.610 4.000 943.270 4.280 ;
+        RECT 944.110 4.000 949.810 4.280 ;
+      LAYER met3 ;
+        RECT 0.525 9.695 949.835 3087.365 ;
+      LAYER met4 ;
+        RECT 1.215 10.240 20.640 3069.345 ;
+        RECT 23.040 10.240 97.440 3069.345 ;
+        RECT 99.840 10.240 174.240 3069.345 ;
+        RECT 176.640 10.240 251.040 3069.345 ;
+        RECT 253.440 10.240 327.840 3069.345 ;
+        RECT 330.240 10.240 404.640 3069.345 ;
+        RECT 407.040 10.240 481.440 3069.345 ;
+        RECT 483.840 10.240 558.240 3069.345 ;
+        RECT 560.640 10.240 635.040 3069.345 ;
+        RECT 637.440 10.240 711.840 3069.345 ;
+        RECT 714.240 10.240 788.640 3069.345 ;
+        RECT 791.040 10.240 865.440 3069.345 ;
+        RECT 867.840 10.240 939.025 3069.345 ;
+        RECT 1.215 9.695 939.025 10.240 ;
+  END
+END RAM_2x4KB
+END LIBRARY
+
diff --git a/mag/RAM_2x4KB.mag.gz b/mag/RAM_2x4KB.mag.gz
new file mode 100644
index 0000000..25e112e
--- /dev/null
+++ b/mag/RAM_2x4KB.mag.gz
Binary files differ
diff --git a/maglef/RAM_2x4KB.mag b/maglef/RAM_2x4KB.mag
new file mode 100644
index 0000000..8b21026
--- /dev/null
+++ b/maglef/RAM_2x4KB.mag
@@ -0,0 +1,400 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1611254817
+<< obsli1 >>
+rect 1104 2159 189951 617457
+<< obsm1 >>
+rect 106 2048 189966 617488
+<< metal2 >>
+rect 1122 0 1178 800
+rect 3422 0 3478 800
+rect 5722 0 5778 800
+rect 8114 0 8170 800
+rect 10414 0 10470 800
+rect 12806 0 12862 800
+rect 15106 0 15162 800
+rect 17498 0 17554 800
+rect 19798 0 19854 800
+rect 22190 0 22246 800
+rect 24490 0 24546 800
+rect 26882 0 26938 800
+rect 29182 0 29238 800
+rect 31574 0 31630 800
+rect 33874 0 33930 800
+rect 36266 0 36322 800
+rect 38566 0 38622 800
+rect 40958 0 41014 800
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+rect 50342 0 50398 800
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+rect 55034 0 55090 800
+rect 57334 0 57390 800
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+rect 62026 0 62082 800
+rect 64418 0 64474 800
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+rect 101954 0 102010 800
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+rect 120722 0 120778 800
+rect 123022 0 123078 800
+rect 125414 0 125470 800
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+rect 130106 0 130162 800
+rect 132406 0 132462 800
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+rect 139490 0 139546 800
+rect 141790 0 141846 800
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+rect 146482 0 146538 800
+rect 148874 0 148930 800
+rect 151174 0 151230 800
+rect 153566 0 153622 800
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+rect 160558 0 160614 800
+rect 162950 0 163006 800
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+rect 169942 0 169998 800
+rect 172334 0 172390 800
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+rect 177026 0 177082 800
+rect 179326 0 179382 800
+rect 181718 0 181774 800
+rect 184018 0 184074 800
+rect 186410 0 186466 800
+rect 188710 0 188766 800
+<< obsm2 >>
+rect 110 856 189962 617488
+rect 110 800 1066 856
+rect 1234 800 3366 856
+rect 3534 800 5666 856
+rect 5834 800 8058 856
+rect 8226 800 10358 856
+rect 10526 800 12750 856
+rect 12918 800 15050 856
+rect 15218 800 17442 856
+rect 17610 800 19742 856
+rect 19910 800 22134 856
+rect 22302 800 24434 856
+rect 24602 800 26826 856
+rect 26994 800 29126 856
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+rect 31686 800 33818 856
+rect 33986 800 36210 856
+rect 36378 800 38510 856
+rect 38678 800 40902 856
+rect 41070 800 43202 856
+rect 43370 800 45594 856
+rect 45762 800 47894 856
+rect 48062 800 50286 856
+rect 50454 800 52586 856
+rect 52754 800 54978 856
+rect 55146 800 57278 856
+rect 57446 800 59670 856
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+rect 62138 800 64362 856
+rect 64530 800 66662 856
+rect 66830 800 69054 856
+rect 69222 800 71354 856
+rect 71522 800 73746 856
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+rect 78606 800 80738 856
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+rect 87990 800 90122 856
+rect 90290 800 92514 856
+rect 92682 800 94814 856
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+rect 167754 800 169886 856
+rect 170054 800 172278 856
+rect 172446 800 174578 856
+rect 174746 800 176970 856
+rect 177138 800 179270 856
+rect 179438 800 181662 856
+rect 181830 800 183962 856
+rect 184130 800 186354 856
+rect 186522 800 188654 856
+rect 188822 800 189962 856
+<< obsm3 >>
+rect 105 1939 189967 617473
+<< metal4 >>
+rect 4208 2128 4528 617488
+rect 19568 2128 19888 617488
+rect 34928 2128 35248 617488
+rect 50288 2128 50608 617488
+rect 65648 2128 65968 617488
+rect 81008 2128 81328 617488
+rect 96368 2128 96688 617488
+rect 111728 2128 112048 617488
+rect 127088 2128 127408 617488
+rect 142448 2128 142768 617488
+rect 157808 2128 158128 617488
+rect 173168 2128 173488 617488
+<< obsm4 >>
+rect 243 2048 4128 613869
+rect 4608 2048 19488 613869
+rect 19968 2048 34848 613869
+rect 35328 2048 50208 613869
+rect 50688 2048 65568 613869
+rect 66048 2048 80928 613869
+rect 81408 2048 96288 613869
+rect 96768 2048 111648 613869
+rect 112128 2048 127008 613869
+rect 127488 2048 142368 613869
+rect 142848 2048 157728 613869
+rect 158208 2048 173088 613869
+rect 173568 2048 187805 613869
+rect 243 1939 187805 2048
+<< labels >>
+rlabel metal2 s 151174 0 151230 800 6 A[0]
+port 1 nsew signal input
+rlabel metal2 s 174634 0 174690 800 6 A[10]
+port 2 nsew signal input
+rlabel metal2 s 153566 0 153622 800 6 A[1]
+port 3 nsew signal input
+rlabel metal2 s 155866 0 155922 800 6 A[2]
+port 4 nsew signal input
+rlabel metal2 s 158258 0 158314 800 6 A[3]
+port 5 nsew signal input
+rlabel metal2 s 160558 0 160614 800 6 A[4]
+port 6 nsew signal input
+rlabel metal2 s 162950 0 163006 800 6 A[5]
+port 7 nsew signal input
+rlabel metal2 s 165250 0 165306 800 6 A[6]
+port 8 nsew signal input
+rlabel metal2 s 167642 0 167698 800 6 A[7]
+port 9 nsew signal input
+rlabel metal2 s 169942 0 169998 800 6 A[8]
+port 10 nsew signal input
+rlabel metal2 s 172334 0 172390 800 6 A[9]
+port 11 nsew signal input
+rlabel metal2 s 177026 0 177082 800 6 CLK
+port 12 nsew signal input
+rlabel metal2 s 76102 0 76158 800 6 Di[0]
+port 13 nsew signal input
+rlabel metal2 s 99562 0 99618 800 6 Di[10]
+port 14 nsew signal input
+rlabel metal2 s 101954 0 102010 800 6 Di[11]
+port 15 nsew signal input
+rlabel metal2 s 104254 0 104310 800 6 Di[12]
+port 16 nsew signal input
+rlabel metal2 s 106646 0 106702 800 6 Di[13]
+port 17 nsew signal input
+rlabel metal2 s 108946 0 109002 800 6 Di[14]
+port 18 nsew signal input
+rlabel metal2 s 111338 0 111394 800 6 Di[15]
+port 19 nsew signal input
+rlabel metal2 s 113638 0 113694 800 6 Di[16]
+port 20 nsew signal input
+rlabel metal2 s 116030 0 116086 800 6 Di[17]
+port 21 nsew signal input
+rlabel metal2 s 118330 0 118386 800 6 Di[18]
+port 22 nsew signal input
+rlabel metal2 s 120722 0 120778 800 6 Di[19]
+port 23 nsew signal input
+rlabel metal2 s 78494 0 78550 800 6 Di[1]
+port 24 nsew signal input
+rlabel metal2 s 123022 0 123078 800 6 Di[20]
+port 25 nsew signal input
+rlabel metal2 s 125414 0 125470 800 6 Di[21]
+port 26 nsew signal input
+rlabel metal2 s 127714 0 127770 800 6 Di[22]
+port 27 nsew signal input
+rlabel metal2 s 130106 0 130162 800 6 Di[23]
+port 28 nsew signal input
+rlabel metal2 s 132406 0 132462 800 6 Di[24]
+port 29 nsew signal input
+rlabel metal2 s 134798 0 134854 800 6 Di[25]
+port 30 nsew signal input
+rlabel metal2 s 137098 0 137154 800 6 Di[26]
+port 31 nsew signal input
+rlabel metal2 s 139490 0 139546 800 6 Di[27]
+port 32 nsew signal input
+rlabel metal2 s 141790 0 141846 800 6 Di[28]
+port 33 nsew signal input
+rlabel metal2 s 144182 0 144238 800 6 Di[29]
+port 34 nsew signal input
+rlabel metal2 s 80794 0 80850 800 6 Di[2]
+port 35 nsew signal input
+rlabel metal2 s 146482 0 146538 800 6 Di[30]
+port 36 nsew signal input
+rlabel metal2 s 148874 0 148930 800 6 Di[31]
+port 37 nsew signal input
+rlabel metal2 s 83186 0 83242 800 6 Di[3]
+port 38 nsew signal input
+rlabel metal2 s 85486 0 85542 800 6 Di[4]
+port 39 nsew signal input
+rlabel metal2 s 87878 0 87934 800 6 Di[5]
+port 40 nsew signal input
+rlabel metal2 s 90178 0 90234 800 6 Di[6]
+port 41 nsew signal input
+rlabel metal2 s 92570 0 92626 800 6 Di[7]
+port 42 nsew signal input
+rlabel metal2 s 94870 0 94926 800 6 Di[8]
+port 43 nsew signal input
+rlabel metal2 s 97262 0 97318 800 6 Di[9]
+port 44 nsew signal input
+rlabel metal2 s 1122 0 1178 800 6 Do[0]
+port 45 nsew signal output
+rlabel metal2 s 24490 0 24546 800 6 Do[10]
+port 46 nsew signal output
+rlabel metal2 s 26882 0 26938 800 6 Do[11]
+port 47 nsew signal output
+rlabel metal2 s 29182 0 29238 800 6 Do[12]
+port 48 nsew signal output
+rlabel metal2 s 31574 0 31630 800 6 Do[13]
+port 49 nsew signal output
+rlabel metal2 s 33874 0 33930 800 6 Do[14]
+port 50 nsew signal output
+rlabel metal2 s 36266 0 36322 800 6 Do[15]
+port 51 nsew signal output
+rlabel metal2 s 38566 0 38622 800 6 Do[16]
+port 52 nsew signal output
+rlabel metal2 s 40958 0 41014 800 6 Do[17]
+port 53 nsew signal output
+rlabel metal2 s 43258 0 43314 800 6 Do[18]
+port 54 nsew signal output
+rlabel metal2 s 45650 0 45706 800 6 Do[19]
+port 55 nsew signal output
+rlabel metal2 s 3422 0 3478 800 6 Do[1]
+port 56 nsew signal output
+rlabel metal2 s 47950 0 48006 800 6 Do[20]
+port 57 nsew signal output
+rlabel metal2 s 50342 0 50398 800 6 Do[21]
+port 58 nsew signal output
+rlabel metal2 s 52642 0 52698 800 6 Do[22]
+port 59 nsew signal output
+rlabel metal2 s 55034 0 55090 800 6 Do[23]
+port 60 nsew signal output
+rlabel metal2 s 57334 0 57390 800 6 Do[24]
+port 61 nsew signal output
+rlabel metal2 s 59726 0 59782 800 6 Do[25]
+port 62 nsew signal output
+rlabel metal2 s 62026 0 62082 800 6 Do[26]
+port 63 nsew signal output
+rlabel metal2 s 64418 0 64474 800 6 Do[27]
+port 64 nsew signal output
+rlabel metal2 s 66718 0 66774 800 6 Do[28]
+port 65 nsew signal output
+rlabel metal2 s 69110 0 69166 800 6 Do[29]
+port 66 nsew signal output
+rlabel metal2 s 5722 0 5778 800 6 Do[2]
+port 67 nsew signal output
+rlabel metal2 s 71410 0 71466 800 6 Do[30]
+port 68 nsew signal output
+rlabel metal2 s 73802 0 73858 800 6 Do[31]
+port 69 nsew signal output
+rlabel metal2 s 8114 0 8170 800 6 Do[3]
+port 70 nsew signal output
+rlabel metal2 s 10414 0 10470 800 6 Do[4]
+port 71 nsew signal output
+rlabel metal2 s 12806 0 12862 800 6 Do[5]
+port 72 nsew signal output
+rlabel metal2 s 15106 0 15162 800 6 Do[6]
+port 73 nsew signal output
+rlabel metal2 s 17498 0 17554 800 6 Do[7]
+port 74 nsew signal output
+rlabel metal2 s 19798 0 19854 800 6 Do[8]
+port 75 nsew signal output
+rlabel metal2 s 22190 0 22246 800 6 Do[9]
+port 76 nsew signal output
+rlabel metal2 s 188710 0 188766 800 6 EN
+port 77 nsew signal input
+rlabel metal2 s 179326 0 179382 800 6 WE[0]
+port 78 nsew signal input
+rlabel metal2 s 181718 0 181774 800 6 WE[1]
+port 79 nsew signal input
+rlabel metal2 s 184018 0 184074 800 6 WE[2]
+port 80 nsew signal input
+rlabel metal2 s 186410 0 186466 800 6 WE[3]
+port 81 nsew signal input
+rlabel metal4 s 157808 2128 158128 617488 6 VPWR
+port 82 nsew power bidirectional
+rlabel metal4 s 127088 2128 127408 617488 6 VPWR
+port 83 nsew power bidirectional
+rlabel metal4 s 96368 2128 96688 617488 6 VPWR
+port 84 nsew power bidirectional
+rlabel metal4 s 65648 2128 65968 617488 6 VPWR
+port 85 nsew power bidirectional
+rlabel metal4 s 34928 2128 35248 617488 6 VPWR
+port 86 nsew power bidirectional
+rlabel metal4 s 4208 2128 4528 617488 6 VPWR
+port 87 nsew power bidirectional
+rlabel metal4 s 173168 2128 173488 617488 6 VGND
+port 88 nsew ground bidirectional
+rlabel metal4 s 142448 2128 142768 617488 6 VGND
+port 89 nsew ground bidirectional
+rlabel metal4 s 111728 2128 112048 617488 6 VGND
+port 90 nsew ground bidirectional
+rlabel metal4 s 81008 2128 81328 617488 6 VGND
+port 91 nsew ground bidirectional
+rlabel metal4 s 50288 2128 50608 617488 6 VGND
+port 92 nsew ground bidirectional
+rlabel metal4 s 19568 2128 19888 617488 6 VGND
+port 93 nsew ground bidirectional
+<< properties >>
+string LEFclass BLOCK
+string FIXED_BBOX 0 0 190000 620000
+string LEFview TRUE
+string GDS_FILE /project/openlane/RAM_2x4KB/runs/RAM_2x4KB/results/magic/RAM_2x4KB.gds
+string GDS_END 532148620
+string GDS_START 189654
+<< end >>
+
diff --git a/spi/lvs/RAM_2x4KB.spice b/spi/lvs/RAM_2x4KB.spice
new file mode 100644
index 0000000..83d23cb
--- /dev/null
+++ b/spi/lvs/RAM_2x4KB.spice
Binary files differ
diff --git a/verilog/gl/RAM_2x4KB.v b/verilog/gl/RAM_2x4KB.v
new file mode 100644
index 0000000..7a3af2d
--- /dev/null
+++ b/verilog/gl/RAM_2x4KB.v
Binary files differ