| ,design,design_name,config,runtime,DIEAREA_mm^2,CellPer_mm^2,(Cell/mm^2)/Core_Util,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,0h4m35s,10.2784,21.50140099626401,43.00280199252802,-1,711.94,221,0,0,0,0,0,0,-1,4,0,-1,-1,210850,1049,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,139816960,0.0,6.09,2.12,1.66,1.24,0.0,33,651,24,642,0,0,0,221,1,0,1,0,0,0,0,3,10,7,5,286,15199,0,15485,100.0,10.0,10,AREA 0,5,50,1,153.6,153.18,0.4,0,sky130_fd_sc_hd,8,0 |
| 0,/project/openlane/RAM_6Kx32,RAM_6Kx32,RAM_6Kx32,3h57m32s,8.99,54131.14571746385,108262.2914349277,91,9977.74,486639,0,0,0,0,0,0,31,-1,0,-1,-1,18574153,3972241,-5.5,-5.5,-5.5,-5.5,-10.17,-29183.6,-29183.6,-29183.6,-29183.6,-76347.32,7476664669,0.0,53.84,40.06,5.25,1.25,-1,290005,290082,236,313,0,0,0,486639,0,0,1,0,2,0,0,160,195,38,8,2262,116126,0,118388,49.578582052553294,20.17,10,AREA 0,5,50,1,153.6,153.18,0.84,0,sky130_fd_sc_hd,0,4 |
