final gds & signoff results
19 files changed
tree: 67708f62290186e6c4c6fd2dfab1c13df6bae615
  1. .github/
  2. .gitignore
  3. .gitmodules
  4. LICENSE
  5. Makefile
  6. README.md
  7. def/
  8. docs/
  9. gds/
  10. info.yaml
  11. lef/
  12. mag/
  13. maglef/
  14. openlane/
  15. signoff/
  16. spi/
  17. verilog/
README.md

Table of contents

Caravel FPU

License UPRJ_CI Caravel Build

Floating Point Unit

FPU Architecture

The default rounding mode for all the operations is RNE as highlighted by RISC-V and IEEE-754 spec.

FPU Exceptions

Integration of FPU as Memory Mapped Peripheral

Wishbone Interface

Logic Analyzer

GPIO

Result of FPU calculation also appers at the 32 GPIO pins.

CSRs for FPU

Instruction Flow