final gds & signoff results
15 files changed
tree: af4c6e5da72cc097475d16acb526c91115b80fd2
  1. .github/
  2. .gitignore
  3. .gitmodules
  5. Makefile
  7. checks/
  8. docs/
  11. gds/
  12. info.yaml
  14. mag/
  15. netgen/
  16. openlane/
  17. signoff/
  19. verilog/
  20. xschem/

Caravel Analog Fulgor

License UPRJ_CI Caravan Build


As posgraduate students at Universidad Nacional del Sur (Bahía Blanca, Argentina) , we (Álvaro Fernandez and Diego Hernando) are specializing in the analog design of mixed-signal integrated circuits. Particullary we are working on high-speed ADCs and clock circuits applied to optcial coherent digital communications. Therefore this first thest chip contains several circuits that will allow us to corroborate the various methods and techniques learned so far in our studies. This is not our final chip version, but a first approach to whole IC desing.

Our Master's studies are possible thanks to the Fundación Fulgor. Fundación Fulgor seeks to create growth opportunities for as many members of Argentine society as possible. The main instrument for the creation of opportunities is education, together with the search for the insertion of its beneficiaries in the productive process. For this reason, the Foundation focuses its efforts on the education and educational support tasks. Fundación Fulgor develops high-level undergraduate and graduate training programs, generating leaders with experience in leading projects and training human resources with great social impact. To this end, Fundación Fulgor not only provides academic scholarships, but also collaborates closely with several universities (Universidad Nacional del Sur, Universidad Nacional de Córdoba), and in the particular case of microelectronics collaborates with The Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA.

Repo Setup

In order to get de PDK, tools and paths needed to get the desing working just run the script.


This script creates a directory named skywater in $HOME. Under this directory you will find the Google-Skywater 130nm Open Source PDK and several tools and configurations needed, in order to work with the analog desing flow.

This script does the following:

Running the tools


In the xschem folder all the schematics and spice symbols are located. To open one of those shematics the following commands need to be run:

cd caravel_analog_fulgor/xschem
xschem {schematic_name.sch}

In the xschem folder it is found the xschemrc file, where the paths to the xschem libraries are defined. There is also a simualtions folder where all the .spice and .raw files are stored.


To run magic and be able to edit or desing a layout the following commands need to be run:

cd caravel_analog_fulgor/mag
magic -rcfile magicrc {layout_name.mag}

The magicrc file specifies where the open_pdk layout libraries are located. If magic is used without the -rcfile specification, the sky130 library won't be loaded.


In order to get the .spice files form layout or extract parasitics from the desings, extractions must be run. The following scripts make easy this step:

  • extraction without creating ports. It extract files for LVS and PEX with C parasitics and RC parasitics.
  • creates ports from the layout labels. It generates the same files as the previous script.

To run them, just tipe:


The script will ask you for the cellname. You need to make sure that the schematic and the layout views of the cell match in names :exclamation:.


netgen is used as the LVS test tool. You need to provide to it the path to the .spice files to compare (from layout and schematic) and with the design rools from the PDK. To make this step easier, there is also a script:

  • compares the layout and schematic .spice files, and check if they match. The script will ask you for the cellname. You need to make sure that the schematic and the layout views of the cell match in names :exclamation:. The LVS report can be found in mag/extractions/lvs_{cellname}.out

Desing Description

In this run you can find:

  • There versions of a A 1GHz Current Starved VCO based PLL:

    • Version 1: It works wir a reference frequency of 100MHz and generates an output frequency of 1GHz.
    • Version 2: It adds progrmabillity to the loop filter by adding capacitance in parallel with the secondary loop filter capacitor.
    • Version 3: It adds progrmabillity not just to the loop filter, but also to the frequency divider. Now is possible to divide the VCO output frequency by 4,6,8,10,12 and 20. This will allow us to use several reference frequencies and to make the PLL work if the tapeout comes in the Slow-Slow corner.
  • A Residual Amplifier With Variable Output Common Mode and Gain:

    • This design consist of a single stage dynamic amplifier with output common mode and gain calibrations, able to operate at 100MHz. Additionally, the design include a clock generation block, where control signals are generated. Finally, the amplified output signal is buffered by source follower buffers.