final gds & signoff results
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tree: ca13e8517f733c9afff3bfc17c0f9a783104bdd6
  1. .github/
  2. .gitignore
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  4. LICENSE
  5. Makefile
  6. README.md
  7. def/
  8. docs/
  9. gds/
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  11. info.yaml
  12. lef/
  13. mag/
  14. maglef/
  15. openlane/
  16. signoff/
  17. spi/
  18. verilog/
README.md

Caravel User Project

License UPRJ_CI Caravel Build

Azadi RISC-V SoC

Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer. The parent repository of azadi-soc can be found here.

Azadi SoC DFFRAM: Flattened with user_project_wrapper

azadi-gds