final gds & signoff results
10 files changed
tree: 2dd1bdd9b947915132215f04bfdc8f4227e7908f
  1. .github/
  2. docs/
  3. gds/
  4. images/
  5. lef/
  6. mag/
  7. maglef/
  8. oas/
  9. openlane/
  10. signoff/
  11. spi/
  12. verilog/
  13. .gitignore
  14. .gitmodules
  15. LICENSE
  16. Makefile
  17. README.md
  18. info.yaml
README.md

Caravel User Project

License UPRJ_CI Caravel Build

Azadi RISC-V SoC

Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer. The parent repository of azadi-soc can be found here.

Azadi SoC DFFRAM: Flattened with user_project_wrapper

azadi-gds