final gds & signoff results
36 files changed
tree: ca13e8517f733c9afff3bfc17c0f9a783104bdd6
  1. .github/
  2. .gitignore
  3. .gitmodules
  5. Makefile
  7. def/
  8. docs/
  9. gds/
  10. images/
  11. info.yaml
  12. lef/
  13. mag/
  14. maglef/
  15. openlane/
  16. signoff/
  17. spi/
  18. verilog/

Caravel User Project

License UPRJ_CI Caravel Build

Azadi RISC-V SoC

Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer. The parent repository of azadi-soc can be found here.

Azadi SoC DFFRAM: Flattened with user_project_wrapper