final gds & signoff results
21 files changed
tree: 1bd4247c15df062bf61c95fd3e27522757d30a0b
  1. .github/
  2. .gitignore
  3. .gitmodules
  5. Makefile
  7. caravel/
  8. def/
  9. docs/
  10. gds/
  11. info.yaml
  12. lef/
  13. mag/
  14. maglef/
  15. openlane/
  16. signoff/
  17. spi/
  18. verilog/


License UPRJ_CI Caravel Build

FuseRISC will demonstrate the benefits of the tight coupling of RISC-V cores and eFPGA fabric for tensorflow micro applications. Two RISC-V cores will have ALU that are integrated directly with a customised eFPGA fabric generated using the FABulous eFPGA framework. Each core is coupled to the caravel wishbone interface and has access to a 1kb OpenRAM SKY130 Standard SRAM. Other control pins are connected to the caravel LA probes. The RISC-V cores are modified IBEX cores from lowRISC.

// SPDX-License-Identifier: Apache-2.0