final gds & signoff results
31 files changed
tree: 0920fed26f46b30626ae15c6e195200ee92bab12
  1. LICENSE
  2. Makefile
  3. Postlayout/
  4. Prelayout/
  5. README.md
  6. README.src.rst
  7. caravel/
  8. checks/
  9. docs/
  10. gds/
  11. info.yaml
  12. lef/
  13. mag/
  14. maglef/
  15. manifest
  16. ngspice/
  17. openlane/
  18. scripts/
  19. signoff/
  20. sky130_fd_pr/
  21. spi/
  22. utils/
  23. verilog/
README.md

POTENTIOMETRIC DIGITAL-TO-ANALOG CONVERTER

The project aims to design a 10-bit Potentiometric Digital to Analog Converter using end-to-end Open-source EDA tools. The target is to design 10-bit potentiometric DAC with 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference using sky130nm technology node.

Table of Content

1.Purpose of Digital to Analog Converter (DAC)

In real world, most of the data available is in the form of analog in nature. We have two types of converters analog to digital converter and digital to analog converter. These two converting interfaces are essential to obtain the required operations of a processor to manipulate the data of digital electronic equipment and an analog electric equipment. Digital to Analog Converter (DAC) is a device that transforms digital data into an analog signal in order to interact with the real world. The digital signal is represented with a binary code, which is a combination of bits 0’s and 1’s. The digital data can be produced from a microprocessor, Field Programmable Gate Array (FPGA), or Application Specified Integrated Circuit (ASIC). There are two commonly used DAC conversions – Weighed resistors method and R-2R ladder network method. Applications of a DAC: audio amplifier, video encoder, display electronics, data acquisition systems, calibration, Digital potentiometer.

2.IP Block Design Specifications

IP Block Diagram

avsdDAC3v3

Terminal Functions

NamePin No.I/ODescription
D [0:9]1-10IDigital inputs
EN11IEnable pin
VDD12IDigital power supply (1.8)
VSS13IDigital ground
OUT14ODAC analog voltage output
VDDA15IAnalog voltage supply (3.3)
VSSA16IAnalog ground
VREFH17IReference voltage high for DAC(3.3)
VREFL18IReference voltage low for DAC

3.EDA tools used to implement Potentiometric DAC

The design has been built using open-source EDA tools. The library used is sky130. This design is implemented using xschem, and ngspice is used to run the simulations & verify the circuitry. For circuit layout implementation, Magic will be used. The step to install xschem with sky130 and ngspice can be found here.

4.Implementation of 10Bit Potentiometric DAC

The basic idea is to divide the voltage into N different voltage values in the range of VREFH and VREFL- for an N-Bit DAC. The design used here to achieve this is the simple resistor string DAC which consists of resistors in series. These resistors are then connected to various switches in such a fashion that it routes the exact voltage to the output. The problem of the largeness of the circuit is reduced by building hierarchical subcircuits of 10-Bit potentiometric DAC – Switch, 2-bit, 3-bit, 4-bit, 5-bit, 6-bit, 7-bit, 8-bit, 9-bit and 10-bit.

Conventional DAC

Basic Architecture of Potentiometric DAC

5.Pre-layout Designs and Simulations

Switch design and simulation

Switch design implementation and respective waveform are shown below

Switch Design

Switch waveform

To see this waveform run switch.spice file

2-Bit DAC design and simulation:

2Bit DAC is implemented using 3 switch instances. 2-Bit circuitry and waveform are shown below

2Bit DAC Design

2Bit DAC WaveForm

To see this waveform run my_2bitdac.spice file

3-Bit DAC design and simulation:

3Bit DAC is implemented using 2 2-Bit DACs and 1 switch instances. 3-Bit circuitry and waveform are shown below

3Bit DAC Design

3Bit DAC WaveForm

To see this waveform run my_3bitdac.spice file

4-Bit DAC design and simulation:

4Bit DAC is implemented using 2 3-Bit DACs and 1 switch instances. 4-Bit circuitry and waveform are shown below

4Bit DAC Design

4Bit DAC WaveForm

To see this waveform run my_4bitdac.spice file

5-Bit DAC design and simulation:

5Bit DAC is implemented using 2 4-Bit DACs and 1 switch instances. 5-Bit circuitry and waveform are shown below

5Bit DAC Design

5Bit DAC WaveForm

To see this waveform run my_5bitdac.spice file

6-Bit DAC design and simulation:

6Bit DAC is implemented using 2 5-Bit DACs and 1 switch instances. 6-Bit circuitry and waveform are shown below

6Bit DAC Design

6Bit DAC WaveForm

To see this waveform run my_6bitdac.spice file

7-Bit DAC design and simulation:

7Bit DAC is implemented using 2 6-Bit DACs and 1 switch instances. 7-Bit circuitry and waveform are shown below 7Bit DAC Design

7Bit DAC WaveForm

To see this waveform run my_7bitdac.spice file

8-Bit DAC design and simulation:

8Bit DAC is implemented using 2 7-Bit DACs and 1 switch instances. 8-Bit circuitry and waveform are shown below

8Bit DAC Design

8Bit DAC WaveForm

To see this waveform run my_8bitdac.spice file

9-Bit DAC design and simulation:

9Bit DAC is implemented using 2 8-Bit DACs and 1 switch instances. 9-Bit circuitry and waveform are shown below

9Bit DAC Design

9Bit DAC WaveForm

To see the waveform run my_9bitdac.spice file.

10-Bit DAC design and simulation:

10Bit DAC is implemented using 2 9-Bit DACs and 1 switch instances. 10-Bit circuitry and waveform are shown below

10Bit DAC Design

10Bit DAC WaveForm

To see the wavefrom run my_10bitdac.spice file.

Every block of the circuit until 10 bit DAC are tested and spice models until 10 bit dac are included in specified folders.

INL AND DNL outputs

DNL_LSB

INL_LSB

6.Post-layout Designs and Simulations

Resistor 250 layout and value

Resistor 250 layout

R = 249.8ohms

Resistor 500 layout and value

Resistor 500 layout

R = 497.2ohms

Inverter layout

Inverter Implementation is shown below

Inverter Layout

Switch layout and simulation

Switch layout implementation and its respective waveform are shown below

Switch Layout

Switch layout waveform

To see this waveform run switch_layout_test.spice file

2-Bit DAC layout and simulation

2Bit DAC is implemented using 3 switch instances. 2-Bit layout and waveform are shown below

2Bit DAC Layout

2Bit DAC WaveForm

To see this waveform run 2bitdac_layout_test.spice file

3-Bit DAC layout and simulation

3Bit DAC is implemented using 2 2-Bit DACs and 1 switch instances. 3-Bit layout and waveform are shown below 3bit DAC layout

3Bit DAC WaveForm

To see the wavefrom run 3bitdac_layout_test.spice file.

4-Bit DAC layout and simulation

4Bit DAC is implemented using 2 3-Bit DACs and 1 switch instances. 4-Bit layout and waveform are shown below

4bit DAC layout

4Bit DAC WaveForm

To see the wavefrom run 4bitdac_layout_test.spice file.

5-Bit DAC layout and simulation

5Bit DAC is implemented using 2 4-Bit DACs and 1 switch instances. 5-Bit layout and waveform are shown below

5bit DAC layout

5Bit DAC WaveForm

To see the wavefrom run 5bitdac_layout_test.spice file.

6-Bit DAC layout and simulation

6Bit DAC is implemented using 2 5-Bit DACs and 1 switch instances. 6-Bit layout and waveform are shown below

6bit DAC layout

6Bit DAC WaveForm

To see the wavefrom run 6bitdac_layout_test.spice file.

7-Bit DAC layout and simulation

7Bit DAC is implemented using 2 6-Bit DACs and 1 switch instances. 7-Bit layout and waveform are shown below

7bit DAC layout

7Bit DAC WaveForm

To see the wavefrom run 7bitdac_layout_test.spice file.

8-Bit DAC layout and simulation

8Bit DAC is implemented using 2 7-Bit DACs and 1 switch instances. 8-Bit layout and waveform are shown below

8bit DAC layout

8Bit DAC WaveForm

To see the wavefrom run 8bitdac_layout_test.spice file.

9-Bit DAC layout and simulation

9Bit DAC is implemented using 2 8-Bit DACs and 1 switch instances. 9-Bit layout and waveform are shown below

9bit DAC layout

9Bit DAC WaveForm

To see the wavefrom run 9bitdac_layout_test.spice file.

10-Bit DAC layout and simulation

10Bit DAC is implemented using 2 9-Bit DACs and 1 switch instances. 10-Bit layout and waveform are shown below

10bit DAC layout

10Bit DAC WaveForm

To see the wavefrom run 10bitdac_layout_test.spice file.

INL AND DNL outputs postlayout

DNL_LSB

INL_LSB

7.Instructions to get started with the design

Spice simulation speed improvement (Multi threading)

Ngspice provides multithreading options to improve the simulation time. To enable multithreading following steps are to be followed:

o Install ngspice from tarball

o sudo apt-get install -y autoconf

o sudo apt-get install -y libtool

o tar -zxvf ngspice

o cd ngspice

o ./autogen.sh

o ./configure --enable-xspice --enable-openmp --disable-debug --with-readline=yes

o make clean

o make

o sudo make install

Then in the netlist's control section, add the following: set num_threads=4 (or more)

Multithreading

However, multithreading option is effective if the major part of the circuit are MOSFETs (BSIM 3V8 or BSIM4V5),since the DAC consits of more number of resistors, multithreading option was not helpful to increase the simulation speed.

Pre-layout Simulation commands

o Clone the git repo with following command

    git clone https://github.com/vsdip/avsddac_3v3_sky130_v1.git

o Open the terminal from the cloned folder or run below command after cloning while in the same path

        cd avsddac_3v3_sky130_v1/

o Command to simulate .Spice files of conventional design

        cd Prelayout/

        ngspice my_nbitdac.spice  

Post-layout Simulation commands

o Clone the git repo with following command (if you haven't cloned for pre-layout simulation)

        git clone https://github.com/vsdip/avsddac_3v3_sky130_v1.git

o Open the terminal from the cloned folder or run below command after cloning while in the same path

    cd avsddac_3v3_sky130_v1/

o Command to simulate .Spice files of conventional design layout

   cd Postlayout/
   
   ngspice nbitdac_layout_test.spice

o type y when simulation asks for

8.Future Works

Runtime for layout can be reduced further.

9.Contributors

Shalini Kanna, Master of Science in Computer Engineering, University of Massachusetts Lowell, Lowell,MA, USA; Contact: kannashalini97@gmail.com, LinkedIn

Harshitha Basavaraju, PhD Scholar @ University of Bundeswehr, Munich, Germany; Contact: harshithab0707@gmail.com, LinkedIn

Skandha Deepsita S, PhD Scholar @ IIITDM Kancheepuram; Contact: skandha.deepsita5@gmail.com, LinkedIn

Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd. - kunalghosh@gmail.com

10.Acknowledgments

Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd. - kunalghosh@gmail.com