final gds & signoff results
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tree: 9e790653669982ddd3a6049dbccfa364e248976e
  1. .github/
  2. .gitignore
  3. .gitmodules
  4. LICENSE
  5. Makefile
  6. README.md
  7. checks/
  8. def/
  9. docs/
  10. gds/
  11. info.yaml
  12. lef/
  13. mag/
  14. maglef/
  15. openlane/
  16. signoff/
  17. spi/
  18. verilog/
README.md

YONGA-LZ4 Decoder

License UPRJ_CI Caravel Build

Table of contents

Overview

YONGA-LZ4 Decoder is an implementation of the decoder of the popular LZ4 compression algorithm.

Setup

export PDK_ROOT=<pdk-installation-path>
export OPENLANE_ROOT=<openlane-installation-path>
cd $UPRJ_ROOT
export CARAVEL_ROOT=$(pwd)/caravel
make install

Running Simulation

WISHBONE Test

  • This test is meant to verify that we can read and write to the YONGA-LZ4 Decoder through the WISHBONE port. The firmware first writes a compressed data stream to input FIFO of the YONGA-LZ4 Decoder, then reads decoded data stream from output FIFO of the YONGA-LZ4 Decoder.

To run RTL simulation,

cd $UPRJ_ROOT
make verify-wb_test

Hardening the User Project Macro using OpenLANE

# Run openlane to harden user_proj_example
make user_proj_example
# Run openlane to harden user_project_wrapper
make user_project_wrapper

Checklist for Open-MPW Two Submission

  • [x] The project repo adheres to the same directory structure in this repo
  • [x] The project repo contain info.yaml at the project root
  • [x] Top level macro is named user_project_wrapper
  • [x] Full Chip Simulation passes for RTL and GL (gate-level)
  • [x] The hardened Macros are LVS and DRC clean
  • [x] The hardened user_project_wrapper adheres to the same pin order specified at pin_order
  • [x] XOR check passes with zero total difference.
  • [x] Openlane summary reports are retained under ./signoff/

List of Contributors

In alphabetical order:

  • Abdullah Yildiz
  • Altug Somay
  • Burak Yakup Cakar
  • Muhammed Bahadir Turkoglu
  • Rifat Demircioglu