1. 0504986 Fix README sizes by mrg · 2 months ago master
  2. a5189a7 Add authors to README by mrg · 2 months ago
  3. 2a92077 Edit README with correct memories by mrg · 2 months ago
  4. c67e6c6 DRC in single ports fixed. by mrg · 2 months ago
  5. de193bc Fixed final gds merge by mrg · 2 months ago
  6. 2cda10b Final design by mrg · 2 months ago
  7. 9c8b600 Sp macros by mrg · 2 months ago
  8. cfead8e Update with new single port macros by mrg · 2 months ago
  9. 16df1c4 Assign spare din/dout signals by mrg · 2 months ago
  10. cca8635 Remove wmask as bus by mrg · 2 months ago
  11. 2f90459 Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main by mrg · 3 months ago
  12. 9150950 Updates... by mrg · 3 months ago
  13. 201fac9 Removed extra write to address 2 by AmoghLonkar · 3 months ago
  14. 7657e52 Works for all memories by AmoghLonkar · 3 months ago
  15. 93a84d7 Dual port memories work properly by AmoghLonkar · 3 months ago
  16. 4433376 Correct setup, debug incorrect byte value by AmoghLonkar · 3 months ago
  17. b30333e Make checks consistent with gpio test by AmoghLonkar · 3 months ago
  18. ca8c347 la_test.c by AmoghLonkar · 3 months ago
  19. ea79ae3 Updated description to match LA test by AmoghLonkar · 3 months ago
  20. fd29518 Interacted with each SRAM, test la_out pin values by AmoghLonkar · 3 months ago
  21. ce25d7a Properly writes, reads and replaces din with correct dout by AmoghLonkar · 3 months ago
  22. 33eab50 Writes correctly to SRAM 0 by AmoghLonkar · 3 months ago
  23. b6ecf06 Moved xfer up, can see proper delays now by AmoghLonkar · 3 months ago
  24. ae1a45f Only use single pin to signal start and end by AmoghLonkar · 3 months ago
  25. d945632 Test now starts and terminates by AmoghLonkar · 3 months ago
  26. ee86546 Revert to original by AmoghLonkar · 3 months ago
  27. e1eed46 Fixed reg_mprj_data, doesn't timeout anymore by AmoghLonkar · 3 months ago
  28. 73a59cc Add gpio_clk back and it is sync with clock by mrg · 3 months ago
  29. 8411fd2 Debugged la_test clock error by mrg · 3 months ago
  30. 0306794 Cleanup gpio_test_tb by mrg · 3 months ago
  31. abe0289 Restrict data to < 8bits for SRAM0 by mrg · 3 months ago
  32. 18d2c0e Fix SRAM11 64-bit errors. by mrg · 3 months ago
  33. 180a052 Fix sram load with extra cycle by mrg · 3 months ago
  34. e0af871 Deassert gpio_sram_load by mrg · 3 months ago
  35. 1574e7b Add error when read mismatch by mrg · 3 months ago
  36. 7690a5f Use some different data by mrg · 3 months ago
  37. f5e29db Write tasks for write and read by mrg · 3 months ago
  38. 68cc0a9 Add signal from mgmt to start testing by mrg · 3 months ago
  39. 785acbf Update memory macros to have unique names by mrg · 3 months ago
  40. 1e29eda Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main by mrg · 3 months ago
  41. be1762c Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main by mrg · 3 months ago
  42. 261bdc5 Added output display by AmoghLonkar · 3 months ago
  43. 80511b3 Final run for precheck by mrg · 3 months ago
  44. 307b86c Final run for precheck by mrg · 3 months ago
  45. 0f01622 Final run for precheck by mrg · 3 months ago
  46. 2cb8c08 Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip into main by AmoghLonkar · 3 months ago
  47. 383e94b Removed asserts by AmoghLonkar · 3 months ago
  48. bac364d Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main by mrg · 3 months ago
  49. c79b1ec Latest LA test by mrg · 3 months ago
  50. 785473b Added tests for single port memories. Assert causing errors but still running tests by AmoghLonkar · 3 months ago
  51. 1450be6 Add initial la test by mrg · 3 months ago
  52. 319d6ed Add initial la test skeleton by mrg · 3 months ago
  53. 1339831 Update gpio test by mrg · 3 months ago
  54. c9fb6b0 Make LA reset and cs active high for reset by mrg · 3 months ago
  55. dfe137d Make LA reset and cs active high for reset by mrg · 3 months ago
  56. 0145b27 Use LA for reset too by mrg · 3 months ago
  57. 9184a51 Update latest version by mrg · 3 months ago
  58. 5a6aee0 Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip into main by AmoghLonkar · 3 months ago
  59. 3baac70 Correct input scanning by AmoghLonkar · 3 months ago
  60. 9377327 Adding makefile by AmoghLonkar · 3 months ago
  61. f0bd15b update README by mrg · 3 months ago
  62. 71dedcd Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip into main by AmoghLonkar · 3 months ago
  63. 38954f1 Up to date tb model by AmoghLonkar · 3 months ago
  64. 6a1c098 Can communicate with SRAMs now by AmoghLonkar · 3 months ago
  65. a6be5e0 Modified pin declarations by AmoghLonkar · 3 months ago
  66. 8b8d027 Removed unused gpio sram clk port by AmoghLonkar · 3 months ago
  67. e988856 Update SP SRAMs to have spare_wen0 by mrg · 3 months ago
  68. 1946164 Cleanup by mrg · 3 months ago
  69. 2ff0e70 Code cleanup by mrg · 3 months ago
  70. 2d08cd6 Compiles without error by AmoghLonkar · 3 months ago
  71. d07f5ba Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip into main by AmoghLonkar · 3 months ago
  72. 662b8ad Removed left and right addr0, etc by AmoghLonkar · 3 months ago
  73. 2e70f51 Resolved compile errors by AmoghLonkar · 3 months ago
  74. 328535d Fix missing gpio_in by mrg · 3 months ago
  75. ad78217 Change csr to csb by mrg · 3 months ago
  76. fc1a774 Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip into main by AmoghLonkar · 3 months ago
  77. a522bcc Figure out how to send signal over pin by AmoghLonkar · 3 months ago
  78. 4a0200e Remove left/right separate pins by mrg · 3 months ago
  79. 076f16c Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip into main by AmoghLonkar · 3 months ago
  80. f70bb92 Added global csr pin by AmoghLonkar · 3 months ago
  81. eb5a605 Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main by mrg · 3 months ago
  82. 8bde8f8 Remove extra character by mrg · 3 months ago
  83. d617e93 Fixed index on GPIO output pin range by AmoghLonkar · 3 months ago
  84. 2603fb9 Remove old verilog by mrg · 3 months ago
  85. d54b7b1 Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main by mrg · 3 months ago
  86. 0d14b0b Use single clock, top-level gate place and route by mrg · 3 months ago
  87. 3ff7d07 Add clock_mux by AmoghLonkar · 3 months ago
  88. 9ccd2e3 Added reg declaration for sram_data and removed duplicate sram_dout declaration by AmoghLonkar · 3 months ago
  89. 3a0040d Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main by mrg · 3 months ago
  90. 0dd2159 Resolve clock port and net issue by making clock_mux by mrg · 3 months ago
  91. dbb04f6 Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip into main by AmoghLonkar · 3 months ago
  92. 309e08c Changed module name, compiles without error by AmoghLonkar · 3 months ago
  93. 3a93f37 Delete openram_testchip_tb.v by Amogh Lonkar · 3 months ago
  94. 7c387d1 Correct pattern by AmoghLonkar · 3 months ago
  95. 7c0e55a Pin 21 for output by AmoghLonkar · 3 months ago
  96. d15e74c Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main by mrg · 3 months ago
  97. 8188070 Change reset to resetn by mrg · 3 months ago
  98. 9ff09f0 Proper assignment to idle sramX_dataY by AmoghLonkar · 3 months ago
  99. ee5398d Removed duplicate declaration for sramX_doutY by AmoghLonkar · 3 months ago
  100. 144ab80 Included the relevant files by AmoghLonkar · 3 months ago