|author||mrg <email@example.com>||Sat Jul 10 20:37:41 2021 -0700|
|committer||mrg <firstname.lastname@example.org>||Sat Jul 10 20:37:41 2021 -0700|
DRC in single ports fixed.
|:exclamation: Important Note|
This project contains a test chip for several OpenRAM memory configurations. The configurations have varying levels of verification. In particular, it has these sizes:
There are two test modes available. Each one inputs an packet that configures the read and write operations of a particular SRAM. The GPIO pin io_in determines whether to use GPIO (1) or LA mode (0).
The test packet is a 112-bit value that has the follow signals and bit size:
During a read operation, the din bits are replaced with the data output bits so that they can be verified.
Note: The 64-bit memory leaves the middle 32-bits as a value of 0 and instead reads/writes the upper and lower 16-bits to reduce the number of packet bits.
In GPIO mode, the test packet is scanned in/out with the GPIO pins in 112 cycles. The GPIO pins used are as follows:
In LA mode, the test packet is directly written from the output of the 128-bit LA. The top bits of the LA register are used for the control signals during test: