final gds & signoff results
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tree: 2d824e01ce1113a2b6161d812b88939db768d585
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. oas/
  9. openlane/
  10. signoff/
  11. spi/
  12. verilog/
  13. .gitignore
  14. .gitmodules
  15. LICENSE
  16. Makefile
  17. README.md
  18. info.yaml
README.md

Caravel User Project

License UPRJ_CI Caravel Build

Demonstration of the Fabulous FPGA design flow using the Skywater 130 process.

This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.

Refer to README for this sample project documentation.