final gds oasis
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tree: b8c87048d8af0b78b50078db6a25e91543b211a3
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. maglef/
  7. mpw_precheck/
  8. openlane/
  9. sdc/
  10. sdf/
  11. signoff/
  12. spef/
  13. spi/
  14. tapeout/
  15. verilog/
  16. .gitignore
  17. LICENSE
  18. Makefile
  19. README.md
README.md

This project contains OpenRAM SRAM's and its test application. The used SRAM was precompiled using OpenRAM. It has 512 32-bit words, which means it has a 2 Kbyte of memory. It has 1 rw port and 1 r port. 4 of them were used in this work, in total 8 Kbyte memory, and they are controllable by Wishbone bus coming from Caravel harness. The layout of the user_project_wrapper can be seen below.

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The waveform of the operation is visible below. Example waveform shows read & write operations sent from software. Both RTL and gate level simulation was done to ensure correct operation.

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SRAM's were implemented directly in the user_project_wrapper due to limitation about SRAM power connections. The control logic was also implemented in user_project_wrapper for simplicity. The operating frequency is max 50 MHz.