|author||Tim Edwards <email@example.com>||Tue Oct 13 17:11:54 2020 -0400|
|committer||Tim Edwards <firstname.lastname@example.org>||Tue Oct 13 17:11:54 2020 -0400|
(1) Added a wrapper interface between the top level verilog and the user project example. (2) Corrected broken directory references in README.md (3) Added the caravel.pdf document (first draft, mostly just figures and no text).
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
The managment SoC runs firmware taht can be used to:
The memory map of the management SoC is given below
(NOTE: This needs updating; see the README file for an updated list.)
This is the user space. It has limited silicon area (TBD, about 2.8mm x 2.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: