Removed VCD and hex files, which should not be in the repository.
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio.hex b/verilog/dv/caravel/mgmt_soc/gpio/gpio.hex
deleted file mode 100755
index 3513089..0000000
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio.hex
+++ /dev/null
@@ -1,72 +0,0 @@
-@00000000

-93 00 00 00 93 01 00 00 13 02 00 00 93 02 00 00 

-13 03 00 00 93 03 00 00 13 04 00 00 93 04 00 00 

-13 05 00 00 93 05 00 00 13 06 00 00 93 06 00 00 

-13 07 00 00 93 07 00 00 13 08 00 00 93 08 00 00 

-13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00 

-13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00 

-13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00 

-13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 85 3F 

-93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1 

-11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00 

-63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 71 28 

-01 A0 01 00 B7 02 00 28 13 03 00 12 23 90 62 00 

-A3 81 02 00 05 C6 21 4F 93 73 F6 0F 93 DE 73 00 

-23 80 D2 01 93 EE 0E 01 23 80 D2 01 86 03 93 F3 

-F3 0F 7D 1F E3 14 0F FE 23 80 62 00 A1 C9 13 0F 

-00 02 83 23 05 00 A1 4F 93 DE F3 01 23 80 D2 01 

-93 EE 0E 01 23 80 D2 01 83 CE 02 00 93 FE 2E 00 

-93 DE 1E 00 86 03 B3 E3 D3 01 7D 1F 63 17 0F 00 

-23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC 

-FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08 

-A3 81 62 00 82 80 01 00 00 00 01 11 22 CE 00 10 

-B7 07 00 26 23 A0 07 00 B7 07 00 26 93 87 87 08 

-09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 47 08 

-09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 07 08 

-09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 C7 07 

-09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 87 07 

-09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 47 07 

-09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 07 07 

-09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 C7 06 

-09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 87 06 

-13 07 30 40 98 C3 B7 07 00 26 93 87 47 06 13 07 

-30 40 98 C3 B7 07 00 26 93 87 07 06 13 07 30 40 

-98 C3 B7 07 00 26 93 87 C7 05 13 07 30 40 98 C3 

-B7 07 00 26 93 87 87 05 13 07 30 40 98 C3 B7 07 

-00 26 93 87 47 05 13 07 30 40 98 C3 B7 07 00 26 

-93 87 07 05 13 07 30 40 98 C3 B7 07 00 26 93 87 

-C7 04 13 07 30 40 98 C3 B7 07 00 26 A1 07 05 47 

-98 C3 01 00 B7 07 00 26 A1 07 98 43 85 47 E3 0B 

-F7 FE B7 07 00 26 37 07 00 A0 98 C3 B7 07 00 26 

-93 87 87 06 05 67 13 07 37 80 98 C3 B7 07 00 26 

-93 87 47 06 05 67 13 07 37 80 98 C3 B7 07 00 26 

-93 87 07 06 05 67 13 07 37 80 98 C3 B7 07 00 26 

-93 87 C7 05 05 67 13 07 37 80 98 C3 B7 07 00 26 

-93 87 87 05 05 67 13 07 37 C0 98 C3 B7 07 00 26 

-93 87 47 05 05 67 13 07 37 C0 98 C3 B7 07 00 26 

-93 87 07 05 05 67 13 07 37 C0 98 C3 B7 07 00 26 

-93 87 C7 04 05 67 13 07 37 C0 98 C3 B7 07 00 26 

-A1 07 05 47 98 C3 01 00 B7 07 00 26 A1 07 98 43 

-85 47 E3 0B F7 FE B7 07 00 26 37 07 00 0B 98 C3 

-B7 07 00 26 93 87 87 06 05 67 13 07 37 C0 98 C3 

-B7 07 00 26 93 87 47 06 05 67 13 07 37 C0 98 C3 

-B7 07 00 26 93 87 07 06 05 67 13 07 37 C0 98 C3 

-B7 07 00 26 93 87 C7 05 05 67 13 07 37 C0 98 C3 

-B7 07 00 26 93 87 87 05 05 67 13 07 37 80 98 C3 

-B7 07 00 26 93 87 47 05 05 67 13 07 37 80 98 C3 

-B7 07 00 26 93 87 07 05 05 67 13 07 37 80 98 C3 

-B7 07 00 26 93 87 C7 04 05 67 13 07 37 80 98 C3 

-B7 07 00 26 A1 07 05 47 98 C3 01 00 B7 07 00 26 

-A1 07 98 43 85 47 E3 0B F7 FE B7 07 00 26 93 87 

-87 06 05 67 13 07 37 80 98 C3 B7 07 00 26 93 87 

-47 06 05 67 13 07 37 80 98 C3 B7 07 00 26 93 87 

-07 06 05 67 13 07 37 80 98 C3 B7 07 00 26 93 87 

-C7 05 05 67 13 07 37 80 98 C3 B7 07 00 26 93 87 

-87 05 05 67 13 07 37 C0 98 C3 B7 07 00 26 93 87 

-47 05 05 67 13 07 37 C0 98 C3 B7 07 00 26 93 87 

-07 05 05 67 13 07 37 C0 98 C3 B7 07 00 26 93 87 

-C7 04 05 67 13 07 37 C0 98 C3 B7 07 00 26 A1 07 

-05 47 98 C3 01 00 B7 07 00 26 A1 07 98 43 85 47 

-E3 0B F7 FE B7 07 00 26 37 07 00 AB 98 C3 B7 07 

-00 26 9C 43 C1 83 93 F7 F7 0F 23 26 F4 FE 83 27 

-C4 FE 85 07 13 97 87 01 B7 07 00 26 98 C3 C5 B7 

diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio.vcd b/verilog/dv/caravel/mgmt_soc/gpio/gpio.vcd
deleted file mode 100644
index 2c8332b..0000000
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio.vcd
+++ /dev/null
@@ -1,2765105 +0,0 @@
-$date
-	Mon Oct 12 22:19:52 2020
-$end
-$version
-	Icarus Verilog
-$end
-$timescale
-	1ps
-$end
-$scope module gpio_tb $end
-$var wire 1 ! VSS $end
-$var wire 1 " flash_clk $end
-$var wire 1 # flash_csb $end
-$var wire 1 $ flash_io0 $end
-$var wire 1 % flash_io1 $end
-$var wire 1 & gpio $end
-$var wire 37 ' mprj_io [36:0] $end
-$var wire 8 ( checkbits_hi [7:0] $end
-$var wire 16 ) checkbits [15:0] $end
-$var wire 1 * VDD3V3 $end
-$var wire 1 + VDD1V8 $end
-$var reg 1 , RSTB $end
-$var reg 8 - checkbits_lo [7:0] $end
-$var reg 1 . clock $end
-$var reg 1 * power1 $end
-$var reg 1 + power2 $end
-$scope module spiflash $end
-$var wire 1 " clk $end
-$var wire 1 # csb $end
-$var wire 1 $ io0 $end
-$var wire 1 / io0_delayed $end
-$var wire 1 % io1 $end
-$var wire 1 0 io1_delayed $end
-$var wire 1 1 io2_delayed $end
-$var wire 1 2 io3_delayed $end
-$var wire 1 3 io3 $end
-$var wire 1 4 io2 $end
-$var reg 8 5 buffer [7:0] $end
-$var reg 1 6 io0_dout $end
-$var reg 1 7 io0_oe $end
-$var reg 1 8 io1_dout $end
-$var reg 1 9 io1_oe $end
-$var reg 1 : io2_dout $end
-$var reg 1 ; io2_oe $end
-$var reg 1 < io3_dout $end
-$var reg 1 = io3_oe $end
-$var reg 4 > mode [3:0] $end
-$var reg 4 ? next_mode [3:0] $end
-$var reg 1 @ powered_up $end
-$var reg 24 A spi_addr [23:0] $end
-$var reg 8 B spi_cmd [7:0] $end
-$var reg 8 C spi_in [7:0] $end
-$var reg 1 D spi_io_vld $end
-$var reg 8 E spi_out [7:0] $end
-$var reg 8 F xip_cmd [7:0] $end
-$var integer 32 G bitcount [31:0] $end
-$var integer 32 H bytecount [31:0] $end
-$var integer 32 I dummycount [31:0] $end
-$scope task ddr_rd_edge $end
-$upscope $end
-$scope task ddr_wr_edge $end
-$upscope $end
-$scope task spi_action $end
-$upscope $end
-$upscope $end
-$scope module uut $end
-$var wire 1 J clock $end
-$var wire 1 " flash_clk $end
-$var wire 1 K flash_clk_ieb_core $end
-$var wire 1 # flash_csb $end
-$var wire 1 L flash_csb_ieb_core $end
-$var wire 1 $ flash_io0 $end
-$var wire 1 % flash_io1 $end
-$var wire 1 & gpio $end
-$var wire 1 M jtag_out $end
-$var wire 1 N jtag_outenb $end
-$var wire 37 O mgmt_io_in [36:0] $end
-$var wire 1 P mprj_ack_i_core $end
-$var wire 32 Q mprj_adr_o_core [31:0] $end
-$var wire 1 R mprj_cyc_o_core $end
-$var wire 32 S mprj_dat_o_core [31:0] $end
-$var wire 37 T mprj_io [36:0] $end
-$var wire 4 U mprj_sel_o_core [3:0] $end
-$var wire 1 V mprj_we_o_core $end
-$var wire 1 W resetb $end
-$var wire 1 + vccd $end
-$var wire 1 + vccd1 $end
-$var wire 1 + vccd2 $end
-$var wire 1 * vdda $end
-$var wire 1 * vdda1 $end
-$var wire 1 * vdda2 $end
-$var wire 1 * vddio $end
-$var wire 1 ! vssa $end
-$var wire 1 ! vssa1 $end
-$var wire 1 ! vssa2 $end
-$var wire 1 ! vssd $end
-$var wire 1 ! vssd1 $end
-$var wire 1 ! vssd2 $end
-$var wire 1 ! vssio $end
-$var wire 1 X xbar_ack_i_core $end
-$var wire 32 Y xbar_dat_i_core [31:0] $end
-$var wire 1 Z xbar_we_o_core $end
-$var wire 1 [ xbar_stb_o_core $end
-$var wire 4 \ xbar_sel_o_core [3:0] $end
-$var wire 32 ] xbar_dat_o_core [31:0] $end
-$var wire 1 ^ xbar_cyc_o_core $end
-$var wire 32 _ xbar_adr_o_core [31:0] $end
-$var wire 37 ` user_io_out [36:0] $end
-$var wire 37 a user_io_oeb [36:0] $end
-$var wire 37 b user_io_in [36:0] $end
-$var wire 1 c sdo_outenb $end
-$var wire 1 d sdo_out $end
-$var wire 1 e rstb_l $end
-$var wire 1 f rstb_h $end
-$var wire 1 g porb_l $end
-$var wire 1 h porb_h $end
-$var wire 1 i mprj_we_o_user $end
-$var wire 1 j mprj_stb_o_user $end
-$var wire 1 k mprj_stb_o_core $end
-$var wire 4 l mprj_sel_o_user [3:0] $end
-$var wire 1 m mprj_resetn $end
-$var wire 37 n mprj_io_vtrip_sel [36:0] $end
-$var wire 37 o mprj_io_slow_sel [36:0] $end
-$var wire 37 p mprj_io_out [36:0] $end
-$var wire 37 q mprj_io_oeb [36:0] $end
-$var wire 1 r mprj_io_loader_resetn $end
-$var wire 1 s mprj_io_loader_data $end
-$var wire 1 t mprj_io_loader_clock $end
-$var wire 37 u mprj_io_inp_dis [36:0] $end
-$var wire 37 v mprj_io_in [36:0] $end
-$var wire 37 w mprj_io_ib_mode_sel [36:0] $end
-$var wire 37 x mprj_io_holdover [36:0] $end
-$var wire 37 y mprj_io_hldh_n [36:0] $end
-$var wire 37 z mprj_io_enh [36:0] $end
-$var wire 111 { mprj_io_dm [110:0] $end
-$var wire 37 | mprj_io_analog_sel [36:0] $end
-$var wire 37 } mprj_io_analog_pol [36:0] $end
-$var wire 37 ~ mprj_io_analog_en [36:0] $end
-$var wire 32 !" mprj_dat_o_user [31:0] $end
-$var wire 32 "" mprj_dat_i_core [31:0] $end
-$var wire 1 #" mprj_cyc_o_user $end
-$var wire 1 $" mprj_clock2 $end
-$var wire 1 %" mprj_clock $end
-$var wire 32 &" mprj_adr_o_user [31:0] $end
-$var wire 2 '" mgmt_io_nc2 [1:0] $end
-$var wire 32 (" mask_rev [31:0] $end
-$var wire 128 )" la_output_core [127:0] $end
-$var wire 128 *" la_oen [127:0] $end
-$var wire 128 +" la_data_out_mprj [127:0] $end
-$var wire 128 ," la_data_in_mprj [127:0] $end
-$var wire 37 -" gpio_serial_link_shifted [36:0] $end
-$var wire 37 ." gpio_serial_link [36:0] $end
-$var wire 1 /" gpio_outenb_core $end
-$var wire 1 0" gpio_out_core $end
-$var wire 1 1" gpio_mode1_core $end
-$var wire 1 2" gpio_mode0_core $end
-$var wire 1 3" gpio_inenb_core $end
-$var wire 1 4" gpio_in_core $end
-$var wire 1 5" flash_io1_oeb_core $end
-$var wire 1 6" flash_io1_ieb_core $end
-$var wire 1 7" flash_io1_do_core $end
-$var wire 1 8" flash_io1_di_core $end
-$var wire 1 9" flash_io0_oeb_core $end
-$var wire 1 :" flash_io0_ieb_core $end
-$var wire 1 ;" flash_io0_do_core $end
-$var wire 1 <" flash_io0_di_core $end
-$var wire 1 =" flash_csb_oeb_core $end
-$var wire 1 >" flash_csb_core $end
-$var wire 1 ?" flash_clk_oeb_core $end
-$var wire 1 @" flash_clk_core $end
-$var wire 1 A" clock_core $end
-$var wire 1 B" caravel_rstn $end
-$var wire 1 C" caravel_clk2 $end
-$var wire 1 D" caravel_clk $end
-$scope module gpio_control_bidir[0] $end
-$var wire 1 E" int_reset $end
-$var wire 1 F" load_data $end
-$var wire 1 G" mgmt_gpio_oeb $end
-$var wire 1 H" mgmt_gpio_out $end
-$var wire 1 I" pad_gpio_ana_en $end
-$var wire 1 J" pad_gpio_ana_pol $end
-$var wire 1 K" pad_gpio_ana_sel $end
-$var wire 3 L" pad_gpio_dm [2:0] $end
-$var wire 1 M" pad_gpio_holdover $end
-$var wire 1 N" pad_gpio_ib_mode_sel $end
-$var wire 1 O" pad_gpio_in $end
-$var wire 1 P" pad_gpio_inenb $end
-$var wire 1 Q" pad_gpio_slow_sel $end
-$var wire 1 R" pad_gpio_vtrip_sel $end
-$var wire 1 S" serial_data_in $end
-$var wire 1 T" user_gpio_oeb $end
-$var wire 1 U" user_gpio_out $end
-$var wire 1 V" vccd $end
-$var wire 1 W" vccd1 $end
-$var wire 1 X" vssd $end
-$var wire 1 Y" vssd1 $end
-$var wire 1 Z" user_gpio_in $end
-$var wire 1 [" serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 \" pad_gpio_outenb $end
-$var wire 1 ]" pad_gpio_out $end
-$var wire 1 ^" mgmt_gpio_in $end
-$var wire 1 _" gpio_logic1 $end
-$var wire 1 `" gpio_in_unbuf $end
-$var reg 1 I" gpio_ana_en $end
-$var reg 1 J" gpio_ana_pol $end
-$var reg 1 K" gpio_ana_sel $end
-$var reg 3 a" gpio_dm [2:0] $end
-$var reg 1 M" gpio_holdover $end
-$var reg 1 N" gpio_ib_mode_sel $end
-$var reg 1 b" gpio_inenb $end
-$var reg 1 c" gpio_outenb $end
-$var reg 1 Q" gpio_slow_sel $end
-$var reg 1 R" gpio_vtrip_sel $end
-$var reg 1 d" mgmt_ena $end
-$var reg 13 e" shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 f" A $end
-$var wire 1 X" VGND $end
-$var wire 1 X" VNB $end
-$var wire 1 V" VPB $end
-$var wire 1 V" VPWR $end
-$var wire 1 Z" Z $end
-$var wire 1 _" TE $end
-$scope module base $end
-$var wire 1 f" A $end
-$var wire 1 X" VGND $end
-$var wire 1 X" VNB $end
-$var wire 1 V" VPB $end
-$var wire 1 V" VPWR $end
-$var wire 1 Z" Z $end
-$var wire 1 g" pwrgood_pp0_out_A $end
-$var wire 1 h" pwrgood_pp1_out_TE $end
-$var wire 1 _" TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 Y" VGND $end
-$var wire 1 Y" VNB $end
-$var wire 1 W" VPB $end
-$var wire 1 W" VPWR $end
-$var wire 1 i" LO $end
-$var wire 1 _" HI $end
-$scope module base $end
-$var wire 1 _" HI $end
-$var wire 1 i" LO $end
-$var wire 1 Y" VGND $end
-$var wire 1 Y" VNB $end
-$var wire 1 W" VPB $end
-$var wire 1 W" VPWR $end
-$var wire 1 j" pulldown0_out_LO $end
-$var wire 1 k" pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_bidir[1] $end
-$var wire 1 l" int_reset $end
-$var wire 1 m" load_data $end
-$var wire 1 n" mgmt_gpio_oeb $end
-$var wire 1 o" mgmt_gpio_out $end
-$var wire 1 p" pad_gpio_ana_en $end
-$var wire 1 q" pad_gpio_ana_pol $end
-$var wire 1 r" pad_gpio_ana_sel $end
-$var wire 3 s" pad_gpio_dm [2:0] $end
-$var wire 1 t" pad_gpio_holdover $end
-$var wire 1 u" pad_gpio_ib_mode_sel $end
-$var wire 1 v" pad_gpio_in $end
-$var wire 1 w" pad_gpio_inenb $end
-$var wire 1 x" pad_gpio_slow_sel $end
-$var wire 1 y" pad_gpio_vtrip_sel $end
-$var wire 1 z" serial_data_in $end
-$var wire 1 {" user_gpio_oeb $end
-$var wire 1 |" user_gpio_out $end
-$var wire 1 }" vccd $end
-$var wire 1 ~" vccd1 $end
-$var wire 1 !# vssd $end
-$var wire 1 "# vssd1 $end
-$var wire 1 ## user_gpio_in $end
-$var wire 1 $# serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 %# pad_gpio_outenb $end
-$var wire 1 &# pad_gpio_out $end
-$var wire 1 '# mgmt_gpio_in $end
-$var wire 1 (# gpio_logic1 $end
-$var wire 1 )# gpio_in_unbuf $end
-$var reg 1 p" gpio_ana_en $end
-$var reg 1 q" gpio_ana_pol $end
-$var reg 1 r" gpio_ana_sel $end
-$var reg 3 *# gpio_dm [2:0] $end
-$var reg 1 t" gpio_holdover $end
-$var reg 1 u" gpio_ib_mode_sel $end
-$var reg 1 +# gpio_inenb $end
-$var reg 1 ,# gpio_outenb $end
-$var reg 1 x" gpio_slow_sel $end
-$var reg 1 y" gpio_vtrip_sel $end
-$var reg 1 -# mgmt_ena $end
-$var reg 13 .# shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 /# A $end
-$var wire 1 !# VGND $end
-$var wire 1 !# VNB $end
-$var wire 1 }" VPB $end
-$var wire 1 }" VPWR $end
-$var wire 1 ## Z $end
-$var wire 1 (# TE $end
-$scope module base $end
-$var wire 1 /# A $end
-$var wire 1 !# VGND $end
-$var wire 1 !# VNB $end
-$var wire 1 }" VPB $end
-$var wire 1 }" VPWR $end
-$var wire 1 ## Z $end
-$var wire 1 0# pwrgood_pp0_out_A $end
-$var wire 1 1# pwrgood_pp1_out_TE $end
-$var wire 1 (# TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 "# VGND $end
-$var wire 1 "# VNB $end
-$var wire 1 ~" VPB $end
-$var wire 1 ~" VPWR $end
-$var wire 1 2# LO $end
-$var wire 1 (# HI $end
-$scope module base $end
-$var wire 1 (# HI $end
-$var wire 1 2# LO $end
-$var wire 1 "# VGND $end
-$var wire 1 "# VNB $end
-$var wire 1 ~" VPB $end
-$var wire 1 ~" VPWR $end
-$var wire 1 3# pulldown0_out_LO $end
-$var wire 1 4# pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[2] $end
-$var wire 1 5# int_reset $end
-$var wire 1 6# load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 8# mgmt_gpio_out $end
-$var wire 1 9# pad_gpio_ana_en $end
-$var wire 1 :# pad_gpio_ana_pol $end
-$var wire 1 ;# pad_gpio_ana_sel $end
-$var wire 3 <# pad_gpio_dm [2:0] $end
-$var wire 1 =# pad_gpio_holdover $end
-$var wire 1 ># pad_gpio_ib_mode_sel $end
-$var wire 1 ?# pad_gpio_in $end
-$var wire 1 @# pad_gpio_inenb $end
-$var wire 1 A# pad_gpio_slow_sel $end
-$var wire 1 B# pad_gpio_vtrip_sel $end
-$var wire 1 C# serial_data_in $end
-$var wire 1 D# user_gpio_oeb $end
-$var wire 1 E# user_gpio_out $end
-$var wire 1 F# vccd $end
-$var wire 1 G# vccd1 $end
-$var wire 1 H# vssd $end
-$var wire 1 I# vssd1 $end
-$var wire 1 J# user_gpio_in $end
-$var wire 1 K# serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 L# pad_gpio_outenb $end
-$var wire 1 M# pad_gpio_out $end
-$var wire 1 N# mgmt_gpio_in $end
-$var wire 1 O# gpio_logic1 $end
-$var wire 1 P# gpio_in_unbuf $end
-$var reg 1 9# gpio_ana_en $end
-$var reg 1 :# gpio_ana_pol $end
-$var reg 1 ;# gpio_ana_sel $end
-$var reg 3 Q# gpio_dm [2:0] $end
-$var reg 1 =# gpio_holdover $end
-$var reg 1 ># gpio_ib_mode_sel $end
-$var reg 1 R# gpio_inenb $end
-$var reg 1 S# gpio_outenb $end
-$var reg 1 A# gpio_slow_sel $end
-$var reg 1 B# gpio_vtrip_sel $end
-$var reg 1 T# mgmt_ena $end
-$var reg 13 U# shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 V# A $end
-$var wire 1 H# VGND $end
-$var wire 1 H# VNB $end
-$var wire 1 F# VPB $end
-$var wire 1 F# VPWR $end
-$var wire 1 J# Z $end
-$var wire 1 O# TE $end
-$scope module base $end
-$var wire 1 V# A $end
-$var wire 1 H# VGND $end
-$var wire 1 H# VNB $end
-$var wire 1 F# VPB $end
-$var wire 1 F# VPWR $end
-$var wire 1 J# Z $end
-$var wire 1 W# pwrgood_pp0_out_A $end
-$var wire 1 X# pwrgood_pp1_out_TE $end
-$var wire 1 O# TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 I# VGND $end
-$var wire 1 I# VNB $end
-$var wire 1 G# VPB $end
-$var wire 1 G# VPWR $end
-$var wire 1 Y# LO $end
-$var wire 1 O# HI $end
-$scope module base $end
-$var wire 1 O# HI $end
-$var wire 1 Y# LO $end
-$var wire 1 I# VGND $end
-$var wire 1 I# VNB $end
-$var wire 1 G# VPB $end
-$var wire 1 G# VPWR $end
-$var wire 1 Z# pulldown0_out_LO $end
-$var wire 1 [# pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[3] $end
-$var wire 1 \# int_reset $end
-$var wire 1 ]# load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 ^# mgmt_gpio_out $end
-$var wire 1 _# pad_gpio_ana_en $end
-$var wire 1 `# pad_gpio_ana_pol $end
-$var wire 1 a# pad_gpio_ana_sel $end
-$var wire 3 b# pad_gpio_dm [2:0] $end
-$var wire 1 c# pad_gpio_holdover $end
-$var wire 1 d# pad_gpio_ib_mode_sel $end
-$var wire 1 e# pad_gpio_in $end
-$var wire 1 f# pad_gpio_inenb $end
-$var wire 1 g# pad_gpio_slow_sel $end
-$var wire 1 h# pad_gpio_vtrip_sel $end
-$var wire 1 i# serial_data_in $end
-$var wire 1 j# user_gpio_oeb $end
-$var wire 1 k# user_gpio_out $end
-$var wire 1 l# vccd $end
-$var wire 1 m# vccd1 $end
-$var wire 1 n# vssd $end
-$var wire 1 o# vssd1 $end
-$var wire 1 p# user_gpio_in $end
-$var wire 1 q# serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 r# pad_gpio_outenb $end
-$var wire 1 s# pad_gpio_out $end
-$var wire 1 t# mgmt_gpio_in $end
-$var wire 1 u# gpio_logic1 $end
-$var wire 1 v# gpio_in_unbuf $end
-$var reg 1 _# gpio_ana_en $end
-$var reg 1 `# gpio_ana_pol $end
-$var reg 1 a# gpio_ana_sel $end
-$var reg 3 w# gpio_dm [2:0] $end
-$var reg 1 c# gpio_holdover $end
-$var reg 1 d# gpio_ib_mode_sel $end
-$var reg 1 x# gpio_inenb $end
-$var reg 1 y# gpio_outenb $end
-$var reg 1 g# gpio_slow_sel $end
-$var reg 1 h# gpio_vtrip_sel $end
-$var reg 1 z# mgmt_ena $end
-$var reg 13 {# shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 |# A $end
-$var wire 1 n# VGND $end
-$var wire 1 n# VNB $end
-$var wire 1 l# VPB $end
-$var wire 1 l# VPWR $end
-$var wire 1 p# Z $end
-$var wire 1 u# TE $end
-$scope module base $end
-$var wire 1 |# A $end
-$var wire 1 n# VGND $end
-$var wire 1 n# VNB $end
-$var wire 1 l# VPB $end
-$var wire 1 l# VPWR $end
-$var wire 1 p# Z $end
-$var wire 1 }# pwrgood_pp0_out_A $end
-$var wire 1 ~# pwrgood_pp1_out_TE $end
-$var wire 1 u# TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 o# VGND $end
-$var wire 1 o# VNB $end
-$var wire 1 m# VPB $end
-$var wire 1 m# VPWR $end
-$var wire 1 !$ LO $end
-$var wire 1 u# HI $end
-$scope module base $end
-$var wire 1 u# HI $end
-$var wire 1 !$ LO $end
-$var wire 1 o# VGND $end
-$var wire 1 o# VNB $end
-$var wire 1 m# VPB $end
-$var wire 1 m# VPWR $end
-$var wire 1 "$ pulldown0_out_LO $end
-$var wire 1 #$ pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[4] $end
-$var wire 1 $$ int_reset $end
-$var wire 1 %$ load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 &$ mgmt_gpio_out $end
-$var wire 1 '$ pad_gpio_ana_en $end
-$var wire 1 ($ pad_gpio_ana_pol $end
-$var wire 1 )$ pad_gpio_ana_sel $end
-$var wire 3 *$ pad_gpio_dm [2:0] $end
-$var wire 1 +$ pad_gpio_holdover $end
-$var wire 1 ,$ pad_gpio_ib_mode_sel $end
-$var wire 1 -$ pad_gpio_in $end
-$var wire 1 .$ pad_gpio_inenb $end
-$var wire 1 /$ pad_gpio_slow_sel $end
-$var wire 1 0$ pad_gpio_vtrip_sel $end
-$var wire 1 1$ serial_data_in $end
-$var wire 1 2$ user_gpio_oeb $end
-$var wire 1 3$ user_gpio_out $end
-$var wire 1 4$ vccd $end
-$var wire 1 5$ vccd1 $end
-$var wire 1 6$ vssd $end
-$var wire 1 7$ vssd1 $end
-$var wire 1 8$ user_gpio_in $end
-$var wire 1 9$ serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 :$ pad_gpio_outenb $end
-$var wire 1 ;$ pad_gpio_out $end
-$var wire 1 <$ mgmt_gpio_in $end
-$var wire 1 =$ gpio_logic1 $end
-$var wire 1 >$ gpio_in_unbuf $end
-$var reg 1 '$ gpio_ana_en $end
-$var reg 1 ($ gpio_ana_pol $end
-$var reg 1 )$ gpio_ana_sel $end
-$var reg 3 ?$ gpio_dm [2:0] $end
-$var reg 1 +$ gpio_holdover $end
-$var reg 1 ,$ gpio_ib_mode_sel $end
-$var reg 1 @$ gpio_inenb $end
-$var reg 1 A$ gpio_outenb $end
-$var reg 1 /$ gpio_slow_sel $end
-$var reg 1 0$ gpio_vtrip_sel $end
-$var reg 1 B$ mgmt_ena $end
-$var reg 13 C$ shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 D$ A $end
-$var wire 1 6$ VGND $end
-$var wire 1 6$ VNB $end
-$var wire 1 4$ VPB $end
-$var wire 1 4$ VPWR $end
-$var wire 1 8$ Z $end
-$var wire 1 =$ TE $end
-$scope module base $end
-$var wire 1 D$ A $end
-$var wire 1 6$ VGND $end
-$var wire 1 6$ VNB $end
-$var wire 1 4$ VPB $end
-$var wire 1 4$ VPWR $end
-$var wire 1 8$ Z $end
-$var wire 1 E$ pwrgood_pp0_out_A $end
-$var wire 1 F$ pwrgood_pp1_out_TE $end
-$var wire 1 =$ TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 7$ VGND $end
-$var wire 1 7$ VNB $end
-$var wire 1 5$ VPB $end
-$var wire 1 5$ VPWR $end
-$var wire 1 G$ LO $end
-$var wire 1 =$ HI $end
-$scope module base $end
-$var wire 1 =$ HI $end
-$var wire 1 G$ LO $end
-$var wire 1 7$ VGND $end
-$var wire 1 7$ VNB $end
-$var wire 1 5$ VPB $end
-$var wire 1 5$ VPWR $end
-$var wire 1 H$ pulldown0_out_LO $end
-$var wire 1 I$ pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[5] $end
-$var wire 1 J$ int_reset $end
-$var wire 1 K$ load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 L$ mgmt_gpio_out $end
-$var wire 1 M$ pad_gpio_ana_en $end
-$var wire 1 N$ pad_gpio_ana_pol $end
-$var wire 1 O$ pad_gpio_ana_sel $end
-$var wire 3 P$ pad_gpio_dm [2:0] $end
-$var wire 1 Q$ pad_gpio_holdover $end
-$var wire 1 R$ pad_gpio_ib_mode_sel $end
-$var wire 1 S$ pad_gpio_in $end
-$var wire 1 T$ pad_gpio_inenb $end
-$var wire 1 U$ pad_gpio_slow_sel $end
-$var wire 1 V$ pad_gpio_vtrip_sel $end
-$var wire 1 W$ serial_data_in $end
-$var wire 1 X$ user_gpio_oeb $end
-$var wire 1 Y$ user_gpio_out $end
-$var wire 1 Z$ vccd $end
-$var wire 1 [$ vccd1 $end
-$var wire 1 \$ vssd $end
-$var wire 1 ]$ vssd1 $end
-$var wire 1 ^$ user_gpio_in $end
-$var wire 1 _$ serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 `$ pad_gpio_outenb $end
-$var wire 1 a$ pad_gpio_out $end
-$var wire 1 b$ mgmt_gpio_in $end
-$var wire 1 c$ gpio_logic1 $end
-$var wire 1 d$ gpio_in_unbuf $end
-$var reg 1 M$ gpio_ana_en $end
-$var reg 1 N$ gpio_ana_pol $end
-$var reg 1 O$ gpio_ana_sel $end
-$var reg 3 e$ gpio_dm [2:0] $end
-$var reg 1 Q$ gpio_holdover $end
-$var reg 1 R$ gpio_ib_mode_sel $end
-$var reg 1 f$ gpio_inenb $end
-$var reg 1 g$ gpio_outenb $end
-$var reg 1 U$ gpio_slow_sel $end
-$var reg 1 V$ gpio_vtrip_sel $end
-$var reg 1 h$ mgmt_ena $end
-$var reg 13 i$ shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 j$ A $end
-$var wire 1 \$ VGND $end
-$var wire 1 \$ VNB $end
-$var wire 1 Z$ VPB $end
-$var wire 1 Z$ VPWR $end
-$var wire 1 ^$ Z $end
-$var wire 1 c$ TE $end
-$scope module base $end
-$var wire 1 j$ A $end
-$var wire 1 \$ VGND $end
-$var wire 1 \$ VNB $end
-$var wire 1 Z$ VPB $end
-$var wire 1 Z$ VPWR $end
-$var wire 1 ^$ Z $end
-$var wire 1 k$ pwrgood_pp0_out_A $end
-$var wire 1 l$ pwrgood_pp1_out_TE $end
-$var wire 1 c$ TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 ]$ VGND $end
-$var wire 1 ]$ VNB $end
-$var wire 1 [$ VPB $end
-$var wire 1 [$ VPWR $end
-$var wire 1 m$ LO $end
-$var wire 1 c$ HI $end
-$scope module base $end
-$var wire 1 c$ HI $end
-$var wire 1 m$ LO $end
-$var wire 1 ]$ VGND $end
-$var wire 1 ]$ VNB $end
-$var wire 1 [$ VPB $end
-$var wire 1 [$ VPWR $end
-$var wire 1 n$ pulldown0_out_LO $end
-$var wire 1 o$ pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[6] $end
-$var wire 1 p$ int_reset $end
-$var wire 1 q$ load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 r$ mgmt_gpio_out $end
-$var wire 1 s$ pad_gpio_ana_en $end
-$var wire 1 t$ pad_gpio_ana_pol $end
-$var wire 1 u$ pad_gpio_ana_sel $end
-$var wire 3 v$ pad_gpio_dm [2:0] $end
-$var wire 1 w$ pad_gpio_holdover $end
-$var wire 1 x$ pad_gpio_ib_mode_sel $end
-$var wire 1 y$ pad_gpio_in $end
-$var wire 1 z$ pad_gpio_inenb $end
-$var wire 1 {$ pad_gpio_slow_sel $end
-$var wire 1 |$ pad_gpio_vtrip_sel $end
-$var wire 1 }$ serial_data_in $end
-$var wire 1 ~$ user_gpio_oeb $end
-$var wire 1 !% user_gpio_out $end
-$var wire 1 "% vccd $end
-$var wire 1 #% vccd1 $end
-$var wire 1 $% vssd $end
-$var wire 1 %% vssd1 $end
-$var wire 1 &% user_gpio_in $end
-$var wire 1 '% serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 (% pad_gpio_outenb $end
-$var wire 1 )% pad_gpio_out $end
-$var wire 1 *% mgmt_gpio_in $end
-$var wire 1 +% gpio_logic1 $end
-$var wire 1 ,% gpio_in_unbuf $end
-$var reg 1 s$ gpio_ana_en $end
-$var reg 1 t$ gpio_ana_pol $end
-$var reg 1 u$ gpio_ana_sel $end
-$var reg 3 -% gpio_dm [2:0] $end
-$var reg 1 w$ gpio_holdover $end
-$var reg 1 x$ gpio_ib_mode_sel $end
-$var reg 1 .% gpio_inenb $end
-$var reg 1 /% gpio_outenb $end
-$var reg 1 {$ gpio_slow_sel $end
-$var reg 1 |$ gpio_vtrip_sel $end
-$var reg 1 0% mgmt_ena $end
-$var reg 13 1% shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 2% A $end
-$var wire 1 $% VGND $end
-$var wire 1 $% VNB $end
-$var wire 1 "% VPB $end
-$var wire 1 "% VPWR $end
-$var wire 1 &% Z $end
-$var wire 1 +% TE $end
-$scope module base $end
-$var wire 1 2% A $end
-$var wire 1 $% VGND $end
-$var wire 1 $% VNB $end
-$var wire 1 "% VPB $end
-$var wire 1 "% VPWR $end
-$var wire 1 &% Z $end
-$var wire 1 3% pwrgood_pp0_out_A $end
-$var wire 1 4% pwrgood_pp1_out_TE $end
-$var wire 1 +% TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 %% VGND $end
-$var wire 1 %% VNB $end
-$var wire 1 #% VPB $end
-$var wire 1 #% VPWR $end
-$var wire 1 5% LO $end
-$var wire 1 +% HI $end
-$scope module base $end
-$var wire 1 +% HI $end
-$var wire 1 5% LO $end
-$var wire 1 %% VGND $end
-$var wire 1 %% VNB $end
-$var wire 1 #% VPB $end
-$var wire 1 #% VPWR $end
-$var wire 1 6% pulldown0_out_LO $end
-$var wire 1 7% pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[7] $end
-$var wire 1 8% int_reset $end
-$var wire 1 9% load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 :% mgmt_gpio_out $end
-$var wire 1 ;% pad_gpio_ana_en $end
-$var wire 1 <% pad_gpio_ana_pol $end
-$var wire 1 =% pad_gpio_ana_sel $end
-$var wire 3 >% pad_gpio_dm [2:0] $end
-$var wire 1 ?% pad_gpio_holdover $end
-$var wire 1 @% pad_gpio_ib_mode_sel $end
-$var wire 1 A% pad_gpio_in $end
-$var wire 1 B% pad_gpio_inenb $end
-$var wire 1 C% pad_gpio_slow_sel $end
-$var wire 1 D% pad_gpio_vtrip_sel $end
-$var wire 1 E% serial_data_in $end
-$var wire 1 F% user_gpio_oeb $end
-$var wire 1 G% user_gpio_out $end
-$var wire 1 H% vccd $end
-$var wire 1 I% vccd1 $end
-$var wire 1 J% vssd $end
-$var wire 1 K% vssd1 $end
-$var wire 1 L% user_gpio_in $end
-$var wire 1 M% serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 N% pad_gpio_outenb $end
-$var wire 1 O% pad_gpio_out $end
-$var wire 1 P% mgmt_gpio_in $end
-$var wire 1 Q% gpio_logic1 $end
-$var wire 1 R% gpio_in_unbuf $end
-$var reg 1 ;% gpio_ana_en $end
-$var reg 1 <% gpio_ana_pol $end
-$var reg 1 =% gpio_ana_sel $end
-$var reg 3 S% gpio_dm [2:0] $end
-$var reg 1 ?% gpio_holdover $end
-$var reg 1 @% gpio_ib_mode_sel $end
-$var reg 1 T% gpio_inenb $end
-$var reg 1 U% gpio_outenb $end
-$var reg 1 C% gpio_slow_sel $end
-$var reg 1 D% gpio_vtrip_sel $end
-$var reg 1 V% mgmt_ena $end
-$var reg 13 W% shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 X% A $end
-$var wire 1 J% VGND $end
-$var wire 1 J% VNB $end
-$var wire 1 H% VPB $end
-$var wire 1 H% VPWR $end
-$var wire 1 L% Z $end
-$var wire 1 Q% TE $end
-$scope module base $end
-$var wire 1 X% A $end
-$var wire 1 J% VGND $end
-$var wire 1 J% VNB $end
-$var wire 1 H% VPB $end
-$var wire 1 H% VPWR $end
-$var wire 1 L% Z $end
-$var wire 1 Y% pwrgood_pp0_out_A $end
-$var wire 1 Z% pwrgood_pp1_out_TE $end
-$var wire 1 Q% TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 K% VGND $end
-$var wire 1 K% VNB $end
-$var wire 1 I% VPB $end
-$var wire 1 I% VPWR $end
-$var wire 1 [% LO $end
-$var wire 1 Q% HI $end
-$scope module base $end
-$var wire 1 Q% HI $end
-$var wire 1 [% LO $end
-$var wire 1 K% VGND $end
-$var wire 1 K% VNB $end
-$var wire 1 I% VPB $end
-$var wire 1 I% VPWR $end
-$var wire 1 \% pulldown0_out_LO $end
-$var wire 1 ]% pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[8] $end
-$var wire 1 ^% int_reset $end
-$var wire 1 _% load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 `% mgmt_gpio_out $end
-$var wire 1 a% pad_gpio_ana_en $end
-$var wire 1 b% pad_gpio_ana_pol $end
-$var wire 1 c% pad_gpio_ana_sel $end
-$var wire 3 d% pad_gpio_dm [2:0] $end
-$var wire 1 e% pad_gpio_holdover $end
-$var wire 1 f% pad_gpio_ib_mode_sel $end
-$var wire 1 g% pad_gpio_in $end
-$var wire 1 h% pad_gpio_inenb $end
-$var wire 1 i% pad_gpio_slow_sel $end
-$var wire 1 j% pad_gpio_vtrip_sel $end
-$var wire 1 k% serial_data_in $end
-$var wire 1 l% user_gpio_oeb $end
-$var wire 1 m% user_gpio_out $end
-$var wire 1 n% vccd $end
-$var wire 1 o% vccd1 $end
-$var wire 1 p% vssd $end
-$var wire 1 q% vssd1 $end
-$var wire 1 r% user_gpio_in $end
-$var wire 1 s% serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 t% pad_gpio_outenb $end
-$var wire 1 u% pad_gpio_out $end
-$var wire 1 v% mgmt_gpio_in $end
-$var wire 1 w% gpio_logic1 $end
-$var wire 1 x% gpio_in_unbuf $end
-$var reg 1 a% gpio_ana_en $end
-$var reg 1 b% gpio_ana_pol $end
-$var reg 1 c% gpio_ana_sel $end
-$var reg 3 y% gpio_dm [2:0] $end
-$var reg 1 e% gpio_holdover $end
-$var reg 1 f% gpio_ib_mode_sel $end
-$var reg 1 z% gpio_inenb $end
-$var reg 1 {% gpio_outenb $end
-$var reg 1 i% gpio_slow_sel $end
-$var reg 1 j% gpio_vtrip_sel $end
-$var reg 1 |% mgmt_ena $end
-$var reg 13 }% shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 ~% A $end
-$var wire 1 p% VGND $end
-$var wire 1 p% VNB $end
-$var wire 1 n% VPB $end
-$var wire 1 n% VPWR $end
-$var wire 1 r% Z $end
-$var wire 1 w% TE $end
-$scope module base $end
-$var wire 1 ~% A $end
-$var wire 1 p% VGND $end
-$var wire 1 p% VNB $end
-$var wire 1 n% VPB $end
-$var wire 1 n% VPWR $end
-$var wire 1 r% Z $end
-$var wire 1 !& pwrgood_pp0_out_A $end
-$var wire 1 "& pwrgood_pp1_out_TE $end
-$var wire 1 w% TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 q% VGND $end
-$var wire 1 q% VNB $end
-$var wire 1 o% VPB $end
-$var wire 1 o% VPWR $end
-$var wire 1 #& LO $end
-$var wire 1 w% HI $end
-$scope module base $end
-$var wire 1 w% HI $end
-$var wire 1 #& LO $end
-$var wire 1 q% VGND $end
-$var wire 1 q% VNB $end
-$var wire 1 o% VPB $end
-$var wire 1 o% VPWR $end
-$var wire 1 $& pulldown0_out_LO $end
-$var wire 1 %& pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[9] $end
-$var wire 1 && int_reset $end
-$var wire 1 '& load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 (& mgmt_gpio_out $end
-$var wire 1 )& pad_gpio_ana_en $end
-$var wire 1 *& pad_gpio_ana_pol $end
-$var wire 1 +& pad_gpio_ana_sel $end
-$var wire 3 ,& pad_gpio_dm [2:0] $end
-$var wire 1 -& pad_gpio_holdover $end
-$var wire 1 .& pad_gpio_ib_mode_sel $end
-$var wire 1 /& pad_gpio_in $end
-$var wire 1 0& pad_gpio_inenb $end
-$var wire 1 1& pad_gpio_slow_sel $end
-$var wire 1 2& pad_gpio_vtrip_sel $end
-$var wire 1 3& serial_data_in $end
-$var wire 1 4& user_gpio_oeb $end
-$var wire 1 5& user_gpio_out $end
-$var wire 1 6& vccd $end
-$var wire 1 7& vccd1 $end
-$var wire 1 8& vssd $end
-$var wire 1 9& vssd1 $end
-$var wire 1 :& user_gpio_in $end
-$var wire 1 ;& serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 <& pad_gpio_outenb $end
-$var wire 1 =& pad_gpio_out $end
-$var wire 1 >& mgmt_gpio_in $end
-$var wire 1 ?& gpio_logic1 $end
-$var wire 1 @& gpio_in_unbuf $end
-$var reg 1 )& gpio_ana_en $end
-$var reg 1 *& gpio_ana_pol $end
-$var reg 1 +& gpio_ana_sel $end
-$var reg 3 A& gpio_dm [2:0] $end
-$var reg 1 -& gpio_holdover $end
-$var reg 1 .& gpio_ib_mode_sel $end
-$var reg 1 B& gpio_inenb $end
-$var reg 1 C& gpio_outenb $end
-$var reg 1 1& gpio_slow_sel $end
-$var reg 1 2& gpio_vtrip_sel $end
-$var reg 1 D& mgmt_ena $end
-$var reg 13 E& shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 F& A $end
-$var wire 1 8& VGND $end
-$var wire 1 8& VNB $end
-$var wire 1 6& VPB $end
-$var wire 1 6& VPWR $end
-$var wire 1 :& Z $end
-$var wire 1 ?& TE $end
-$scope module base $end
-$var wire 1 F& A $end
-$var wire 1 8& VGND $end
-$var wire 1 8& VNB $end
-$var wire 1 6& VPB $end
-$var wire 1 6& VPWR $end
-$var wire 1 :& Z $end
-$var wire 1 G& pwrgood_pp0_out_A $end
-$var wire 1 H& pwrgood_pp1_out_TE $end
-$var wire 1 ?& TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 9& VGND $end
-$var wire 1 9& VNB $end
-$var wire 1 7& VPB $end
-$var wire 1 7& VPWR $end
-$var wire 1 I& LO $end
-$var wire 1 ?& HI $end
-$scope module base $end
-$var wire 1 ?& HI $end
-$var wire 1 I& LO $end
-$var wire 1 9& VGND $end
-$var wire 1 9& VNB $end
-$var wire 1 7& VPB $end
-$var wire 1 7& VPWR $end
-$var wire 1 J& pulldown0_out_LO $end
-$var wire 1 K& pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[10] $end
-$var wire 1 L& int_reset $end
-$var wire 1 M& load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 N& mgmt_gpio_out $end
-$var wire 1 O& pad_gpio_ana_en $end
-$var wire 1 P& pad_gpio_ana_pol $end
-$var wire 1 Q& pad_gpio_ana_sel $end
-$var wire 3 R& pad_gpio_dm [2:0] $end
-$var wire 1 S& pad_gpio_holdover $end
-$var wire 1 T& pad_gpio_ib_mode_sel $end
-$var wire 1 U& pad_gpio_in $end
-$var wire 1 V& pad_gpio_inenb $end
-$var wire 1 W& pad_gpio_slow_sel $end
-$var wire 1 X& pad_gpio_vtrip_sel $end
-$var wire 1 Y& serial_data_in $end
-$var wire 1 Z& user_gpio_oeb $end
-$var wire 1 [& user_gpio_out $end
-$var wire 1 \& vccd $end
-$var wire 1 ]& vccd1 $end
-$var wire 1 ^& vssd $end
-$var wire 1 _& vssd1 $end
-$var wire 1 `& user_gpio_in $end
-$var wire 1 a& serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 b& pad_gpio_outenb $end
-$var wire 1 c& pad_gpio_out $end
-$var wire 1 d& mgmt_gpio_in $end
-$var wire 1 e& gpio_logic1 $end
-$var wire 1 f& gpio_in_unbuf $end
-$var reg 1 O& gpio_ana_en $end
-$var reg 1 P& gpio_ana_pol $end
-$var reg 1 Q& gpio_ana_sel $end
-$var reg 3 g& gpio_dm [2:0] $end
-$var reg 1 S& gpio_holdover $end
-$var reg 1 T& gpio_ib_mode_sel $end
-$var reg 1 h& gpio_inenb $end
-$var reg 1 i& gpio_outenb $end
-$var reg 1 W& gpio_slow_sel $end
-$var reg 1 X& gpio_vtrip_sel $end
-$var reg 1 j& mgmt_ena $end
-$var reg 13 k& shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 l& A $end
-$var wire 1 ^& VGND $end
-$var wire 1 ^& VNB $end
-$var wire 1 \& VPB $end
-$var wire 1 \& VPWR $end
-$var wire 1 `& Z $end
-$var wire 1 e& TE $end
-$scope module base $end
-$var wire 1 l& A $end
-$var wire 1 ^& VGND $end
-$var wire 1 ^& VNB $end
-$var wire 1 \& VPB $end
-$var wire 1 \& VPWR $end
-$var wire 1 `& Z $end
-$var wire 1 m& pwrgood_pp0_out_A $end
-$var wire 1 n& pwrgood_pp1_out_TE $end
-$var wire 1 e& TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 _& VGND $end
-$var wire 1 _& VNB $end
-$var wire 1 ]& VPB $end
-$var wire 1 ]& VPWR $end
-$var wire 1 o& LO $end
-$var wire 1 e& HI $end
-$scope module base $end
-$var wire 1 e& HI $end
-$var wire 1 o& LO $end
-$var wire 1 _& VGND $end
-$var wire 1 _& VNB $end
-$var wire 1 ]& VPB $end
-$var wire 1 ]& VPWR $end
-$var wire 1 p& pulldown0_out_LO $end
-$var wire 1 q& pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[11] $end
-$var wire 1 r& int_reset $end
-$var wire 1 s& load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 t& mgmt_gpio_out $end
-$var wire 1 u& pad_gpio_ana_en $end
-$var wire 1 v& pad_gpio_ana_pol $end
-$var wire 1 w& pad_gpio_ana_sel $end
-$var wire 3 x& pad_gpio_dm [2:0] $end
-$var wire 1 y& pad_gpio_holdover $end
-$var wire 1 z& pad_gpio_ib_mode_sel $end
-$var wire 1 {& pad_gpio_in $end
-$var wire 1 |& pad_gpio_inenb $end
-$var wire 1 }& pad_gpio_slow_sel $end
-$var wire 1 ~& pad_gpio_vtrip_sel $end
-$var wire 1 !' serial_data_in $end
-$var wire 1 "' user_gpio_oeb $end
-$var wire 1 #' user_gpio_out $end
-$var wire 1 $' vccd $end
-$var wire 1 %' vccd1 $end
-$var wire 1 &' vssd $end
-$var wire 1 '' vssd1 $end
-$var wire 1 (' user_gpio_in $end
-$var wire 1 )' serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 *' pad_gpio_outenb $end
-$var wire 1 +' pad_gpio_out $end
-$var wire 1 ,' mgmt_gpio_in $end
-$var wire 1 -' gpio_logic1 $end
-$var wire 1 .' gpio_in_unbuf $end
-$var reg 1 u& gpio_ana_en $end
-$var reg 1 v& gpio_ana_pol $end
-$var reg 1 w& gpio_ana_sel $end
-$var reg 3 /' gpio_dm [2:0] $end
-$var reg 1 y& gpio_holdover $end
-$var reg 1 z& gpio_ib_mode_sel $end
-$var reg 1 0' gpio_inenb $end
-$var reg 1 1' gpio_outenb $end
-$var reg 1 }& gpio_slow_sel $end
-$var reg 1 ~& gpio_vtrip_sel $end
-$var reg 1 2' mgmt_ena $end
-$var reg 13 3' shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 4' A $end
-$var wire 1 &' VGND $end
-$var wire 1 &' VNB $end
-$var wire 1 $' VPB $end
-$var wire 1 $' VPWR $end
-$var wire 1 (' Z $end
-$var wire 1 -' TE $end
-$scope module base $end
-$var wire 1 4' A $end
-$var wire 1 &' VGND $end
-$var wire 1 &' VNB $end
-$var wire 1 $' VPB $end
-$var wire 1 $' VPWR $end
-$var wire 1 (' Z $end
-$var wire 1 5' pwrgood_pp0_out_A $end
-$var wire 1 6' pwrgood_pp1_out_TE $end
-$var wire 1 -' TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 '' VGND $end
-$var wire 1 '' VNB $end
-$var wire 1 %' VPB $end
-$var wire 1 %' VPWR $end
-$var wire 1 7' LO $end
-$var wire 1 -' HI $end
-$scope module base $end
-$var wire 1 -' HI $end
-$var wire 1 7' LO $end
-$var wire 1 '' VGND $end
-$var wire 1 '' VNB $end
-$var wire 1 %' VPB $end
-$var wire 1 %' VPWR $end
-$var wire 1 8' pulldown0_out_LO $end
-$var wire 1 9' pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[12] $end
-$var wire 1 :' int_reset $end
-$var wire 1 ;' load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 <' mgmt_gpio_out $end
-$var wire 1 =' pad_gpio_ana_en $end
-$var wire 1 >' pad_gpio_ana_pol $end
-$var wire 1 ?' pad_gpio_ana_sel $end
-$var wire 3 @' pad_gpio_dm [2:0] $end
-$var wire 1 A' pad_gpio_holdover $end
-$var wire 1 B' pad_gpio_ib_mode_sel $end
-$var wire 1 C' pad_gpio_in $end
-$var wire 1 D' pad_gpio_inenb $end
-$var wire 1 E' pad_gpio_slow_sel $end
-$var wire 1 F' pad_gpio_vtrip_sel $end
-$var wire 1 G' serial_data_in $end
-$var wire 1 H' user_gpio_oeb $end
-$var wire 1 I' user_gpio_out $end
-$var wire 1 J' vccd $end
-$var wire 1 K' vccd1 $end
-$var wire 1 L' vssd $end
-$var wire 1 M' vssd1 $end
-$var wire 1 N' user_gpio_in $end
-$var wire 1 O' serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 P' pad_gpio_outenb $end
-$var wire 1 Q' pad_gpio_out $end
-$var wire 1 R' mgmt_gpio_in $end
-$var wire 1 S' gpio_logic1 $end
-$var wire 1 T' gpio_in_unbuf $end
-$var reg 1 =' gpio_ana_en $end
-$var reg 1 >' gpio_ana_pol $end
-$var reg 1 ?' gpio_ana_sel $end
-$var reg 3 U' gpio_dm [2:0] $end
-$var reg 1 A' gpio_holdover $end
-$var reg 1 B' gpio_ib_mode_sel $end
-$var reg 1 V' gpio_inenb $end
-$var reg 1 W' gpio_outenb $end
-$var reg 1 E' gpio_slow_sel $end
-$var reg 1 F' gpio_vtrip_sel $end
-$var reg 1 X' mgmt_ena $end
-$var reg 13 Y' shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 Z' A $end
-$var wire 1 L' VGND $end
-$var wire 1 L' VNB $end
-$var wire 1 J' VPB $end
-$var wire 1 J' VPWR $end
-$var wire 1 N' Z $end
-$var wire 1 S' TE $end
-$scope module base $end
-$var wire 1 Z' A $end
-$var wire 1 L' VGND $end
-$var wire 1 L' VNB $end
-$var wire 1 J' VPB $end
-$var wire 1 J' VPWR $end
-$var wire 1 N' Z $end
-$var wire 1 [' pwrgood_pp0_out_A $end
-$var wire 1 \' pwrgood_pp1_out_TE $end
-$var wire 1 S' TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 M' VGND $end
-$var wire 1 M' VNB $end
-$var wire 1 K' VPB $end
-$var wire 1 K' VPWR $end
-$var wire 1 ]' LO $end
-$var wire 1 S' HI $end
-$scope module base $end
-$var wire 1 S' HI $end
-$var wire 1 ]' LO $end
-$var wire 1 M' VGND $end
-$var wire 1 M' VNB $end
-$var wire 1 K' VPB $end
-$var wire 1 K' VPWR $end
-$var wire 1 ^' pulldown0_out_LO $end
-$var wire 1 _' pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[13] $end
-$var wire 1 `' int_reset $end
-$var wire 1 a' load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 b' mgmt_gpio_out $end
-$var wire 1 c' pad_gpio_ana_en $end
-$var wire 1 d' pad_gpio_ana_pol $end
-$var wire 1 e' pad_gpio_ana_sel $end
-$var wire 3 f' pad_gpio_dm [2:0] $end
-$var wire 1 g' pad_gpio_holdover $end
-$var wire 1 h' pad_gpio_ib_mode_sel $end
-$var wire 1 i' pad_gpio_in $end
-$var wire 1 j' pad_gpio_inenb $end
-$var wire 1 k' pad_gpio_slow_sel $end
-$var wire 1 l' pad_gpio_vtrip_sel $end
-$var wire 1 m' serial_data_in $end
-$var wire 1 n' user_gpio_oeb $end
-$var wire 1 o' user_gpio_out $end
-$var wire 1 p' vccd $end
-$var wire 1 q' vccd1 $end
-$var wire 1 r' vssd $end
-$var wire 1 s' vssd1 $end
-$var wire 1 t' user_gpio_in $end
-$var wire 1 u' serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 v' pad_gpio_outenb $end
-$var wire 1 w' pad_gpio_out $end
-$var wire 1 x' mgmt_gpio_in $end
-$var wire 1 y' gpio_logic1 $end
-$var wire 1 z' gpio_in_unbuf $end
-$var reg 1 c' gpio_ana_en $end
-$var reg 1 d' gpio_ana_pol $end
-$var reg 1 e' gpio_ana_sel $end
-$var reg 3 {' gpio_dm [2:0] $end
-$var reg 1 g' gpio_holdover $end
-$var reg 1 h' gpio_ib_mode_sel $end
-$var reg 1 |' gpio_inenb $end
-$var reg 1 }' gpio_outenb $end
-$var reg 1 k' gpio_slow_sel $end
-$var reg 1 l' gpio_vtrip_sel $end
-$var reg 1 ~' mgmt_ena $end
-$var reg 13 !( shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 "( A $end
-$var wire 1 r' VGND $end
-$var wire 1 r' VNB $end
-$var wire 1 p' VPB $end
-$var wire 1 p' VPWR $end
-$var wire 1 t' Z $end
-$var wire 1 y' TE $end
-$scope module base $end
-$var wire 1 "( A $end
-$var wire 1 r' VGND $end
-$var wire 1 r' VNB $end
-$var wire 1 p' VPB $end
-$var wire 1 p' VPWR $end
-$var wire 1 t' Z $end
-$var wire 1 #( pwrgood_pp0_out_A $end
-$var wire 1 $( pwrgood_pp1_out_TE $end
-$var wire 1 y' TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 s' VGND $end
-$var wire 1 s' VNB $end
-$var wire 1 q' VPB $end
-$var wire 1 q' VPWR $end
-$var wire 1 %( LO $end
-$var wire 1 y' HI $end
-$scope module base $end
-$var wire 1 y' HI $end
-$var wire 1 %( LO $end
-$var wire 1 s' VGND $end
-$var wire 1 s' VNB $end
-$var wire 1 q' VPB $end
-$var wire 1 q' VPWR $end
-$var wire 1 &( pulldown0_out_LO $end
-$var wire 1 '( pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[14] $end
-$var wire 1 (( int_reset $end
-$var wire 1 )( load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 *( mgmt_gpio_out $end
-$var wire 1 +( pad_gpio_ana_en $end
-$var wire 1 ,( pad_gpio_ana_pol $end
-$var wire 1 -( pad_gpio_ana_sel $end
-$var wire 3 .( pad_gpio_dm [2:0] $end
-$var wire 1 /( pad_gpio_holdover $end
-$var wire 1 0( pad_gpio_ib_mode_sel $end
-$var wire 1 1( pad_gpio_in $end
-$var wire 1 2( pad_gpio_inenb $end
-$var wire 1 3( pad_gpio_slow_sel $end
-$var wire 1 4( pad_gpio_vtrip_sel $end
-$var wire 1 5( serial_data_in $end
-$var wire 1 6( user_gpio_oeb $end
-$var wire 1 7( user_gpio_out $end
-$var wire 1 8( vccd $end
-$var wire 1 9( vccd1 $end
-$var wire 1 :( vssd $end
-$var wire 1 ;( vssd1 $end
-$var wire 1 <( user_gpio_in $end
-$var wire 1 =( serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 >( pad_gpio_outenb $end
-$var wire 1 ?( pad_gpio_out $end
-$var wire 1 @( mgmt_gpio_in $end
-$var wire 1 A( gpio_logic1 $end
-$var wire 1 B( gpio_in_unbuf $end
-$var reg 1 +( gpio_ana_en $end
-$var reg 1 ,( gpio_ana_pol $end
-$var reg 1 -( gpio_ana_sel $end
-$var reg 3 C( gpio_dm [2:0] $end
-$var reg 1 /( gpio_holdover $end
-$var reg 1 0( gpio_ib_mode_sel $end
-$var reg 1 D( gpio_inenb $end
-$var reg 1 E( gpio_outenb $end
-$var reg 1 3( gpio_slow_sel $end
-$var reg 1 4( gpio_vtrip_sel $end
-$var reg 1 F( mgmt_ena $end
-$var reg 13 G( shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 H( A $end
-$var wire 1 :( VGND $end
-$var wire 1 :( VNB $end
-$var wire 1 8( VPB $end
-$var wire 1 8( VPWR $end
-$var wire 1 <( Z $end
-$var wire 1 A( TE $end
-$scope module base $end
-$var wire 1 H( A $end
-$var wire 1 :( VGND $end
-$var wire 1 :( VNB $end
-$var wire 1 8( VPB $end
-$var wire 1 8( VPWR $end
-$var wire 1 <( Z $end
-$var wire 1 I( pwrgood_pp0_out_A $end
-$var wire 1 J( pwrgood_pp1_out_TE $end
-$var wire 1 A( TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 ;( VGND $end
-$var wire 1 ;( VNB $end
-$var wire 1 9( VPB $end
-$var wire 1 9( VPWR $end
-$var wire 1 K( LO $end
-$var wire 1 A( HI $end
-$scope module base $end
-$var wire 1 A( HI $end
-$var wire 1 K( LO $end
-$var wire 1 ;( VGND $end
-$var wire 1 ;( VNB $end
-$var wire 1 9( VPB $end
-$var wire 1 9( VPWR $end
-$var wire 1 L( pulldown0_out_LO $end
-$var wire 1 M( pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[15] $end
-$var wire 1 N( int_reset $end
-$var wire 1 O( load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 P( mgmt_gpio_out $end
-$var wire 1 Q( pad_gpio_ana_en $end
-$var wire 1 R( pad_gpio_ana_pol $end
-$var wire 1 S( pad_gpio_ana_sel $end
-$var wire 3 T( pad_gpio_dm [2:0] $end
-$var wire 1 U( pad_gpio_holdover $end
-$var wire 1 V( pad_gpio_ib_mode_sel $end
-$var wire 1 W( pad_gpio_in $end
-$var wire 1 X( pad_gpio_inenb $end
-$var wire 1 Y( pad_gpio_slow_sel $end
-$var wire 1 Z( pad_gpio_vtrip_sel $end
-$var wire 1 [( serial_data_in $end
-$var wire 1 \( user_gpio_oeb $end
-$var wire 1 ]( user_gpio_out $end
-$var wire 1 ^( vccd $end
-$var wire 1 _( vccd1 $end
-$var wire 1 `( vssd $end
-$var wire 1 a( vssd1 $end
-$var wire 1 b( user_gpio_in $end
-$var wire 1 c( serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 d( pad_gpio_outenb $end
-$var wire 1 e( pad_gpio_out $end
-$var wire 1 f( mgmt_gpio_in $end
-$var wire 1 g( gpio_logic1 $end
-$var wire 1 h( gpio_in_unbuf $end
-$var reg 1 Q( gpio_ana_en $end
-$var reg 1 R( gpio_ana_pol $end
-$var reg 1 S( gpio_ana_sel $end
-$var reg 3 i( gpio_dm [2:0] $end
-$var reg 1 U( gpio_holdover $end
-$var reg 1 V( gpio_ib_mode_sel $end
-$var reg 1 j( gpio_inenb $end
-$var reg 1 k( gpio_outenb $end
-$var reg 1 Y( gpio_slow_sel $end
-$var reg 1 Z( gpio_vtrip_sel $end
-$var reg 1 l( mgmt_ena $end
-$var reg 13 m( shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 n( A $end
-$var wire 1 `( VGND $end
-$var wire 1 `( VNB $end
-$var wire 1 ^( VPB $end
-$var wire 1 ^( VPWR $end
-$var wire 1 b( Z $end
-$var wire 1 g( TE $end
-$scope module base $end
-$var wire 1 n( A $end
-$var wire 1 `( VGND $end
-$var wire 1 `( VNB $end
-$var wire 1 ^( VPB $end
-$var wire 1 ^( VPWR $end
-$var wire 1 b( Z $end
-$var wire 1 o( pwrgood_pp0_out_A $end
-$var wire 1 p( pwrgood_pp1_out_TE $end
-$var wire 1 g( TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 a( VGND $end
-$var wire 1 a( VNB $end
-$var wire 1 _( VPB $end
-$var wire 1 _( VPWR $end
-$var wire 1 q( LO $end
-$var wire 1 g( HI $end
-$scope module base $end
-$var wire 1 g( HI $end
-$var wire 1 q( LO $end
-$var wire 1 a( VGND $end
-$var wire 1 a( VNB $end
-$var wire 1 _( VPB $end
-$var wire 1 _( VPWR $end
-$var wire 1 r( pulldown0_out_LO $end
-$var wire 1 s( pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[16] $end
-$var wire 1 t( int_reset $end
-$var wire 1 u( load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 v( mgmt_gpio_out $end
-$var wire 1 w( pad_gpio_ana_en $end
-$var wire 1 x( pad_gpio_ana_pol $end
-$var wire 1 y( pad_gpio_ana_sel $end
-$var wire 3 z( pad_gpio_dm [2:0] $end
-$var wire 1 {( pad_gpio_holdover $end
-$var wire 1 |( pad_gpio_ib_mode_sel $end
-$var wire 1 }( pad_gpio_in $end
-$var wire 1 ~( pad_gpio_inenb $end
-$var wire 1 !) pad_gpio_slow_sel $end
-$var wire 1 ") pad_gpio_vtrip_sel $end
-$var wire 1 #) serial_data_in $end
-$var wire 1 $) user_gpio_oeb $end
-$var wire 1 %) user_gpio_out $end
-$var wire 1 &) vccd $end
-$var wire 1 ') vccd1 $end
-$var wire 1 () vssd $end
-$var wire 1 )) vssd1 $end
-$var wire 1 *) user_gpio_in $end
-$var wire 1 +) serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 ,) pad_gpio_outenb $end
-$var wire 1 -) pad_gpio_out $end
-$var wire 1 .) mgmt_gpio_in $end
-$var wire 1 /) gpio_logic1 $end
-$var wire 1 0) gpio_in_unbuf $end
-$var reg 1 w( gpio_ana_en $end
-$var reg 1 x( gpio_ana_pol $end
-$var reg 1 y( gpio_ana_sel $end
-$var reg 3 1) gpio_dm [2:0] $end
-$var reg 1 {( gpio_holdover $end
-$var reg 1 |( gpio_ib_mode_sel $end
-$var reg 1 2) gpio_inenb $end
-$var reg 1 3) gpio_outenb $end
-$var reg 1 !) gpio_slow_sel $end
-$var reg 1 ") gpio_vtrip_sel $end
-$var reg 1 4) mgmt_ena $end
-$var reg 13 5) shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 6) A $end
-$var wire 1 () VGND $end
-$var wire 1 () VNB $end
-$var wire 1 &) VPB $end
-$var wire 1 &) VPWR $end
-$var wire 1 *) Z $end
-$var wire 1 /) TE $end
-$scope module base $end
-$var wire 1 6) A $end
-$var wire 1 () VGND $end
-$var wire 1 () VNB $end
-$var wire 1 &) VPB $end
-$var wire 1 &) VPWR $end
-$var wire 1 *) Z $end
-$var wire 1 7) pwrgood_pp0_out_A $end
-$var wire 1 8) pwrgood_pp1_out_TE $end
-$var wire 1 /) TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 )) VGND $end
-$var wire 1 )) VNB $end
-$var wire 1 ') VPB $end
-$var wire 1 ') VPWR $end
-$var wire 1 9) LO $end
-$var wire 1 /) HI $end
-$scope module base $end
-$var wire 1 /) HI $end
-$var wire 1 9) LO $end
-$var wire 1 )) VGND $end
-$var wire 1 )) VNB $end
-$var wire 1 ') VPB $end
-$var wire 1 ') VPWR $end
-$var wire 1 :) pulldown0_out_LO $end
-$var wire 1 ;) pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[17] $end
-$var wire 1 <) int_reset $end
-$var wire 1 =) load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 >) mgmt_gpio_out $end
-$var wire 1 ?) pad_gpio_ana_en $end
-$var wire 1 @) pad_gpio_ana_pol $end
-$var wire 1 A) pad_gpio_ana_sel $end
-$var wire 3 B) pad_gpio_dm [2:0] $end
-$var wire 1 C) pad_gpio_holdover $end
-$var wire 1 D) pad_gpio_ib_mode_sel $end
-$var wire 1 E) pad_gpio_in $end
-$var wire 1 F) pad_gpio_inenb $end
-$var wire 1 G) pad_gpio_slow_sel $end
-$var wire 1 H) pad_gpio_vtrip_sel $end
-$var wire 1 I) serial_data_in $end
-$var wire 1 J) user_gpio_oeb $end
-$var wire 1 K) user_gpio_out $end
-$var wire 1 L) vccd $end
-$var wire 1 M) vccd1 $end
-$var wire 1 N) vssd $end
-$var wire 1 O) vssd1 $end
-$var wire 1 P) user_gpio_in $end
-$var wire 1 Q) serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 R) pad_gpio_outenb $end
-$var wire 1 S) pad_gpio_out $end
-$var wire 1 T) mgmt_gpio_in $end
-$var wire 1 U) gpio_logic1 $end
-$var wire 1 V) gpio_in_unbuf $end
-$var reg 1 ?) gpio_ana_en $end
-$var reg 1 @) gpio_ana_pol $end
-$var reg 1 A) gpio_ana_sel $end
-$var reg 3 W) gpio_dm [2:0] $end
-$var reg 1 C) gpio_holdover $end
-$var reg 1 D) gpio_ib_mode_sel $end
-$var reg 1 X) gpio_inenb $end
-$var reg 1 Y) gpio_outenb $end
-$var reg 1 G) gpio_slow_sel $end
-$var reg 1 H) gpio_vtrip_sel $end
-$var reg 1 Z) mgmt_ena $end
-$var reg 13 [) shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 \) A $end
-$var wire 1 N) VGND $end
-$var wire 1 N) VNB $end
-$var wire 1 L) VPB $end
-$var wire 1 L) VPWR $end
-$var wire 1 P) Z $end
-$var wire 1 U) TE $end
-$scope module base $end
-$var wire 1 \) A $end
-$var wire 1 N) VGND $end
-$var wire 1 N) VNB $end
-$var wire 1 L) VPB $end
-$var wire 1 L) VPWR $end
-$var wire 1 P) Z $end
-$var wire 1 ]) pwrgood_pp0_out_A $end
-$var wire 1 ^) pwrgood_pp1_out_TE $end
-$var wire 1 U) TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 O) VGND $end
-$var wire 1 O) VNB $end
-$var wire 1 M) VPB $end
-$var wire 1 M) VPWR $end
-$var wire 1 _) LO $end
-$var wire 1 U) HI $end
-$scope module base $end
-$var wire 1 U) HI $end
-$var wire 1 _) LO $end
-$var wire 1 O) VGND $end
-$var wire 1 O) VNB $end
-$var wire 1 M) VPB $end
-$var wire 1 M) VPWR $end
-$var wire 1 `) pulldown0_out_LO $end
-$var wire 1 a) pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[18] $end
-$var wire 1 b) int_reset $end
-$var wire 1 c) load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 d) mgmt_gpio_out $end
-$var wire 1 e) pad_gpio_ana_en $end
-$var wire 1 f) pad_gpio_ana_pol $end
-$var wire 1 g) pad_gpio_ana_sel $end
-$var wire 3 h) pad_gpio_dm [2:0] $end
-$var wire 1 i) pad_gpio_holdover $end
-$var wire 1 j) pad_gpio_ib_mode_sel $end
-$var wire 1 k) pad_gpio_in $end
-$var wire 1 l) pad_gpio_inenb $end
-$var wire 1 m) pad_gpio_slow_sel $end
-$var wire 1 n) pad_gpio_vtrip_sel $end
-$var wire 1 o) serial_data_in $end
-$var wire 1 p) user_gpio_oeb $end
-$var wire 1 q) user_gpio_out $end
-$var wire 1 r) vccd $end
-$var wire 1 s) vccd1 $end
-$var wire 1 t) vssd $end
-$var wire 1 u) vssd1 $end
-$var wire 1 v) user_gpio_in $end
-$var wire 1 w) serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 x) pad_gpio_outenb $end
-$var wire 1 y) pad_gpio_out $end
-$var wire 1 z) mgmt_gpio_in $end
-$var wire 1 {) gpio_logic1 $end
-$var wire 1 |) gpio_in_unbuf $end
-$var reg 1 e) gpio_ana_en $end
-$var reg 1 f) gpio_ana_pol $end
-$var reg 1 g) gpio_ana_sel $end
-$var reg 3 }) gpio_dm [2:0] $end
-$var reg 1 i) gpio_holdover $end
-$var reg 1 j) gpio_ib_mode_sel $end
-$var reg 1 ~) gpio_inenb $end
-$var reg 1 !* gpio_outenb $end
-$var reg 1 m) gpio_slow_sel $end
-$var reg 1 n) gpio_vtrip_sel $end
-$var reg 1 "* mgmt_ena $end
-$var reg 13 #* shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 $* A $end
-$var wire 1 t) VGND $end
-$var wire 1 t) VNB $end
-$var wire 1 r) VPB $end
-$var wire 1 r) VPWR $end
-$var wire 1 v) Z $end
-$var wire 1 {) TE $end
-$scope module base $end
-$var wire 1 $* A $end
-$var wire 1 t) VGND $end
-$var wire 1 t) VNB $end
-$var wire 1 r) VPB $end
-$var wire 1 r) VPWR $end
-$var wire 1 v) Z $end
-$var wire 1 %* pwrgood_pp0_out_A $end
-$var wire 1 &* pwrgood_pp1_out_TE $end
-$var wire 1 {) TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 u) VGND $end
-$var wire 1 u) VNB $end
-$var wire 1 s) VPB $end
-$var wire 1 s) VPWR $end
-$var wire 1 '* LO $end
-$var wire 1 {) HI $end
-$scope module base $end
-$var wire 1 {) HI $end
-$var wire 1 '* LO $end
-$var wire 1 u) VGND $end
-$var wire 1 u) VNB $end
-$var wire 1 s) VPB $end
-$var wire 1 s) VPWR $end
-$var wire 1 (* pulldown0_out_LO $end
-$var wire 1 )* pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[19] $end
-$var wire 1 ** int_reset $end
-$var wire 1 +* load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 ,* mgmt_gpio_out $end
-$var wire 1 -* pad_gpio_ana_en $end
-$var wire 1 .* pad_gpio_ana_pol $end
-$var wire 1 /* pad_gpio_ana_sel $end
-$var wire 3 0* pad_gpio_dm [2:0] $end
-$var wire 1 1* pad_gpio_holdover $end
-$var wire 1 2* pad_gpio_ib_mode_sel $end
-$var wire 1 3* pad_gpio_in $end
-$var wire 1 4* pad_gpio_inenb $end
-$var wire 1 5* pad_gpio_slow_sel $end
-$var wire 1 6* pad_gpio_vtrip_sel $end
-$var wire 1 7* serial_data_in $end
-$var wire 1 8* user_gpio_oeb $end
-$var wire 1 9* user_gpio_out $end
-$var wire 1 :* vccd $end
-$var wire 1 ;* vccd1 $end
-$var wire 1 <* vssd $end
-$var wire 1 =* vssd1 $end
-$var wire 1 >* user_gpio_in $end
-$var wire 1 ?* serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 @* pad_gpio_outenb $end
-$var wire 1 A* pad_gpio_out $end
-$var wire 1 B* mgmt_gpio_in $end
-$var wire 1 C* gpio_logic1 $end
-$var wire 1 D* gpio_in_unbuf $end
-$var reg 1 -* gpio_ana_en $end
-$var reg 1 .* gpio_ana_pol $end
-$var reg 1 /* gpio_ana_sel $end
-$var reg 3 E* gpio_dm [2:0] $end
-$var reg 1 1* gpio_holdover $end
-$var reg 1 2* gpio_ib_mode_sel $end
-$var reg 1 F* gpio_inenb $end
-$var reg 1 G* gpio_outenb $end
-$var reg 1 5* gpio_slow_sel $end
-$var reg 1 6* gpio_vtrip_sel $end
-$var reg 1 H* mgmt_ena $end
-$var reg 13 I* shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 J* A $end
-$var wire 1 <* VGND $end
-$var wire 1 <* VNB $end
-$var wire 1 :* VPB $end
-$var wire 1 :* VPWR $end
-$var wire 1 >* Z $end
-$var wire 1 C* TE $end
-$scope module base $end
-$var wire 1 J* A $end
-$var wire 1 <* VGND $end
-$var wire 1 <* VNB $end
-$var wire 1 :* VPB $end
-$var wire 1 :* VPWR $end
-$var wire 1 >* Z $end
-$var wire 1 K* pwrgood_pp0_out_A $end
-$var wire 1 L* pwrgood_pp1_out_TE $end
-$var wire 1 C* TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 =* VGND $end
-$var wire 1 =* VNB $end
-$var wire 1 ;* VPB $end
-$var wire 1 ;* VPWR $end
-$var wire 1 M* LO $end
-$var wire 1 C* HI $end
-$scope module base $end
-$var wire 1 C* HI $end
-$var wire 1 M* LO $end
-$var wire 1 =* VGND $end
-$var wire 1 =* VNB $end
-$var wire 1 ;* VPB $end
-$var wire 1 ;* VPWR $end
-$var wire 1 N* pulldown0_out_LO $end
-$var wire 1 O* pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[20] $end
-$var wire 1 P* int_reset $end
-$var wire 1 Q* load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 R* mgmt_gpio_out $end
-$var wire 1 S* pad_gpio_ana_en $end
-$var wire 1 T* pad_gpio_ana_pol $end
-$var wire 1 U* pad_gpio_ana_sel $end
-$var wire 3 V* pad_gpio_dm [2:0] $end
-$var wire 1 W* pad_gpio_holdover $end
-$var wire 1 X* pad_gpio_ib_mode_sel $end
-$var wire 1 Y* pad_gpio_in $end
-$var wire 1 Z* pad_gpio_inenb $end
-$var wire 1 [* pad_gpio_slow_sel $end
-$var wire 1 \* pad_gpio_vtrip_sel $end
-$var wire 1 ]* serial_data_in $end
-$var wire 1 ^* user_gpio_oeb $end
-$var wire 1 _* user_gpio_out $end
-$var wire 1 `* vccd $end
-$var wire 1 a* vccd1 $end
-$var wire 1 b* vssd $end
-$var wire 1 c* vssd1 $end
-$var wire 1 d* user_gpio_in $end
-$var wire 1 e* serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 f* pad_gpio_outenb $end
-$var wire 1 g* pad_gpio_out $end
-$var wire 1 h* mgmt_gpio_in $end
-$var wire 1 i* gpio_logic1 $end
-$var wire 1 j* gpio_in_unbuf $end
-$var reg 1 S* gpio_ana_en $end
-$var reg 1 T* gpio_ana_pol $end
-$var reg 1 U* gpio_ana_sel $end
-$var reg 3 k* gpio_dm [2:0] $end
-$var reg 1 W* gpio_holdover $end
-$var reg 1 X* gpio_ib_mode_sel $end
-$var reg 1 l* gpio_inenb $end
-$var reg 1 m* gpio_outenb $end
-$var reg 1 [* gpio_slow_sel $end
-$var reg 1 \* gpio_vtrip_sel $end
-$var reg 1 n* mgmt_ena $end
-$var reg 13 o* shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 p* A $end
-$var wire 1 b* VGND $end
-$var wire 1 b* VNB $end
-$var wire 1 `* VPB $end
-$var wire 1 `* VPWR $end
-$var wire 1 d* Z $end
-$var wire 1 i* TE $end
-$scope module base $end
-$var wire 1 p* A $end
-$var wire 1 b* VGND $end
-$var wire 1 b* VNB $end
-$var wire 1 `* VPB $end
-$var wire 1 `* VPWR $end
-$var wire 1 d* Z $end
-$var wire 1 q* pwrgood_pp0_out_A $end
-$var wire 1 r* pwrgood_pp1_out_TE $end
-$var wire 1 i* TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 c* VGND $end
-$var wire 1 c* VNB $end
-$var wire 1 a* VPB $end
-$var wire 1 a* VPWR $end
-$var wire 1 s* LO $end
-$var wire 1 i* HI $end
-$scope module base $end
-$var wire 1 i* HI $end
-$var wire 1 s* LO $end
-$var wire 1 c* VGND $end
-$var wire 1 c* VNB $end
-$var wire 1 a* VPB $end
-$var wire 1 a* VPWR $end
-$var wire 1 t* pulldown0_out_LO $end
-$var wire 1 u* pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[21] $end
-$var wire 1 v* int_reset $end
-$var wire 1 w* load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 x* mgmt_gpio_out $end
-$var wire 1 y* pad_gpio_ana_en $end
-$var wire 1 z* pad_gpio_ana_pol $end
-$var wire 1 {* pad_gpio_ana_sel $end
-$var wire 3 |* pad_gpio_dm [2:0] $end
-$var wire 1 }* pad_gpio_holdover $end
-$var wire 1 ~* pad_gpio_ib_mode_sel $end
-$var wire 1 !+ pad_gpio_in $end
-$var wire 1 "+ pad_gpio_inenb $end
-$var wire 1 #+ pad_gpio_slow_sel $end
-$var wire 1 $+ pad_gpio_vtrip_sel $end
-$var wire 1 %+ serial_data_in $end
-$var wire 1 &+ user_gpio_oeb $end
-$var wire 1 '+ user_gpio_out $end
-$var wire 1 (+ vccd $end
-$var wire 1 )+ vccd1 $end
-$var wire 1 *+ vssd $end
-$var wire 1 ++ vssd1 $end
-$var wire 1 ,+ user_gpio_in $end
-$var wire 1 -+ serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 .+ pad_gpio_outenb $end
-$var wire 1 /+ pad_gpio_out $end
-$var wire 1 0+ mgmt_gpio_in $end
-$var wire 1 1+ gpio_logic1 $end
-$var wire 1 2+ gpio_in_unbuf $end
-$var reg 1 y* gpio_ana_en $end
-$var reg 1 z* gpio_ana_pol $end
-$var reg 1 {* gpio_ana_sel $end
-$var reg 3 3+ gpio_dm [2:0] $end
-$var reg 1 }* gpio_holdover $end
-$var reg 1 ~* gpio_ib_mode_sel $end
-$var reg 1 4+ gpio_inenb $end
-$var reg 1 5+ gpio_outenb $end
-$var reg 1 #+ gpio_slow_sel $end
-$var reg 1 $+ gpio_vtrip_sel $end
-$var reg 1 6+ mgmt_ena $end
-$var reg 13 7+ shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 8+ A $end
-$var wire 1 *+ VGND $end
-$var wire 1 *+ VNB $end
-$var wire 1 (+ VPB $end
-$var wire 1 (+ VPWR $end
-$var wire 1 ,+ Z $end
-$var wire 1 1+ TE $end
-$scope module base $end
-$var wire 1 8+ A $end
-$var wire 1 *+ VGND $end
-$var wire 1 *+ VNB $end
-$var wire 1 (+ VPB $end
-$var wire 1 (+ VPWR $end
-$var wire 1 ,+ Z $end
-$var wire 1 9+ pwrgood_pp0_out_A $end
-$var wire 1 :+ pwrgood_pp1_out_TE $end
-$var wire 1 1+ TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 ++ VGND $end
-$var wire 1 ++ VNB $end
-$var wire 1 )+ VPB $end
-$var wire 1 )+ VPWR $end
-$var wire 1 ;+ LO $end
-$var wire 1 1+ HI $end
-$scope module base $end
-$var wire 1 1+ HI $end
-$var wire 1 ;+ LO $end
-$var wire 1 ++ VGND $end
-$var wire 1 ++ VNB $end
-$var wire 1 )+ VPB $end
-$var wire 1 )+ VPWR $end
-$var wire 1 <+ pulldown0_out_LO $end
-$var wire 1 =+ pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[22] $end
-$var wire 1 >+ int_reset $end
-$var wire 1 ?+ load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 @+ mgmt_gpio_out $end
-$var wire 1 A+ pad_gpio_ana_en $end
-$var wire 1 B+ pad_gpio_ana_pol $end
-$var wire 1 C+ pad_gpio_ana_sel $end
-$var wire 3 D+ pad_gpio_dm [2:0] $end
-$var wire 1 E+ pad_gpio_holdover $end
-$var wire 1 F+ pad_gpio_ib_mode_sel $end
-$var wire 1 G+ pad_gpio_in $end
-$var wire 1 H+ pad_gpio_inenb $end
-$var wire 1 I+ pad_gpio_slow_sel $end
-$var wire 1 J+ pad_gpio_vtrip_sel $end
-$var wire 1 K+ serial_data_in $end
-$var wire 1 L+ user_gpio_oeb $end
-$var wire 1 M+ user_gpio_out $end
-$var wire 1 N+ vccd $end
-$var wire 1 O+ vccd1 $end
-$var wire 1 P+ vssd $end
-$var wire 1 Q+ vssd1 $end
-$var wire 1 R+ user_gpio_in $end
-$var wire 1 S+ serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 T+ pad_gpio_outenb $end
-$var wire 1 U+ pad_gpio_out $end
-$var wire 1 V+ mgmt_gpio_in $end
-$var wire 1 W+ gpio_logic1 $end
-$var wire 1 X+ gpio_in_unbuf $end
-$var reg 1 A+ gpio_ana_en $end
-$var reg 1 B+ gpio_ana_pol $end
-$var reg 1 C+ gpio_ana_sel $end
-$var reg 3 Y+ gpio_dm [2:0] $end
-$var reg 1 E+ gpio_holdover $end
-$var reg 1 F+ gpio_ib_mode_sel $end
-$var reg 1 Z+ gpio_inenb $end
-$var reg 1 [+ gpio_outenb $end
-$var reg 1 I+ gpio_slow_sel $end
-$var reg 1 J+ gpio_vtrip_sel $end
-$var reg 1 \+ mgmt_ena $end
-$var reg 13 ]+ shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 ^+ A $end
-$var wire 1 P+ VGND $end
-$var wire 1 P+ VNB $end
-$var wire 1 N+ VPB $end
-$var wire 1 N+ VPWR $end
-$var wire 1 R+ Z $end
-$var wire 1 W+ TE $end
-$scope module base $end
-$var wire 1 ^+ A $end
-$var wire 1 P+ VGND $end
-$var wire 1 P+ VNB $end
-$var wire 1 N+ VPB $end
-$var wire 1 N+ VPWR $end
-$var wire 1 R+ Z $end
-$var wire 1 _+ pwrgood_pp0_out_A $end
-$var wire 1 `+ pwrgood_pp1_out_TE $end
-$var wire 1 W+ TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 Q+ VGND $end
-$var wire 1 Q+ VNB $end
-$var wire 1 O+ VPB $end
-$var wire 1 O+ VPWR $end
-$var wire 1 a+ LO $end
-$var wire 1 W+ HI $end
-$scope module base $end
-$var wire 1 W+ HI $end
-$var wire 1 a+ LO $end
-$var wire 1 Q+ VGND $end
-$var wire 1 Q+ VNB $end
-$var wire 1 O+ VPB $end
-$var wire 1 O+ VPWR $end
-$var wire 1 b+ pulldown0_out_LO $end
-$var wire 1 c+ pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[23] $end
-$var wire 1 d+ int_reset $end
-$var wire 1 e+ load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 f+ mgmt_gpio_out $end
-$var wire 1 g+ pad_gpio_ana_en $end
-$var wire 1 h+ pad_gpio_ana_pol $end
-$var wire 1 i+ pad_gpio_ana_sel $end
-$var wire 3 j+ pad_gpio_dm [2:0] $end
-$var wire 1 k+ pad_gpio_holdover $end
-$var wire 1 l+ pad_gpio_ib_mode_sel $end
-$var wire 1 m+ pad_gpio_in $end
-$var wire 1 n+ pad_gpio_inenb $end
-$var wire 1 o+ pad_gpio_slow_sel $end
-$var wire 1 p+ pad_gpio_vtrip_sel $end
-$var wire 1 q+ serial_data_in $end
-$var wire 1 r+ user_gpio_oeb $end
-$var wire 1 s+ user_gpio_out $end
-$var wire 1 t+ vccd $end
-$var wire 1 u+ vccd1 $end
-$var wire 1 v+ vssd $end
-$var wire 1 w+ vssd1 $end
-$var wire 1 x+ user_gpio_in $end
-$var wire 1 y+ serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 z+ pad_gpio_outenb $end
-$var wire 1 {+ pad_gpio_out $end
-$var wire 1 |+ mgmt_gpio_in $end
-$var wire 1 }+ gpio_logic1 $end
-$var wire 1 ~+ gpio_in_unbuf $end
-$var reg 1 g+ gpio_ana_en $end
-$var reg 1 h+ gpio_ana_pol $end
-$var reg 1 i+ gpio_ana_sel $end
-$var reg 3 !, gpio_dm [2:0] $end
-$var reg 1 k+ gpio_holdover $end
-$var reg 1 l+ gpio_ib_mode_sel $end
-$var reg 1 ", gpio_inenb $end
-$var reg 1 #, gpio_outenb $end
-$var reg 1 o+ gpio_slow_sel $end
-$var reg 1 p+ gpio_vtrip_sel $end
-$var reg 1 $, mgmt_ena $end
-$var reg 13 %, shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 &, A $end
-$var wire 1 v+ VGND $end
-$var wire 1 v+ VNB $end
-$var wire 1 t+ VPB $end
-$var wire 1 t+ VPWR $end
-$var wire 1 x+ Z $end
-$var wire 1 }+ TE $end
-$scope module base $end
-$var wire 1 &, A $end
-$var wire 1 v+ VGND $end
-$var wire 1 v+ VNB $end
-$var wire 1 t+ VPB $end
-$var wire 1 t+ VPWR $end
-$var wire 1 x+ Z $end
-$var wire 1 ', pwrgood_pp0_out_A $end
-$var wire 1 (, pwrgood_pp1_out_TE $end
-$var wire 1 }+ TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 w+ VGND $end
-$var wire 1 w+ VNB $end
-$var wire 1 u+ VPB $end
-$var wire 1 u+ VPWR $end
-$var wire 1 ), LO $end
-$var wire 1 }+ HI $end
-$scope module base $end
-$var wire 1 }+ HI $end
-$var wire 1 ), LO $end
-$var wire 1 w+ VGND $end
-$var wire 1 w+ VNB $end
-$var wire 1 u+ VPB $end
-$var wire 1 u+ VPWR $end
-$var wire 1 *, pulldown0_out_LO $end
-$var wire 1 +, pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[24] $end
-$var wire 1 ,, int_reset $end
-$var wire 1 -, load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 ., mgmt_gpio_out $end
-$var wire 1 /, pad_gpio_ana_en $end
-$var wire 1 0, pad_gpio_ana_pol $end
-$var wire 1 1, pad_gpio_ana_sel $end
-$var wire 3 2, pad_gpio_dm [2:0] $end
-$var wire 1 3, pad_gpio_holdover $end
-$var wire 1 4, pad_gpio_ib_mode_sel $end
-$var wire 1 5, pad_gpio_in $end
-$var wire 1 6, pad_gpio_inenb $end
-$var wire 1 7, pad_gpio_slow_sel $end
-$var wire 1 8, pad_gpio_vtrip_sel $end
-$var wire 1 9, serial_data_in $end
-$var wire 1 :, user_gpio_oeb $end
-$var wire 1 ;, user_gpio_out $end
-$var wire 1 <, vccd $end
-$var wire 1 =, vccd1 $end
-$var wire 1 >, vssd $end
-$var wire 1 ?, vssd1 $end
-$var wire 1 @, user_gpio_in $end
-$var wire 1 A, serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 B, pad_gpio_outenb $end
-$var wire 1 C, pad_gpio_out $end
-$var wire 1 D, mgmt_gpio_in $end
-$var wire 1 E, gpio_logic1 $end
-$var wire 1 F, gpio_in_unbuf $end
-$var reg 1 /, gpio_ana_en $end
-$var reg 1 0, gpio_ana_pol $end
-$var reg 1 1, gpio_ana_sel $end
-$var reg 3 G, gpio_dm [2:0] $end
-$var reg 1 3, gpio_holdover $end
-$var reg 1 4, gpio_ib_mode_sel $end
-$var reg 1 H, gpio_inenb $end
-$var reg 1 I, gpio_outenb $end
-$var reg 1 7, gpio_slow_sel $end
-$var reg 1 8, gpio_vtrip_sel $end
-$var reg 1 J, mgmt_ena $end
-$var reg 13 K, shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 L, A $end
-$var wire 1 >, VGND $end
-$var wire 1 >, VNB $end
-$var wire 1 <, VPB $end
-$var wire 1 <, VPWR $end
-$var wire 1 @, Z $end
-$var wire 1 E, TE $end
-$scope module base $end
-$var wire 1 L, A $end
-$var wire 1 >, VGND $end
-$var wire 1 >, VNB $end
-$var wire 1 <, VPB $end
-$var wire 1 <, VPWR $end
-$var wire 1 @, Z $end
-$var wire 1 M, pwrgood_pp0_out_A $end
-$var wire 1 N, pwrgood_pp1_out_TE $end
-$var wire 1 E, TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 ?, VGND $end
-$var wire 1 ?, VNB $end
-$var wire 1 =, VPB $end
-$var wire 1 =, VPWR $end
-$var wire 1 O, LO $end
-$var wire 1 E, HI $end
-$scope module base $end
-$var wire 1 E, HI $end
-$var wire 1 O, LO $end
-$var wire 1 ?, VGND $end
-$var wire 1 ?, VNB $end
-$var wire 1 =, VPB $end
-$var wire 1 =, VPWR $end
-$var wire 1 P, pulldown0_out_LO $end
-$var wire 1 Q, pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[25] $end
-$var wire 1 R, int_reset $end
-$var wire 1 S, load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 T, mgmt_gpio_out $end
-$var wire 1 U, pad_gpio_ana_en $end
-$var wire 1 V, pad_gpio_ana_pol $end
-$var wire 1 W, pad_gpio_ana_sel $end
-$var wire 3 X, pad_gpio_dm [2:0] $end
-$var wire 1 Y, pad_gpio_holdover $end
-$var wire 1 Z, pad_gpio_ib_mode_sel $end
-$var wire 1 [, pad_gpio_in $end
-$var wire 1 \, pad_gpio_inenb $end
-$var wire 1 ], pad_gpio_slow_sel $end
-$var wire 1 ^, pad_gpio_vtrip_sel $end
-$var wire 1 _, serial_data_in $end
-$var wire 1 `, user_gpio_oeb $end
-$var wire 1 a, user_gpio_out $end
-$var wire 1 b, vccd $end
-$var wire 1 c, vccd1 $end
-$var wire 1 d, vssd $end
-$var wire 1 e, vssd1 $end
-$var wire 1 f, user_gpio_in $end
-$var wire 1 g, serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 h, pad_gpio_outenb $end
-$var wire 1 i, pad_gpio_out $end
-$var wire 1 j, mgmt_gpio_in $end
-$var wire 1 k, gpio_logic1 $end
-$var wire 1 l, gpio_in_unbuf $end
-$var reg 1 U, gpio_ana_en $end
-$var reg 1 V, gpio_ana_pol $end
-$var reg 1 W, gpio_ana_sel $end
-$var reg 3 m, gpio_dm [2:0] $end
-$var reg 1 Y, gpio_holdover $end
-$var reg 1 Z, gpio_ib_mode_sel $end
-$var reg 1 n, gpio_inenb $end
-$var reg 1 o, gpio_outenb $end
-$var reg 1 ], gpio_slow_sel $end
-$var reg 1 ^, gpio_vtrip_sel $end
-$var reg 1 p, mgmt_ena $end
-$var reg 13 q, shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 r, A $end
-$var wire 1 d, VGND $end
-$var wire 1 d, VNB $end
-$var wire 1 b, VPB $end
-$var wire 1 b, VPWR $end
-$var wire 1 f, Z $end
-$var wire 1 k, TE $end
-$scope module base $end
-$var wire 1 r, A $end
-$var wire 1 d, VGND $end
-$var wire 1 d, VNB $end
-$var wire 1 b, VPB $end
-$var wire 1 b, VPWR $end
-$var wire 1 f, Z $end
-$var wire 1 s, pwrgood_pp0_out_A $end
-$var wire 1 t, pwrgood_pp1_out_TE $end
-$var wire 1 k, TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 e, VGND $end
-$var wire 1 e, VNB $end
-$var wire 1 c, VPB $end
-$var wire 1 c, VPWR $end
-$var wire 1 u, LO $end
-$var wire 1 k, HI $end
-$scope module base $end
-$var wire 1 k, HI $end
-$var wire 1 u, LO $end
-$var wire 1 e, VGND $end
-$var wire 1 e, VNB $end
-$var wire 1 c, VPB $end
-$var wire 1 c, VPWR $end
-$var wire 1 v, pulldown0_out_LO $end
-$var wire 1 w, pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[26] $end
-$var wire 1 x, int_reset $end
-$var wire 1 y, load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 z, mgmt_gpio_out $end
-$var wire 1 {, pad_gpio_ana_en $end
-$var wire 1 |, pad_gpio_ana_pol $end
-$var wire 1 }, pad_gpio_ana_sel $end
-$var wire 3 ~, pad_gpio_dm [2:0] $end
-$var wire 1 !- pad_gpio_holdover $end
-$var wire 1 "- pad_gpio_ib_mode_sel $end
-$var wire 1 #- pad_gpio_in $end
-$var wire 1 $- pad_gpio_inenb $end
-$var wire 1 %- pad_gpio_slow_sel $end
-$var wire 1 &- pad_gpio_vtrip_sel $end
-$var wire 1 '- serial_data_in $end
-$var wire 1 (- user_gpio_oeb $end
-$var wire 1 )- user_gpio_out $end
-$var wire 1 *- vccd $end
-$var wire 1 +- vccd1 $end
-$var wire 1 ,- vssd $end
-$var wire 1 -- vssd1 $end
-$var wire 1 .- user_gpio_in $end
-$var wire 1 /- serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 0- pad_gpio_outenb $end
-$var wire 1 1- pad_gpio_out $end
-$var wire 1 2- mgmt_gpio_in $end
-$var wire 1 3- gpio_logic1 $end
-$var wire 1 4- gpio_in_unbuf $end
-$var reg 1 {, gpio_ana_en $end
-$var reg 1 |, gpio_ana_pol $end
-$var reg 1 }, gpio_ana_sel $end
-$var reg 3 5- gpio_dm [2:0] $end
-$var reg 1 !- gpio_holdover $end
-$var reg 1 "- gpio_ib_mode_sel $end
-$var reg 1 6- gpio_inenb $end
-$var reg 1 7- gpio_outenb $end
-$var reg 1 %- gpio_slow_sel $end
-$var reg 1 &- gpio_vtrip_sel $end
-$var reg 1 8- mgmt_ena $end
-$var reg 13 9- shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 :- A $end
-$var wire 1 ,- VGND $end
-$var wire 1 ,- VNB $end
-$var wire 1 *- VPB $end
-$var wire 1 *- VPWR $end
-$var wire 1 .- Z $end
-$var wire 1 3- TE $end
-$scope module base $end
-$var wire 1 :- A $end
-$var wire 1 ,- VGND $end
-$var wire 1 ,- VNB $end
-$var wire 1 *- VPB $end
-$var wire 1 *- VPWR $end
-$var wire 1 .- Z $end
-$var wire 1 ;- pwrgood_pp0_out_A $end
-$var wire 1 <- pwrgood_pp1_out_TE $end
-$var wire 1 3- TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 -- VGND $end
-$var wire 1 -- VNB $end
-$var wire 1 +- VPB $end
-$var wire 1 +- VPWR $end
-$var wire 1 =- LO $end
-$var wire 1 3- HI $end
-$scope module base $end
-$var wire 1 3- HI $end
-$var wire 1 =- LO $end
-$var wire 1 -- VGND $end
-$var wire 1 -- VNB $end
-$var wire 1 +- VPB $end
-$var wire 1 +- VPWR $end
-$var wire 1 >- pulldown0_out_LO $end
-$var wire 1 ?- pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[27] $end
-$var wire 1 @- int_reset $end
-$var wire 1 A- load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 B- mgmt_gpio_out $end
-$var wire 1 C- pad_gpio_ana_en $end
-$var wire 1 D- pad_gpio_ana_pol $end
-$var wire 1 E- pad_gpio_ana_sel $end
-$var wire 3 F- pad_gpio_dm [2:0] $end
-$var wire 1 G- pad_gpio_holdover $end
-$var wire 1 H- pad_gpio_ib_mode_sel $end
-$var wire 1 I- pad_gpio_in $end
-$var wire 1 J- pad_gpio_inenb $end
-$var wire 1 K- pad_gpio_slow_sel $end
-$var wire 1 L- pad_gpio_vtrip_sel $end
-$var wire 1 M- serial_data_in $end
-$var wire 1 N- user_gpio_oeb $end
-$var wire 1 O- user_gpio_out $end
-$var wire 1 P- vccd $end
-$var wire 1 Q- vccd1 $end
-$var wire 1 R- vssd $end
-$var wire 1 S- vssd1 $end
-$var wire 1 T- user_gpio_in $end
-$var wire 1 U- serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 V- pad_gpio_outenb $end
-$var wire 1 W- pad_gpio_out $end
-$var wire 1 X- mgmt_gpio_in $end
-$var wire 1 Y- gpio_logic1 $end
-$var wire 1 Z- gpio_in_unbuf $end
-$var reg 1 C- gpio_ana_en $end
-$var reg 1 D- gpio_ana_pol $end
-$var reg 1 E- gpio_ana_sel $end
-$var reg 3 [- gpio_dm [2:0] $end
-$var reg 1 G- gpio_holdover $end
-$var reg 1 H- gpio_ib_mode_sel $end
-$var reg 1 \- gpio_inenb $end
-$var reg 1 ]- gpio_outenb $end
-$var reg 1 K- gpio_slow_sel $end
-$var reg 1 L- gpio_vtrip_sel $end
-$var reg 1 ^- mgmt_ena $end
-$var reg 13 _- shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 `- A $end
-$var wire 1 R- VGND $end
-$var wire 1 R- VNB $end
-$var wire 1 P- VPB $end
-$var wire 1 P- VPWR $end
-$var wire 1 T- Z $end
-$var wire 1 Y- TE $end
-$scope module base $end
-$var wire 1 `- A $end
-$var wire 1 R- VGND $end
-$var wire 1 R- VNB $end
-$var wire 1 P- VPB $end
-$var wire 1 P- VPWR $end
-$var wire 1 T- Z $end
-$var wire 1 a- pwrgood_pp0_out_A $end
-$var wire 1 b- pwrgood_pp1_out_TE $end
-$var wire 1 Y- TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 S- VGND $end
-$var wire 1 S- VNB $end
-$var wire 1 Q- VPB $end
-$var wire 1 Q- VPWR $end
-$var wire 1 c- LO $end
-$var wire 1 Y- HI $end
-$scope module base $end
-$var wire 1 Y- HI $end
-$var wire 1 c- LO $end
-$var wire 1 S- VGND $end
-$var wire 1 S- VNB $end
-$var wire 1 Q- VPB $end
-$var wire 1 Q- VPWR $end
-$var wire 1 d- pulldown0_out_LO $end
-$var wire 1 e- pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[28] $end
-$var wire 1 f- int_reset $end
-$var wire 1 g- load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 h- mgmt_gpio_out $end
-$var wire 1 i- pad_gpio_ana_en $end
-$var wire 1 j- pad_gpio_ana_pol $end
-$var wire 1 k- pad_gpio_ana_sel $end
-$var wire 3 l- pad_gpio_dm [2:0] $end
-$var wire 1 m- pad_gpio_holdover $end
-$var wire 1 n- pad_gpio_ib_mode_sel $end
-$var wire 1 o- pad_gpio_in $end
-$var wire 1 p- pad_gpio_inenb $end
-$var wire 1 q- pad_gpio_slow_sel $end
-$var wire 1 r- pad_gpio_vtrip_sel $end
-$var wire 1 s- serial_data_in $end
-$var wire 1 t- user_gpio_oeb $end
-$var wire 1 u- user_gpio_out $end
-$var wire 1 v- vccd $end
-$var wire 1 w- vccd1 $end
-$var wire 1 x- vssd $end
-$var wire 1 y- vssd1 $end
-$var wire 1 z- user_gpio_in $end
-$var wire 1 {- serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 |- pad_gpio_outenb $end
-$var wire 1 }- pad_gpio_out $end
-$var wire 1 ~- mgmt_gpio_in $end
-$var wire 1 !. gpio_logic1 $end
-$var wire 1 ". gpio_in_unbuf $end
-$var reg 1 i- gpio_ana_en $end
-$var reg 1 j- gpio_ana_pol $end
-$var reg 1 k- gpio_ana_sel $end
-$var reg 3 #. gpio_dm [2:0] $end
-$var reg 1 m- gpio_holdover $end
-$var reg 1 n- gpio_ib_mode_sel $end
-$var reg 1 $. gpio_inenb $end
-$var reg 1 %. gpio_outenb $end
-$var reg 1 q- gpio_slow_sel $end
-$var reg 1 r- gpio_vtrip_sel $end
-$var reg 1 &. mgmt_ena $end
-$var reg 13 '. shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 (. A $end
-$var wire 1 x- VGND $end
-$var wire 1 x- VNB $end
-$var wire 1 v- VPB $end
-$var wire 1 v- VPWR $end
-$var wire 1 z- Z $end
-$var wire 1 !. TE $end
-$scope module base $end
-$var wire 1 (. A $end
-$var wire 1 x- VGND $end
-$var wire 1 x- VNB $end
-$var wire 1 v- VPB $end
-$var wire 1 v- VPWR $end
-$var wire 1 z- Z $end
-$var wire 1 ). pwrgood_pp0_out_A $end
-$var wire 1 *. pwrgood_pp1_out_TE $end
-$var wire 1 !. TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 y- VGND $end
-$var wire 1 y- VNB $end
-$var wire 1 w- VPB $end
-$var wire 1 w- VPWR $end
-$var wire 1 +. LO $end
-$var wire 1 !. HI $end
-$scope module base $end
-$var wire 1 !. HI $end
-$var wire 1 +. LO $end
-$var wire 1 y- VGND $end
-$var wire 1 y- VNB $end
-$var wire 1 w- VPB $end
-$var wire 1 w- VPWR $end
-$var wire 1 ,. pulldown0_out_LO $end
-$var wire 1 -. pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[29] $end
-$var wire 1 .. int_reset $end
-$var wire 1 /. load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 0. mgmt_gpio_out $end
-$var wire 1 1. pad_gpio_ana_en $end
-$var wire 1 2. pad_gpio_ana_pol $end
-$var wire 1 3. pad_gpio_ana_sel $end
-$var wire 3 4. pad_gpio_dm [2:0] $end
-$var wire 1 5. pad_gpio_holdover $end
-$var wire 1 6. pad_gpio_ib_mode_sel $end
-$var wire 1 7. pad_gpio_in $end
-$var wire 1 8. pad_gpio_inenb $end
-$var wire 1 9. pad_gpio_slow_sel $end
-$var wire 1 :. pad_gpio_vtrip_sel $end
-$var wire 1 ;. serial_data_in $end
-$var wire 1 <. user_gpio_oeb $end
-$var wire 1 =. user_gpio_out $end
-$var wire 1 >. vccd $end
-$var wire 1 ?. vccd1 $end
-$var wire 1 @. vssd $end
-$var wire 1 A. vssd1 $end
-$var wire 1 B. user_gpio_in $end
-$var wire 1 C. serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 D. pad_gpio_outenb $end
-$var wire 1 E. pad_gpio_out $end
-$var wire 1 F. mgmt_gpio_in $end
-$var wire 1 G. gpio_logic1 $end
-$var wire 1 H. gpio_in_unbuf $end
-$var reg 1 1. gpio_ana_en $end
-$var reg 1 2. gpio_ana_pol $end
-$var reg 1 3. gpio_ana_sel $end
-$var reg 3 I. gpio_dm [2:0] $end
-$var reg 1 5. gpio_holdover $end
-$var reg 1 6. gpio_ib_mode_sel $end
-$var reg 1 J. gpio_inenb $end
-$var reg 1 K. gpio_outenb $end
-$var reg 1 9. gpio_slow_sel $end
-$var reg 1 :. gpio_vtrip_sel $end
-$var reg 1 L. mgmt_ena $end
-$var reg 13 M. shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 N. A $end
-$var wire 1 @. VGND $end
-$var wire 1 @. VNB $end
-$var wire 1 >. VPB $end
-$var wire 1 >. VPWR $end
-$var wire 1 B. Z $end
-$var wire 1 G. TE $end
-$scope module base $end
-$var wire 1 N. A $end
-$var wire 1 @. VGND $end
-$var wire 1 @. VNB $end
-$var wire 1 >. VPB $end
-$var wire 1 >. VPWR $end
-$var wire 1 B. Z $end
-$var wire 1 O. pwrgood_pp0_out_A $end
-$var wire 1 P. pwrgood_pp1_out_TE $end
-$var wire 1 G. TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 A. VGND $end
-$var wire 1 A. VNB $end
-$var wire 1 ?. VPB $end
-$var wire 1 ?. VPWR $end
-$var wire 1 Q. LO $end
-$var wire 1 G. HI $end
-$scope module base $end
-$var wire 1 G. HI $end
-$var wire 1 Q. LO $end
-$var wire 1 A. VGND $end
-$var wire 1 A. VNB $end
-$var wire 1 ?. VPB $end
-$var wire 1 ?. VPWR $end
-$var wire 1 R. pulldown0_out_LO $end
-$var wire 1 S. pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[30] $end
-$var wire 1 T. int_reset $end
-$var wire 1 U. load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 V. mgmt_gpio_out $end
-$var wire 1 W. pad_gpio_ana_en $end
-$var wire 1 X. pad_gpio_ana_pol $end
-$var wire 1 Y. pad_gpio_ana_sel $end
-$var wire 3 Z. pad_gpio_dm [2:0] $end
-$var wire 1 [. pad_gpio_holdover $end
-$var wire 1 \. pad_gpio_ib_mode_sel $end
-$var wire 1 ]. pad_gpio_in $end
-$var wire 1 ^. pad_gpio_inenb $end
-$var wire 1 _. pad_gpio_slow_sel $end
-$var wire 1 `. pad_gpio_vtrip_sel $end
-$var wire 1 a. serial_data_in $end
-$var wire 1 b. user_gpio_oeb $end
-$var wire 1 c. user_gpio_out $end
-$var wire 1 d. vccd $end
-$var wire 1 e. vccd1 $end
-$var wire 1 f. vssd $end
-$var wire 1 g. vssd1 $end
-$var wire 1 h. user_gpio_in $end
-$var wire 1 i. serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 j. pad_gpio_outenb $end
-$var wire 1 k. pad_gpio_out $end
-$var wire 1 l. mgmt_gpio_in $end
-$var wire 1 m. gpio_logic1 $end
-$var wire 1 n. gpio_in_unbuf $end
-$var reg 1 W. gpio_ana_en $end
-$var reg 1 X. gpio_ana_pol $end
-$var reg 1 Y. gpio_ana_sel $end
-$var reg 3 o. gpio_dm [2:0] $end
-$var reg 1 [. gpio_holdover $end
-$var reg 1 \. gpio_ib_mode_sel $end
-$var reg 1 p. gpio_inenb $end
-$var reg 1 q. gpio_outenb $end
-$var reg 1 _. gpio_slow_sel $end
-$var reg 1 `. gpio_vtrip_sel $end
-$var reg 1 r. mgmt_ena $end
-$var reg 13 s. shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 t. A $end
-$var wire 1 f. VGND $end
-$var wire 1 f. VNB $end
-$var wire 1 d. VPB $end
-$var wire 1 d. VPWR $end
-$var wire 1 h. Z $end
-$var wire 1 m. TE $end
-$scope module base $end
-$var wire 1 t. A $end
-$var wire 1 f. VGND $end
-$var wire 1 f. VNB $end
-$var wire 1 d. VPB $end
-$var wire 1 d. VPWR $end
-$var wire 1 h. Z $end
-$var wire 1 u. pwrgood_pp0_out_A $end
-$var wire 1 v. pwrgood_pp1_out_TE $end
-$var wire 1 m. TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 g. VGND $end
-$var wire 1 g. VNB $end
-$var wire 1 e. VPB $end
-$var wire 1 e. VPWR $end
-$var wire 1 w. LO $end
-$var wire 1 m. HI $end
-$scope module base $end
-$var wire 1 m. HI $end
-$var wire 1 w. LO $end
-$var wire 1 g. VGND $end
-$var wire 1 g. VNB $end
-$var wire 1 e. VPB $end
-$var wire 1 e. VPWR $end
-$var wire 1 x. pulldown0_out_LO $end
-$var wire 1 y. pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[31] $end
-$var wire 1 z. int_reset $end
-$var wire 1 {. load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 |. mgmt_gpio_out $end
-$var wire 1 }. pad_gpio_ana_en $end
-$var wire 1 ~. pad_gpio_ana_pol $end
-$var wire 1 !/ pad_gpio_ana_sel $end
-$var wire 3 "/ pad_gpio_dm [2:0] $end
-$var wire 1 #/ pad_gpio_holdover $end
-$var wire 1 $/ pad_gpio_ib_mode_sel $end
-$var wire 1 %/ pad_gpio_in $end
-$var wire 1 &/ pad_gpio_inenb $end
-$var wire 1 '/ pad_gpio_slow_sel $end
-$var wire 1 (/ pad_gpio_vtrip_sel $end
-$var wire 1 )/ serial_data_in $end
-$var wire 1 */ user_gpio_oeb $end
-$var wire 1 +/ user_gpio_out $end
-$var wire 1 ,/ vccd $end
-$var wire 1 -/ vccd1 $end
-$var wire 1 ./ vssd $end
-$var wire 1 // vssd1 $end
-$var wire 1 0/ user_gpio_in $end
-$var wire 1 1/ serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 2/ pad_gpio_outenb $end
-$var wire 1 3/ pad_gpio_out $end
-$var wire 1 4/ mgmt_gpio_in $end
-$var wire 1 5/ gpio_logic1 $end
-$var wire 1 6/ gpio_in_unbuf $end
-$var reg 1 }. gpio_ana_en $end
-$var reg 1 ~. gpio_ana_pol $end
-$var reg 1 !/ gpio_ana_sel $end
-$var reg 3 7/ gpio_dm [2:0] $end
-$var reg 1 #/ gpio_holdover $end
-$var reg 1 $/ gpio_ib_mode_sel $end
-$var reg 1 8/ gpio_inenb $end
-$var reg 1 9/ gpio_outenb $end
-$var reg 1 '/ gpio_slow_sel $end
-$var reg 1 (/ gpio_vtrip_sel $end
-$var reg 1 :/ mgmt_ena $end
-$var reg 13 ;/ shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 </ A $end
-$var wire 1 ./ VGND $end
-$var wire 1 ./ VNB $end
-$var wire 1 ,/ VPB $end
-$var wire 1 ,/ VPWR $end
-$var wire 1 0/ Z $end
-$var wire 1 5/ TE $end
-$scope module base $end
-$var wire 1 </ A $end
-$var wire 1 ./ VGND $end
-$var wire 1 ./ VNB $end
-$var wire 1 ,/ VPB $end
-$var wire 1 ,/ VPWR $end
-$var wire 1 0/ Z $end
-$var wire 1 =/ pwrgood_pp0_out_A $end
-$var wire 1 >/ pwrgood_pp1_out_TE $end
-$var wire 1 5/ TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 // VGND $end
-$var wire 1 // VNB $end
-$var wire 1 -/ VPB $end
-$var wire 1 -/ VPWR $end
-$var wire 1 ?/ LO $end
-$var wire 1 5/ HI $end
-$scope module base $end
-$var wire 1 5/ HI $end
-$var wire 1 ?/ LO $end
-$var wire 1 // VGND $end
-$var wire 1 // VNB $end
-$var wire 1 -/ VPB $end
-$var wire 1 -/ VPWR $end
-$var wire 1 @/ pulldown0_out_LO $end
-$var wire 1 A/ pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[32] $end
-$var wire 1 B/ int_reset $end
-$var wire 1 C/ load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 D/ mgmt_gpio_out $end
-$var wire 1 E/ pad_gpio_ana_en $end
-$var wire 1 F/ pad_gpio_ana_pol $end
-$var wire 1 G/ pad_gpio_ana_sel $end
-$var wire 3 H/ pad_gpio_dm [2:0] $end
-$var wire 1 I/ pad_gpio_holdover $end
-$var wire 1 J/ pad_gpio_ib_mode_sel $end
-$var wire 1 K/ pad_gpio_in $end
-$var wire 1 L/ pad_gpio_inenb $end
-$var wire 1 M/ pad_gpio_slow_sel $end
-$var wire 1 N/ pad_gpio_vtrip_sel $end
-$var wire 1 O/ serial_data_in $end
-$var wire 1 P/ user_gpio_oeb $end
-$var wire 1 Q/ user_gpio_out $end
-$var wire 1 R/ vccd $end
-$var wire 1 S/ vccd1 $end
-$var wire 1 T/ vssd $end
-$var wire 1 U/ vssd1 $end
-$var wire 1 V/ user_gpio_in $end
-$var wire 1 W/ serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 X/ pad_gpio_outenb $end
-$var wire 1 Y/ pad_gpio_out $end
-$var wire 1 Z/ mgmt_gpio_in $end
-$var wire 1 [/ gpio_logic1 $end
-$var wire 1 \/ gpio_in_unbuf $end
-$var reg 1 E/ gpio_ana_en $end
-$var reg 1 F/ gpio_ana_pol $end
-$var reg 1 G/ gpio_ana_sel $end
-$var reg 3 ]/ gpio_dm [2:0] $end
-$var reg 1 I/ gpio_holdover $end
-$var reg 1 J/ gpio_ib_mode_sel $end
-$var reg 1 ^/ gpio_inenb $end
-$var reg 1 _/ gpio_outenb $end
-$var reg 1 M/ gpio_slow_sel $end
-$var reg 1 N/ gpio_vtrip_sel $end
-$var reg 1 `/ mgmt_ena $end
-$var reg 13 a/ shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 b/ A $end
-$var wire 1 T/ VGND $end
-$var wire 1 T/ VNB $end
-$var wire 1 R/ VPB $end
-$var wire 1 R/ VPWR $end
-$var wire 1 V/ Z $end
-$var wire 1 [/ TE $end
-$scope module base $end
-$var wire 1 b/ A $end
-$var wire 1 T/ VGND $end
-$var wire 1 T/ VNB $end
-$var wire 1 R/ VPB $end
-$var wire 1 R/ VPWR $end
-$var wire 1 V/ Z $end
-$var wire 1 c/ pwrgood_pp0_out_A $end
-$var wire 1 d/ pwrgood_pp1_out_TE $end
-$var wire 1 [/ TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 U/ VGND $end
-$var wire 1 U/ VNB $end
-$var wire 1 S/ VPB $end
-$var wire 1 S/ VPWR $end
-$var wire 1 e/ LO $end
-$var wire 1 [/ HI $end
-$scope module base $end
-$var wire 1 [/ HI $end
-$var wire 1 e/ LO $end
-$var wire 1 U/ VGND $end
-$var wire 1 U/ VNB $end
-$var wire 1 S/ VPB $end
-$var wire 1 S/ VPWR $end
-$var wire 1 f/ pulldown0_out_LO $end
-$var wire 1 g/ pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[33] $end
-$var wire 1 h/ int_reset $end
-$var wire 1 i/ load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 j/ mgmt_gpio_out $end
-$var wire 1 k/ pad_gpio_ana_en $end
-$var wire 1 l/ pad_gpio_ana_pol $end
-$var wire 1 m/ pad_gpio_ana_sel $end
-$var wire 3 n/ pad_gpio_dm [2:0] $end
-$var wire 1 o/ pad_gpio_holdover $end
-$var wire 1 p/ pad_gpio_ib_mode_sel $end
-$var wire 1 q/ pad_gpio_in $end
-$var wire 1 r/ pad_gpio_inenb $end
-$var wire 1 s/ pad_gpio_slow_sel $end
-$var wire 1 t/ pad_gpio_vtrip_sel $end
-$var wire 1 u/ serial_data_in $end
-$var wire 1 v/ user_gpio_oeb $end
-$var wire 1 w/ user_gpio_out $end
-$var wire 1 x/ vccd $end
-$var wire 1 y/ vccd1 $end
-$var wire 1 z/ vssd $end
-$var wire 1 {/ vssd1 $end
-$var wire 1 |/ user_gpio_in $end
-$var wire 1 }/ serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 ~/ pad_gpio_outenb $end
-$var wire 1 !0 pad_gpio_out $end
-$var wire 1 "0 mgmt_gpio_in $end
-$var wire 1 #0 gpio_logic1 $end
-$var wire 1 $0 gpio_in_unbuf $end
-$var reg 1 k/ gpio_ana_en $end
-$var reg 1 l/ gpio_ana_pol $end
-$var reg 1 m/ gpio_ana_sel $end
-$var reg 3 %0 gpio_dm [2:0] $end
-$var reg 1 o/ gpio_holdover $end
-$var reg 1 p/ gpio_ib_mode_sel $end
-$var reg 1 &0 gpio_inenb $end
-$var reg 1 '0 gpio_outenb $end
-$var reg 1 s/ gpio_slow_sel $end
-$var reg 1 t/ gpio_vtrip_sel $end
-$var reg 1 (0 mgmt_ena $end
-$var reg 13 )0 shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 *0 A $end
-$var wire 1 z/ VGND $end
-$var wire 1 z/ VNB $end
-$var wire 1 x/ VPB $end
-$var wire 1 x/ VPWR $end
-$var wire 1 |/ Z $end
-$var wire 1 #0 TE $end
-$scope module base $end
-$var wire 1 *0 A $end
-$var wire 1 z/ VGND $end
-$var wire 1 z/ VNB $end
-$var wire 1 x/ VPB $end
-$var wire 1 x/ VPWR $end
-$var wire 1 |/ Z $end
-$var wire 1 +0 pwrgood_pp0_out_A $end
-$var wire 1 ,0 pwrgood_pp1_out_TE $end
-$var wire 1 #0 TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 {/ VGND $end
-$var wire 1 {/ VNB $end
-$var wire 1 y/ VPB $end
-$var wire 1 y/ VPWR $end
-$var wire 1 -0 LO $end
-$var wire 1 #0 HI $end
-$scope module base $end
-$var wire 1 #0 HI $end
-$var wire 1 -0 LO $end
-$var wire 1 {/ VGND $end
-$var wire 1 {/ VNB $end
-$var wire 1 y/ VPB $end
-$var wire 1 y/ VPWR $end
-$var wire 1 .0 pulldown0_out_LO $end
-$var wire 1 /0 pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[34] $end
-$var wire 1 00 int_reset $end
-$var wire 1 10 load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 20 mgmt_gpio_out $end
-$var wire 1 30 pad_gpio_ana_en $end
-$var wire 1 40 pad_gpio_ana_pol $end
-$var wire 1 50 pad_gpio_ana_sel $end
-$var wire 3 60 pad_gpio_dm [2:0] $end
-$var wire 1 70 pad_gpio_holdover $end
-$var wire 1 80 pad_gpio_ib_mode_sel $end
-$var wire 1 90 pad_gpio_in $end
-$var wire 1 :0 pad_gpio_inenb $end
-$var wire 1 ;0 pad_gpio_slow_sel $end
-$var wire 1 <0 pad_gpio_vtrip_sel $end
-$var wire 1 =0 serial_data_in $end
-$var wire 1 >0 user_gpio_oeb $end
-$var wire 1 ?0 user_gpio_out $end
-$var wire 1 @0 vccd $end
-$var wire 1 A0 vccd1 $end
-$var wire 1 B0 vssd $end
-$var wire 1 C0 vssd1 $end
-$var wire 1 D0 user_gpio_in $end
-$var wire 1 E0 serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 F0 pad_gpio_outenb $end
-$var wire 1 G0 pad_gpio_out $end
-$var wire 1 H0 mgmt_gpio_in $end
-$var wire 1 I0 gpio_logic1 $end
-$var wire 1 J0 gpio_in_unbuf $end
-$var reg 1 30 gpio_ana_en $end
-$var reg 1 40 gpio_ana_pol $end
-$var reg 1 50 gpio_ana_sel $end
-$var reg 3 K0 gpio_dm [2:0] $end
-$var reg 1 70 gpio_holdover $end
-$var reg 1 80 gpio_ib_mode_sel $end
-$var reg 1 L0 gpio_inenb $end
-$var reg 1 M0 gpio_outenb $end
-$var reg 1 ;0 gpio_slow_sel $end
-$var reg 1 <0 gpio_vtrip_sel $end
-$var reg 1 N0 mgmt_ena $end
-$var reg 13 O0 shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 P0 A $end
-$var wire 1 B0 VGND $end
-$var wire 1 B0 VNB $end
-$var wire 1 @0 VPB $end
-$var wire 1 @0 VPWR $end
-$var wire 1 D0 Z $end
-$var wire 1 I0 TE $end
-$scope module base $end
-$var wire 1 P0 A $end
-$var wire 1 B0 VGND $end
-$var wire 1 B0 VNB $end
-$var wire 1 @0 VPB $end
-$var wire 1 @0 VPWR $end
-$var wire 1 D0 Z $end
-$var wire 1 Q0 pwrgood_pp0_out_A $end
-$var wire 1 R0 pwrgood_pp1_out_TE $end
-$var wire 1 I0 TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 C0 VGND $end
-$var wire 1 C0 VNB $end
-$var wire 1 A0 VPB $end
-$var wire 1 A0 VPWR $end
-$var wire 1 S0 LO $end
-$var wire 1 I0 HI $end
-$scope module base $end
-$var wire 1 I0 HI $end
-$var wire 1 S0 LO $end
-$var wire 1 C0 VGND $end
-$var wire 1 C0 VNB $end
-$var wire 1 A0 VPB $end
-$var wire 1 A0 VPWR $end
-$var wire 1 T0 pulldown0_out_LO $end
-$var wire 1 U0 pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[35] $end
-$var wire 1 V0 int_reset $end
-$var wire 1 W0 load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 X0 mgmt_gpio_out $end
-$var wire 1 Y0 pad_gpio_ana_en $end
-$var wire 1 Z0 pad_gpio_ana_pol $end
-$var wire 1 [0 pad_gpio_ana_sel $end
-$var wire 3 \0 pad_gpio_dm [2:0] $end
-$var wire 1 ]0 pad_gpio_holdover $end
-$var wire 1 ^0 pad_gpio_ib_mode_sel $end
-$var wire 1 _0 pad_gpio_in $end
-$var wire 1 `0 pad_gpio_inenb $end
-$var wire 1 a0 pad_gpio_slow_sel $end
-$var wire 1 b0 pad_gpio_vtrip_sel $end
-$var wire 1 c0 serial_data_in $end
-$var wire 1 d0 user_gpio_oeb $end
-$var wire 1 e0 user_gpio_out $end
-$var wire 1 f0 vccd $end
-$var wire 1 g0 vccd1 $end
-$var wire 1 h0 vssd $end
-$var wire 1 i0 vssd1 $end
-$var wire 1 j0 user_gpio_in $end
-$var wire 1 k0 serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 l0 pad_gpio_outenb $end
-$var wire 1 m0 pad_gpio_out $end
-$var wire 1 n0 mgmt_gpio_in $end
-$var wire 1 o0 gpio_logic1 $end
-$var wire 1 p0 gpio_in_unbuf $end
-$var reg 1 Y0 gpio_ana_en $end
-$var reg 1 Z0 gpio_ana_pol $end
-$var reg 1 [0 gpio_ana_sel $end
-$var reg 3 q0 gpio_dm [2:0] $end
-$var reg 1 ]0 gpio_holdover $end
-$var reg 1 ^0 gpio_ib_mode_sel $end
-$var reg 1 r0 gpio_inenb $end
-$var reg 1 s0 gpio_outenb $end
-$var reg 1 a0 gpio_slow_sel $end
-$var reg 1 b0 gpio_vtrip_sel $end
-$var reg 1 t0 mgmt_ena $end
-$var reg 13 u0 shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 v0 A $end
-$var wire 1 h0 VGND $end
-$var wire 1 h0 VNB $end
-$var wire 1 f0 VPB $end
-$var wire 1 f0 VPWR $end
-$var wire 1 j0 Z $end
-$var wire 1 o0 TE $end
-$scope module base $end
-$var wire 1 v0 A $end
-$var wire 1 h0 VGND $end
-$var wire 1 h0 VNB $end
-$var wire 1 f0 VPB $end
-$var wire 1 f0 VPWR $end
-$var wire 1 j0 Z $end
-$var wire 1 w0 pwrgood_pp0_out_A $end
-$var wire 1 x0 pwrgood_pp1_out_TE $end
-$var wire 1 o0 TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 i0 VGND $end
-$var wire 1 i0 VNB $end
-$var wire 1 g0 VPB $end
-$var wire 1 g0 VPWR $end
-$var wire 1 y0 LO $end
-$var wire 1 o0 HI $end
-$scope module base $end
-$var wire 1 o0 HI $end
-$var wire 1 y0 LO $end
-$var wire 1 i0 VGND $end
-$var wire 1 i0 VNB $end
-$var wire 1 g0 VPB $end
-$var wire 1 g0 VPWR $end
-$var wire 1 z0 pulldown0_out_LO $end
-$var wire 1 {0 pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_control_in[36] $end
-$var wire 1 |0 int_reset $end
-$var wire 1 }0 load_data $end
-$var wire 1 7# mgmt_gpio_oeb $end
-$var wire 1 ~0 mgmt_gpio_out $end
-$var wire 1 !1 pad_gpio_ana_en $end
-$var wire 1 "1 pad_gpio_ana_pol $end
-$var wire 1 #1 pad_gpio_ana_sel $end
-$var wire 3 $1 pad_gpio_dm [2:0] $end
-$var wire 1 %1 pad_gpio_holdover $end
-$var wire 1 &1 pad_gpio_ib_mode_sel $end
-$var wire 1 '1 pad_gpio_in $end
-$var wire 1 (1 pad_gpio_inenb $end
-$var wire 1 )1 pad_gpio_slow_sel $end
-$var wire 1 *1 pad_gpio_vtrip_sel $end
-$var wire 1 +1 serial_data_in $end
-$var wire 1 ,1 user_gpio_oeb $end
-$var wire 1 -1 user_gpio_out $end
-$var wire 1 .1 vccd $end
-$var wire 1 /1 vccd1 $end
-$var wire 1 01 vssd $end
-$var wire 1 11 vssd1 $end
-$var wire 1 21 user_gpio_in $end
-$var wire 1 31 serial_data_out $end
-$var wire 1 t serial_clock $end
-$var wire 1 r resetn $end
-$var wire 1 41 pad_gpio_outenb $end
-$var wire 1 51 pad_gpio_out $end
-$var wire 1 61 mgmt_gpio_in $end
-$var wire 1 71 gpio_logic1 $end
-$var wire 1 81 gpio_in_unbuf $end
-$var reg 1 !1 gpio_ana_en $end
-$var reg 1 "1 gpio_ana_pol $end
-$var reg 1 #1 gpio_ana_sel $end
-$var reg 3 91 gpio_dm [2:0] $end
-$var reg 1 %1 gpio_holdover $end
-$var reg 1 &1 gpio_ib_mode_sel $end
-$var reg 1 :1 gpio_inenb $end
-$var reg 1 ;1 gpio_outenb $end
-$var reg 1 )1 gpio_slow_sel $end
-$var reg 1 *1 gpio_vtrip_sel $end
-$var reg 1 <1 mgmt_ena $end
-$var reg 13 =1 shift_register [12:0] $end
-$scope module gpio_in_buf $end
-$var wire 1 >1 A $end
-$var wire 1 01 VGND $end
-$var wire 1 01 VNB $end
-$var wire 1 .1 VPB $end
-$var wire 1 .1 VPWR $end
-$var wire 1 21 Z $end
-$var wire 1 71 TE $end
-$scope module base $end
-$var wire 1 >1 A $end
-$var wire 1 01 VGND $end
-$var wire 1 01 VNB $end
-$var wire 1 .1 VPB $end
-$var wire 1 .1 VPWR $end
-$var wire 1 21 Z $end
-$var wire 1 ?1 pwrgood_pp0_out_A $end
-$var wire 1 @1 pwrgood_pp1_out_TE $end
-$var wire 1 71 TE $end
-$upscope $end
-$upscope $end
-$scope module gpio_logic_high $end
-$var wire 1 11 VGND $end
-$var wire 1 11 VNB $end
-$var wire 1 /1 VPB $end
-$var wire 1 /1 VPWR $end
-$var wire 1 A1 LO $end
-$var wire 1 71 HI $end
-$scope module base $end
-$var wire 1 71 HI $end
-$var wire 1 A1 LO $end
-$var wire 1 11 VGND $end
-$var wire 1 11 VNB $end
-$var wire 1 /1 VPB $end
-$var wire 1 /1 VPWR $end
-$var wire 1 B1 pulldown0_out_LO $end
-$var wire 1 C1 pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module mgmt_buffers $end
-$var wire 32 D1 mprj_adr_o_core [31:0] $end
-$var wire 1 R mprj_cyc_o_core $end
-$var wire 32 E1 mprj_dat_o_core [31:0] $end
-$var wire 4 F1 mprj_sel_o_core [3:0] $end
-$var wire 1 V mprj_we_o_core $end
-$var wire 1 + vccd $end
-$var wire 1 + vccd1 $end
-$var wire 1 ! vssd $end
-$var wire 1 ! vssd1 $end
-$var wire 1 m user_resetn $end
-$var wire 1 $" user_clock2 $end
-$var wire 1 %" user_clock $end
-$var wire 1 i mprj_we_o_user $end
-$var wire 1 j mprj_stb_o_user $end
-$var wire 1 k mprj_stb_o_core $end
-$var wire 4 G1 mprj_sel_o_user [3:0] $end
-$var wire 74 H1 mprj_logic1 [73:0] $end
-$var wire 32 I1 mprj_dat_o_user [31:0] $end
-$var wire 1 #" mprj_cyc_o_user $end
-$var wire 32 J1 mprj_adr_o_user [31:0] $end
-$var wire 128 K1 la_output_core [127:0] $end
-$var wire 128 L1 la_oen [127:0] $end
-$var wire 128 M1 la_data_in_mprj [127:0] $end
-$var wire 1 B" caravel_rstn $end
-$var wire 1 C" caravel_clk2 $end
-$var wire 1 D" caravel_clk $end
-$scope module la_buf[0] $end
-$var wire 1 N1 A $end
-$var wire 1 O1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 P1 Z $end
-$scope module base $end
-$var wire 1 N1 A $end
-$var wire 1 O1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 P1 Z $end
-$var wire 1 Q1 pwrgood_pp0_out_A $end
-$var wire 1 R1 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[1] $end
-$var wire 1 S1 A $end
-$var wire 1 T1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 U1 Z $end
-$scope module base $end
-$var wire 1 S1 A $end
-$var wire 1 T1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 U1 Z $end
-$var wire 1 V1 pwrgood_pp0_out_A $end
-$var wire 1 W1 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[2] $end
-$var wire 1 X1 A $end
-$var wire 1 Y1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 Z1 Z $end
-$scope module base $end
-$var wire 1 X1 A $end
-$var wire 1 Y1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 Z1 Z $end
-$var wire 1 [1 pwrgood_pp0_out_A $end
-$var wire 1 \1 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[3] $end
-$var wire 1 ]1 A $end
-$var wire 1 ^1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 _1 Z $end
-$scope module base $end
-$var wire 1 ]1 A $end
-$var wire 1 ^1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 _1 Z $end
-$var wire 1 `1 pwrgood_pp0_out_A $end
-$var wire 1 a1 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[4] $end
-$var wire 1 b1 A $end
-$var wire 1 c1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 d1 Z $end
-$scope module base $end
-$var wire 1 b1 A $end
-$var wire 1 c1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 d1 Z $end
-$var wire 1 e1 pwrgood_pp0_out_A $end
-$var wire 1 f1 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[5] $end
-$var wire 1 g1 A $end
-$var wire 1 h1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 i1 Z $end
-$scope module base $end
-$var wire 1 g1 A $end
-$var wire 1 h1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 i1 Z $end
-$var wire 1 j1 pwrgood_pp0_out_A $end
-$var wire 1 k1 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[6] $end
-$var wire 1 l1 A $end
-$var wire 1 m1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 n1 Z $end
-$scope module base $end
-$var wire 1 l1 A $end
-$var wire 1 m1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 n1 Z $end
-$var wire 1 o1 pwrgood_pp0_out_A $end
-$var wire 1 p1 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[7] $end
-$var wire 1 q1 A $end
-$var wire 1 r1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 s1 Z $end
-$scope module base $end
-$var wire 1 q1 A $end
-$var wire 1 r1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 s1 Z $end
-$var wire 1 t1 pwrgood_pp0_out_A $end
-$var wire 1 u1 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[8] $end
-$var wire 1 v1 A $end
-$var wire 1 w1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 x1 Z $end
-$scope module base $end
-$var wire 1 v1 A $end
-$var wire 1 w1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 x1 Z $end
-$var wire 1 y1 pwrgood_pp0_out_A $end
-$var wire 1 z1 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[9] $end
-$var wire 1 {1 A $end
-$var wire 1 |1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 }1 Z $end
-$scope module base $end
-$var wire 1 {1 A $end
-$var wire 1 |1 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 }1 Z $end
-$var wire 1 ~1 pwrgood_pp0_out_A $end
-$var wire 1 !2 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[10] $end
-$var wire 1 "2 A $end
-$var wire 1 #2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 $2 Z $end
-$scope module base $end
-$var wire 1 "2 A $end
-$var wire 1 #2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 $2 Z $end
-$var wire 1 %2 pwrgood_pp0_out_A $end
-$var wire 1 &2 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[11] $end
-$var wire 1 '2 A $end
-$var wire 1 (2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 )2 Z $end
-$scope module base $end
-$var wire 1 '2 A $end
-$var wire 1 (2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 )2 Z $end
-$var wire 1 *2 pwrgood_pp0_out_A $end
-$var wire 1 +2 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[12] $end
-$var wire 1 ,2 A $end
-$var wire 1 -2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 .2 Z $end
-$scope module base $end
-$var wire 1 ,2 A $end
-$var wire 1 -2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 .2 Z $end
-$var wire 1 /2 pwrgood_pp0_out_A $end
-$var wire 1 02 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[13] $end
-$var wire 1 12 A $end
-$var wire 1 22 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 32 Z $end
-$scope module base $end
-$var wire 1 12 A $end
-$var wire 1 22 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 32 Z $end
-$var wire 1 42 pwrgood_pp0_out_A $end
-$var wire 1 52 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[14] $end
-$var wire 1 62 A $end
-$var wire 1 72 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 82 Z $end
-$scope module base $end
-$var wire 1 62 A $end
-$var wire 1 72 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 82 Z $end
-$var wire 1 92 pwrgood_pp0_out_A $end
-$var wire 1 :2 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[15] $end
-$var wire 1 ;2 A $end
-$var wire 1 <2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 =2 Z $end
-$scope module base $end
-$var wire 1 ;2 A $end
-$var wire 1 <2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 =2 Z $end
-$var wire 1 >2 pwrgood_pp0_out_A $end
-$var wire 1 ?2 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[16] $end
-$var wire 1 @2 A $end
-$var wire 1 A2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 B2 Z $end
-$scope module base $end
-$var wire 1 @2 A $end
-$var wire 1 A2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 B2 Z $end
-$var wire 1 C2 pwrgood_pp0_out_A $end
-$var wire 1 D2 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[17] $end
-$var wire 1 E2 A $end
-$var wire 1 F2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 G2 Z $end
-$scope module base $end
-$var wire 1 E2 A $end
-$var wire 1 F2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 G2 Z $end
-$var wire 1 H2 pwrgood_pp0_out_A $end
-$var wire 1 I2 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[18] $end
-$var wire 1 J2 A $end
-$var wire 1 K2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 L2 Z $end
-$scope module base $end
-$var wire 1 J2 A $end
-$var wire 1 K2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 L2 Z $end
-$var wire 1 M2 pwrgood_pp0_out_A $end
-$var wire 1 N2 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[19] $end
-$var wire 1 O2 A $end
-$var wire 1 P2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 Q2 Z $end
-$scope module base $end
-$var wire 1 O2 A $end
-$var wire 1 P2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 Q2 Z $end
-$var wire 1 R2 pwrgood_pp0_out_A $end
-$var wire 1 S2 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[20] $end
-$var wire 1 T2 A $end
-$var wire 1 U2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 V2 Z $end
-$scope module base $end
-$var wire 1 T2 A $end
-$var wire 1 U2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 V2 Z $end
-$var wire 1 W2 pwrgood_pp0_out_A $end
-$var wire 1 X2 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[21] $end
-$var wire 1 Y2 A $end
-$var wire 1 Z2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 [2 Z $end
-$scope module base $end
-$var wire 1 Y2 A $end
-$var wire 1 Z2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 [2 Z $end
-$var wire 1 \2 pwrgood_pp0_out_A $end
-$var wire 1 ]2 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[22] $end
-$var wire 1 ^2 A $end
-$var wire 1 _2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 `2 Z $end
-$scope module base $end
-$var wire 1 ^2 A $end
-$var wire 1 _2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 `2 Z $end
-$var wire 1 a2 pwrgood_pp0_out_A $end
-$var wire 1 b2 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[23] $end
-$var wire 1 c2 A $end
-$var wire 1 d2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 e2 Z $end
-$scope module base $end
-$var wire 1 c2 A $end
-$var wire 1 d2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 e2 Z $end
-$var wire 1 f2 pwrgood_pp0_out_A $end
-$var wire 1 g2 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[24] $end
-$var wire 1 h2 A $end
-$var wire 1 i2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 j2 Z $end
-$scope module base $end
-$var wire 1 h2 A $end
-$var wire 1 i2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 j2 Z $end
-$var wire 1 k2 pwrgood_pp0_out_A $end
-$var wire 1 l2 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[25] $end
-$var wire 1 m2 A $end
-$var wire 1 n2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 o2 Z $end
-$scope module base $end
-$var wire 1 m2 A $end
-$var wire 1 n2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 o2 Z $end
-$var wire 1 p2 pwrgood_pp0_out_A $end
-$var wire 1 q2 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[26] $end
-$var wire 1 r2 A $end
-$var wire 1 s2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 t2 Z $end
-$scope module base $end
-$var wire 1 r2 A $end
-$var wire 1 s2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 t2 Z $end
-$var wire 1 u2 pwrgood_pp0_out_A $end
-$var wire 1 v2 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[27] $end
-$var wire 1 w2 A $end
-$var wire 1 x2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 y2 Z $end
-$scope module base $end
-$var wire 1 w2 A $end
-$var wire 1 x2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 y2 Z $end
-$var wire 1 z2 pwrgood_pp0_out_A $end
-$var wire 1 {2 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[28] $end
-$var wire 1 |2 A $end
-$var wire 1 }2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ~2 Z $end
-$scope module base $end
-$var wire 1 |2 A $end
-$var wire 1 }2 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ~2 Z $end
-$var wire 1 !3 pwrgood_pp0_out_A $end
-$var wire 1 "3 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[29] $end
-$var wire 1 #3 A $end
-$var wire 1 $3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 %3 Z $end
-$scope module base $end
-$var wire 1 #3 A $end
-$var wire 1 $3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 %3 Z $end
-$var wire 1 &3 pwrgood_pp0_out_A $end
-$var wire 1 '3 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[30] $end
-$var wire 1 (3 A $end
-$var wire 1 )3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 *3 Z $end
-$scope module base $end
-$var wire 1 (3 A $end
-$var wire 1 )3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 *3 Z $end
-$var wire 1 +3 pwrgood_pp0_out_A $end
-$var wire 1 ,3 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[31] $end
-$var wire 1 -3 A $end
-$var wire 1 .3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 /3 Z $end
-$scope module base $end
-$var wire 1 -3 A $end
-$var wire 1 .3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 /3 Z $end
-$var wire 1 03 pwrgood_pp0_out_A $end
-$var wire 1 13 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[32] $end
-$var wire 1 23 A $end
-$var wire 1 33 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 43 Z $end
-$scope module base $end
-$var wire 1 23 A $end
-$var wire 1 33 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 43 Z $end
-$var wire 1 53 pwrgood_pp0_out_A $end
-$var wire 1 63 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[33] $end
-$var wire 1 73 A $end
-$var wire 1 83 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 93 Z $end
-$scope module base $end
-$var wire 1 73 A $end
-$var wire 1 83 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 93 Z $end
-$var wire 1 :3 pwrgood_pp0_out_A $end
-$var wire 1 ;3 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[34] $end
-$var wire 1 <3 A $end
-$var wire 1 =3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 >3 Z $end
-$scope module base $end
-$var wire 1 <3 A $end
-$var wire 1 =3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 >3 Z $end
-$var wire 1 ?3 pwrgood_pp0_out_A $end
-$var wire 1 @3 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[35] $end
-$var wire 1 A3 A $end
-$var wire 1 B3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 C3 Z $end
-$scope module base $end
-$var wire 1 A3 A $end
-$var wire 1 B3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 C3 Z $end
-$var wire 1 D3 pwrgood_pp0_out_A $end
-$var wire 1 E3 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[36] $end
-$var wire 1 F3 A $end
-$var wire 1 G3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 H3 Z $end
-$scope module base $end
-$var wire 1 F3 A $end
-$var wire 1 G3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 H3 Z $end
-$var wire 1 I3 pwrgood_pp0_out_A $end
-$var wire 1 J3 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[37] $end
-$var wire 1 K3 A $end
-$var wire 1 L3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 M3 Z $end
-$scope module base $end
-$var wire 1 K3 A $end
-$var wire 1 L3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 M3 Z $end
-$var wire 1 N3 pwrgood_pp0_out_A $end
-$var wire 1 O3 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[38] $end
-$var wire 1 P3 A $end
-$var wire 1 Q3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 R3 Z $end
-$scope module base $end
-$var wire 1 P3 A $end
-$var wire 1 Q3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 R3 Z $end
-$var wire 1 S3 pwrgood_pp0_out_A $end
-$var wire 1 T3 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[39] $end
-$var wire 1 U3 A $end
-$var wire 1 V3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 W3 Z $end
-$scope module base $end
-$var wire 1 U3 A $end
-$var wire 1 V3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 W3 Z $end
-$var wire 1 X3 pwrgood_pp0_out_A $end
-$var wire 1 Y3 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[40] $end
-$var wire 1 Z3 A $end
-$var wire 1 [3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 \3 Z $end
-$scope module base $end
-$var wire 1 Z3 A $end
-$var wire 1 [3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 \3 Z $end
-$var wire 1 ]3 pwrgood_pp0_out_A $end
-$var wire 1 ^3 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[41] $end
-$var wire 1 _3 A $end
-$var wire 1 `3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 a3 Z $end
-$scope module base $end
-$var wire 1 _3 A $end
-$var wire 1 `3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 a3 Z $end
-$var wire 1 b3 pwrgood_pp0_out_A $end
-$var wire 1 c3 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[42] $end
-$var wire 1 d3 A $end
-$var wire 1 e3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 f3 Z $end
-$scope module base $end
-$var wire 1 d3 A $end
-$var wire 1 e3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 f3 Z $end
-$var wire 1 g3 pwrgood_pp0_out_A $end
-$var wire 1 h3 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[43] $end
-$var wire 1 i3 A $end
-$var wire 1 j3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 k3 Z $end
-$scope module base $end
-$var wire 1 i3 A $end
-$var wire 1 j3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 k3 Z $end
-$var wire 1 l3 pwrgood_pp0_out_A $end
-$var wire 1 m3 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[44] $end
-$var wire 1 n3 A $end
-$var wire 1 o3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 p3 Z $end
-$scope module base $end
-$var wire 1 n3 A $end
-$var wire 1 o3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 p3 Z $end
-$var wire 1 q3 pwrgood_pp0_out_A $end
-$var wire 1 r3 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[45] $end
-$var wire 1 s3 A $end
-$var wire 1 t3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 u3 Z $end
-$scope module base $end
-$var wire 1 s3 A $end
-$var wire 1 t3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 u3 Z $end
-$var wire 1 v3 pwrgood_pp0_out_A $end
-$var wire 1 w3 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[46] $end
-$var wire 1 x3 A $end
-$var wire 1 y3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 z3 Z $end
-$scope module base $end
-$var wire 1 x3 A $end
-$var wire 1 y3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 z3 Z $end
-$var wire 1 {3 pwrgood_pp0_out_A $end
-$var wire 1 |3 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[47] $end
-$var wire 1 }3 A $end
-$var wire 1 ~3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 !4 Z $end
-$scope module base $end
-$var wire 1 }3 A $end
-$var wire 1 ~3 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 !4 Z $end
-$var wire 1 "4 pwrgood_pp0_out_A $end
-$var wire 1 #4 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[48] $end
-$var wire 1 $4 A $end
-$var wire 1 %4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 &4 Z $end
-$scope module base $end
-$var wire 1 $4 A $end
-$var wire 1 %4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 &4 Z $end
-$var wire 1 '4 pwrgood_pp0_out_A $end
-$var wire 1 (4 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[49] $end
-$var wire 1 )4 A $end
-$var wire 1 *4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 +4 Z $end
-$scope module base $end
-$var wire 1 )4 A $end
-$var wire 1 *4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 +4 Z $end
-$var wire 1 ,4 pwrgood_pp0_out_A $end
-$var wire 1 -4 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[50] $end
-$var wire 1 .4 A $end
-$var wire 1 /4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 04 Z $end
-$scope module base $end
-$var wire 1 .4 A $end
-$var wire 1 /4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 04 Z $end
-$var wire 1 14 pwrgood_pp0_out_A $end
-$var wire 1 24 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[51] $end
-$var wire 1 34 A $end
-$var wire 1 44 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 54 Z $end
-$scope module base $end
-$var wire 1 34 A $end
-$var wire 1 44 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 54 Z $end
-$var wire 1 64 pwrgood_pp0_out_A $end
-$var wire 1 74 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[52] $end
-$var wire 1 84 A $end
-$var wire 1 94 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 :4 Z $end
-$scope module base $end
-$var wire 1 84 A $end
-$var wire 1 94 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 :4 Z $end
-$var wire 1 ;4 pwrgood_pp0_out_A $end
-$var wire 1 <4 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[53] $end
-$var wire 1 =4 A $end
-$var wire 1 >4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ?4 Z $end
-$scope module base $end
-$var wire 1 =4 A $end
-$var wire 1 >4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ?4 Z $end
-$var wire 1 @4 pwrgood_pp0_out_A $end
-$var wire 1 A4 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[54] $end
-$var wire 1 B4 A $end
-$var wire 1 C4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 D4 Z $end
-$scope module base $end
-$var wire 1 B4 A $end
-$var wire 1 C4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 D4 Z $end
-$var wire 1 E4 pwrgood_pp0_out_A $end
-$var wire 1 F4 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[55] $end
-$var wire 1 G4 A $end
-$var wire 1 H4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 I4 Z $end
-$scope module base $end
-$var wire 1 G4 A $end
-$var wire 1 H4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 I4 Z $end
-$var wire 1 J4 pwrgood_pp0_out_A $end
-$var wire 1 K4 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[56] $end
-$var wire 1 L4 A $end
-$var wire 1 M4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 N4 Z $end
-$scope module base $end
-$var wire 1 L4 A $end
-$var wire 1 M4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 N4 Z $end
-$var wire 1 O4 pwrgood_pp0_out_A $end
-$var wire 1 P4 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[57] $end
-$var wire 1 Q4 A $end
-$var wire 1 R4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 S4 Z $end
-$scope module base $end
-$var wire 1 Q4 A $end
-$var wire 1 R4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 S4 Z $end
-$var wire 1 T4 pwrgood_pp0_out_A $end
-$var wire 1 U4 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[58] $end
-$var wire 1 V4 A $end
-$var wire 1 W4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 X4 Z $end
-$scope module base $end
-$var wire 1 V4 A $end
-$var wire 1 W4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 X4 Z $end
-$var wire 1 Y4 pwrgood_pp0_out_A $end
-$var wire 1 Z4 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[59] $end
-$var wire 1 [4 A $end
-$var wire 1 \4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ]4 Z $end
-$scope module base $end
-$var wire 1 [4 A $end
-$var wire 1 \4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ]4 Z $end
-$var wire 1 ^4 pwrgood_pp0_out_A $end
-$var wire 1 _4 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[60] $end
-$var wire 1 `4 A $end
-$var wire 1 a4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 b4 Z $end
-$scope module base $end
-$var wire 1 `4 A $end
-$var wire 1 a4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 b4 Z $end
-$var wire 1 c4 pwrgood_pp0_out_A $end
-$var wire 1 d4 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[61] $end
-$var wire 1 e4 A $end
-$var wire 1 f4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 g4 Z $end
-$scope module base $end
-$var wire 1 e4 A $end
-$var wire 1 f4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 g4 Z $end
-$var wire 1 h4 pwrgood_pp0_out_A $end
-$var wire 1 i4 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[62] $end
-$var wire 1 j4 A $end
-$var wire 1 k4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 l4 Z $end
-$scope module base $end
-$var wire 1 j4 A $end
-$var wire 1 k4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 l4 Z $end
-$var wire 1 m4 pwrgood_pp0_out_A $end
-$var wire 1 n4 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[63] $end
-$var wire 1 o4 A $end
-$var wire 1 p4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 q4 Z $end
-$scope module base $end
-$var wire 1 o4 A $end
-$var wire 1 p4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 q4 Z $end
-$var wire 1 r4 pwrgood_pp0_out_A $end
-$var wire 1 s4 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[64] $end
-$var wire 1 t4 A $end
-$var wire 1 u4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 v4 Z $end
-$scope module base $end
-$var wire 1 t4 A $end
-$var wire 1 u4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 v4 Z $end
-$var wire 1 w4 pwrgood_pp0_out_A $end
-$var wire 1 x4 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[65] $end
-$var wire 1 y4 A $end
-$var wire 1 z4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 {4 Z $end
-$scope module base $end
-$var wire 1 y4 A $end
-$var wire 1 z4 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 {4 Z $end
-$var wire 1 |4 pwrgood_pp0_out_A $end
-$var wire 1 }4 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[66] $end
-$var wire 1 ~4 A $end
-$var wire 1 !5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 "5 Z $end
-$scope module base $end
-$var wire 1 ~4 A $end
-$var wire 1 !5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 "5 Z $end
-$var wire 1 #5 pwrgood_pp0_out_A $end
-$var wire 1 $5 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[67] $end
-$var wire 1 %5 A $end
-$var wire 1 &5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 '5 Z $end
-$scope module base $end
-$var wire 1 %5 A $end
-$var wire 1 &5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 '5 Z $end
-$var wire 1 (5 pwrgood_pp0_out_A $end
-$var wire 1 )5 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[68] $end
-$var wire 1 *5 A $end
-$var wire 1 +5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ,5 Z $end
-$scope module base $end
-$var wire 1 *5 A $end
-$var wire 1 +5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ,5 Z $end
-$var wire 1 -5 pwrgood_pp0_out_A $end
-$var wire 1 .5 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[69] $end
-$var wire 1 /5 A $end
-$var wire 1 05 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 15 Z $end
-$scope module base $end
-$var wire 1 /5 A $end
-$var wire 1 05 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 15 Z $end
-$var wire 1 25 pwrgood_pp0_out_A $end
-$var wire 1 35 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[70] $end
-$var wire 1 45 A $end
-$var wire 1 55 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 65 Z $end
-$scope module base $end
-$var wire 1 45 A $end
-$var wire 1 55 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 65 Z $end
-$var wire 1 75 pwrgood_pp0_out_A $end
-$var wire 1 85 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[71] $end
-$var wire 1 95 A $end
-$var wire 1 :5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ;5 Z $end
-$scope module base $end
-$var wire 1 95 A $end
-$var wire 1 :5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ;5 Z $end
-$var wire 1 <5 pwrgood_pp0_out_A $end
-$var wire 1 =5 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[72] $end
-$var wire 1 >5 A $end
-$var wire 1 ?5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 @5 Z $end
-$scope module base $end
-$var wire 1 >5 A $end
-$var wire 1 ?5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 @5 Z $end
-$var wire 1 A5 pwrgood_pp0_out_A $end
-$var wire 1 B5 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[73] $end
-$var wire 1 C5 A $end
-$var wire 1 D5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 E5 Z $end
-$scope module base $end
-$var wire 1 C5 A $end
-$var wire 1 D5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 E5 Z $end
-$var wire 1 F5 pwrgood_pp0_out_A $end
-$var wire 1 G5 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[74] $end
-$var wire 1 H5 A $end
-$var wire 1 I5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 J5 Z $end
-$scope module base $end
-$var wire 1 H5 A $end
-$var wire 1 I5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 J5 Z $end
-$var wire 1 K5 pwrgood_pp0_out_A $end
-$var wire 1 L5 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[75] $end
-$var wire 1 M5 A $end
-$var wire 1 N5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 O5 Z $end
-$scope module base $end
-$var wire 1 M5 A $end
-$var wire 1 N5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 O5 Z $end
-$var wire 1 P5 pwrgood_pp0_out_A $end
-$var wire 1 Q5 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[76] $end
-$var wire 1 R5 A $end
-$var wire 1 S5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 T5 Z $end
-$scope module base $end
-$var wire 1 R5 A $end
-$var wire 1 S5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 T5 Z $end
-$var wire 1 U5 pwrgood_pp0_out_A $end
-$var wire 1 V5 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[77] $end
-$var wire 1 W5 A $end
-$var wire 1 X5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 Y5 Z $end
-$scope module base $end
-$var wire 1 W5 A $end
-$var wire 1 X5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 Y5 Z $end
-$var wire 1 Z5 pwrgood_pp0_out_A $end
-$var wire 1 [5 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[78] $end
-$var wire 1 \5 A $end
-$var wire 1 ]5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ^5 Z $end
-$scope module base $end
-$var wire 1 \5 A $end
-$var wire 1 ]5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ^5 Z $end
-$var wire 1 _5 pwrgood_pp0_out_A $end
-$var wire 1 `5 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[79] $end
-$var wire 1 a5 A $end
-$var wire 1 b5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 c5 Z $end
-$scope module base $end
-$var wire 1 a5 A $end
-$var wire 1 b5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 c5 Z $end
-$var wire 1 d5 pwrgood_pp0_out_A $end
-$var wire 1 e5 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[80] $end
-$var wire 1 f5 A $end
-$var wire 1 g5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 h5 Z $end
-$scope module base $end
-$var wire 1 f5 A $end
-$var wire 1 g5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 h5 Z $end
-$var wire 1 i5 pwrgood_pp0_out_A $end
-$var wire 1 j5 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[81] $end
-$var wire 1 k5 A $end
-$var wire 1 l5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 m5 Z $end
-$scope module base $end
-$var wire 1 k5 A $end
-$var wire 1 l5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 m5 Z $end
-$var wire 1 n5 pwrgood_pp0_out_A $end
-$var wire 1 o5 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[82] $end
-$var wire 1 p5 A $end
-$var wire 1 q5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 r5 Z $end
-$scope module base $end
-$var wire 1 p5 A $end
-$var wire 1 q5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 r5 Z $end
-$var wire 1 s5 pwrgood_pp0_out_A $end
-$var wire 1 t5 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[83] $end
-$var wire 1 u5 A $end
-$var wire 1 v5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 w5 Z $end
-$scope module base $end
-$var wire 1 u5 A $end
-$var wire 1 v5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 w5 Z $end
-$var wire 1 x5 pwrgood_pp0_out_A $end
-$var wire 1 y5 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[84] $end
-$var wire 1 z5 A $end
-$var wire 1 {5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 |5 Z $end
-$scope module base $end
-$var wire 1 z5 A $end
-$var wire 1 {5 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 |5 Z $end
-$var wire 1 }5 pwrgood_pp0_out_A $end
-$var wire 1 ~5 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[85] $end
-$var wire 1 !6 A $end
-$var wire 1 "6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 #6 Z $end
-$scope module base $end
-$var wire 1 !6 A $end
-$var wire 1 "6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 #6 Z $end
-$var wire 1 $6 pwrgood_pp0_out_A $end
-$var wire 1 %6 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[86] $end
-$var wire 1 &6 A $end
-$var wire 1 '6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 (6 Z $end
-$scope module base $end
-$var wire 1 &6 A $end
-$var wire 1 '6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 (6 Z $end
-$var wire 1 )6 pwrgood_pp0_out_A $end
-$var wire 1 *6 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[87] $end
-$var wire 1 +6 A $end
-$var wire 1 ,6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 -6 Z $end
-$scope module base $end
-$var wire 1 +6 A $end
-$var wire 1 ,6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 -6 Z $end
-$var wire 1 .6 pwrgood_pp0_out_A $end
-$var wire 1 /6 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[88] $end
-$var wire 1 06 A $end
-$var wire 1 16 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 26 Z $end
-$scope module base $end
-$var wire 1 06 A $end
-$var wire 1 16 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 26 Z $end
-$var wire 1 36 pwrgood_pp0_out_A $end
-$var wire 1 46 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[89] $end
-$var wire 1 56 A $end
-$var wire 1 66 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 76 Z $end
-$scope module base $end
-$var wire 1 56 A $end
-$var wire 1 66 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 76 Z $end
-$var wire 1 86 pwrgood_pp0_out_A $end
-$var wire 1 96 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[90] $end
-$var wire 1 :6 A $end
-$var wire 1 ;6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 <6 Z $end
-$scope module base $end
-$var wire 1 :6 A $end
-$var wire 1 ;6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 <6 Z $end
-$var wire 1 =6 pwrgood_pp0_out_A $end
-$var wire 1 >6 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[91] $end
-$var wire 1 ?6 A $end
-$var wire 1 @6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 A6 Z $end
-$scope module base $end
-$var wire 1 ?6 A $end
-$var wire 1 @6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 A6 Z $end
-$var wire 1 B6 pwrgood_pp0_out_A $end
-$var wire 1 C6 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[92] $end
-$var wire 1 D6 A $end
-$var wire 1 E6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 F6 Z $end
-$scope module base $end
-$var wire 1 D6 A $end
-$var wire 1 E6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 F6 Z $end
-$var wire 1 G6 pwrgood_pp0_out_A $end
-$var wire 1 H6 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[93] $end
-$var wire 1 I6 A $end
-$var wire 1 J6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 K6 Z $end
-$scope module base $end
-$var wire 1 I6 A $end
-$var wire 1 J6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 K6 Z $end
-$var wire 1 L6 pwrgood_pp0_out_A $end
-$var wire 1 M6 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[94] $end
-$var wire 1 N6 A $end
-$var wire 1 O6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 P6 Z $end
-$scope module base $end
-$var wire 1 N6 A $end
-$var wire 1 O6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 P6 Z $end
-$var wire 1 Q6 pwrgood_pp0_out_A $end
-$var wire 1 R6 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[95] $end
-$var wire 1 S6 A $end
-$var wire 1 T6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 U6 Z $end
-$scope module base $end
-$var wire 1 S6 A $end
-$var wire 1 T6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 U6 Z $end
-$var wire 1 V6 pwrgood_pp0_out_A $end
-$var wire 1 W6 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[96] $end
-$var wire 1 X6 A $end
-$var wire 1 Y6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 Z6 Z $end
-$scope module base $end
-$var wire 1 X6 A $end
-$var wire 1 Y6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 Z6 Z $end
-$var wire 1 [6 pwrgood_pp0_out_A $end
-$var wire 1 \6 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[97] $end
-$var wire 1 ]6 A $end
-$var wire 1 ^6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 _6 Z $end
-$scope module base $end
-$var wire 1 ]6 A $end
-$var wire 1 ^6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 _6 Z $end
-$var wire 1 `6 pwrgood_pp0_out_A $end
-$var wire 1 a6 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[98] $end
-$var wire 1 b6 A $end
-$var wire 1 c6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 d6 Z $end
-$scope module base $end
-$var wire 1 b6 A $end
-$var wire 1 c6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 d6 Z $end
-$var wire 1 e6 pwrgood_pp0_out_A $end
-$var wire 1 f6 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[99] $end
-$var wire 1 g6 A $end
-$var wire 1 h6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 i6 Z $end
-$scope module base $end
-$var wire 1 g6 A $end
-$var wire 1 h6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 i6 Z $end
-$var wire 1 j6 pwrgood_pp0_out_A $end
-$var wire 1 k6 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[100] $end
-$var wire 1 l6 A $end
-$var wire 1 m6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 n6 Z $end
-$scope module base $end
-$var wire 1 l6 A $end
-$var wire 1 m6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 n6 Z $end
-$var wire 1 o6 pwrgood_pp0_out_A $end
-$var wire 1 p6 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[101] $end
-$var wire 1 q6 A $end
-$var wire 1 r6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 s6 Z $end
-$scope module base $end
-$var wire 1 q6 A $end
-$var wire 1 r6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 s6 Z $end
-$var wire 1 t6 pwrgood_pp0_out_A $end
-$var wire 1 u6 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[102] $end
-$var wire 1 v6 A $end
-$var wire 1 w6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 x6 Z $end
-$scope module base $end
-$var wire 1 v6 A $end
-$var wire 1 w6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 x6 Z $end
-$var wire 1 y6 pwrgood_pp0_out_A $end
-$var wire 1 z6 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[103] $end
-$var wire 1 {6 A $end
-$var wire 1 |6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 }6 Z $end
-$scope module base $end
-$var wire 1 {6 A $end
-$var wire 1 |6 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 }6 Z $end
-$var wire 1 ~6 pwrgood_pp0_out_A $end
-$var wire 1 !7 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[104] $end
-$var wire 1 "7 A $end
-$var wire 1 #7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 $7 Z $end
-$scope module base $end
-$var wire 1 "7 A $end
-$var wire 1 #7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 $7 Z $end
-$var wire 1 %7 pwrgood_pp0_out_A $end
-$var wire 1 &7 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[105] $end
-$var wire 1 '7 A $end
-$var wire 1 (7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 )7 Z $end
-$scope module base $end
-$var wire 1 '7 A $end
-$var wire 1 (7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 )7 Z $end
-$var wire 1 *7 pwrgood_pp0_out_A $end
-$var wire 1 +7 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[106] $end
-$var wire 1 ,7 A $end
-$var wire 1 -7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 .7 Z $end
-$scope module base $end
-$var wire 1 ,7 A $end
-$var wire 1 -7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 .7 Z $end
-$var wire 1 /7 pwrgood_pp0_out_A $end
-$var wire 1 07 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[107] $end
-$var wire 1 17 A $end
-$var wire 1 27 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 37 Z $end
-$scope module base $end
-$var wire 1 17 A $end
-$var wire 1 27 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 37 Z $end
-$var wire 1 47 pwrgood_pp0_out_A $end
-$var wire 1 57 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[108] $end
-$var wire 1 67 A $end
-$var wire 1 77 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 87 Z $end
-$scope module base $end
-$var wire 1 67 A $end
-$var wire 1 77 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 87 Z $end
-$var wire 1 97 pwrgood_pp0_out_A $end
-$var wire 1 :7 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[109] $end
-$var wire 1 ;7 A $end
-$var wire 1 <7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 =7 Z $end
-$scope module base $end
-$var wire 1 ;7 A $end
-$var wire 1 <7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 =7 Z $end
-$var wire 1 >7 pwrgood_pp0_out_A $end
-$var wire 1 ?7 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[110] $end
-$var wire 1 @7 A $end
-$var wire 1 A7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 B7 Z $end
-$scope module base $end
-$var wire 1 @7 A $end
-$var wire 1 A7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 B7 Z $end
-$var wire 1 C7 pwrgood_pp0_out_A $end
-$var wire 1 D7 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[111] $end
-$var wire 1 E7 A $end
-$var wire 1 F7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 G7 Z $end
-$scope module base $end
-$var wire 1 E7 A $end
-$var wire 1 F7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 G7 Z $end
-$var wire 1 H7 pwrgood_pp0_out_A $end
-$var wire 1 I7 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[112] $end
-$var wire 1 J7 A $end
-$var wire 1 K7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 L7 Z $end
-$scope module base $end
-$var wire 1 J7 A $end
-$var wire 1 K7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 L7 Z $end
-$var wire 1 M7 pwrgood_pp0_out_A $end
-$var wire 1 N7 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[113] $end
-$var wire 1 O7 A $end
-$var wire 1 P7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 Q7 Z $end
-$scope module base $end
-$var wire 1 O7 A $end
-$var wire 1 P7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 Q7 Z $end
-$var wire 1 R7 pwrgood_pp0_out_A $end
-$var wire 1 S7 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[114] $end
-$var wire 1 T7 A $end
-$var wire 1 U7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 V7 Z $end
-$scope module base $end
-$var wire 1 T7 A $end
-$var wire 1 U7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 V7 Z $end
-$var wire 1 W7 pwrgood_pp0_out_A $end
-$var wire 1 X7 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[115] $end
-$var wire 1 Y7 A $end
-$var wire 1 Z7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 [7 Z $end
-$scope module base $end
-$var wire 1 Y7 A $end
-$var wire 1 Z7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 [7 Z $end
-$var wire 1 \7 pwrgood_pp0_out_A $end
-$var wire 1 ]7 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[116] $end
-$var wire 1 ^7 A $end
-$var wire 1 _7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 `7 Z $end
-$scope module base $end
-$var wire 1 ^7 A $end
-$var wire 1 _7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 `7 Z $end
-$var wire 1 a7 pwrgood_pp0_out_A $end
-$var wire 1 b7 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[117] $end
-$var wire 1 c7 A $end
-$var wire 1 d7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 e7 Z $end
-$scope module base $end
-$var wire 1 c7 A $end
-$var wire 1 d7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 e7 Z $end
-$var wire 1 f7 pwrgood_pp0_out_A $end
-$var wire 1 g7 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[118] $end
-$var wire 1 h7 A $end
-$var wire 1 i7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 j7 Z $end
-$scope module base $end
-$var wire 1 h7 A $end
-$var wire 1 i7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 j7 Z $end
-$var wire 1 k7 pwrgood_pp0_out_A $end
-$var wire 1 l7 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[119] $end
-$var wire 1 m7 A $end
-$var wire 1 n7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 o7 Z $end
-$scope module base $end
-$var wire 1 m7 A $end
-$var wire 1 n7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 o7 Z $end
-$var wire 1 p7 pwrgood_pp0_out_A $end
-$var wire 1 q7 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[120] $end
-$var wire 1 r7 A $end
-$var wire 1 s7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 t7 Z $end
-$scope module base $end
-$var wire 1 r7 A $end
-$var wire 1 s7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 t7 Z $end
-$var wire 1 u7 pwrgood_pp0_out_A $end
-$var wire 1 v7 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[121] $end
-$var wire 1 w7 A $end
-$var wire 1 x7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 y7 Z $end
-$scope module base $end
-$var wire 1 w7 A $end
-$var wire 1 x7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 y7 Z $end
-$var wire 1 z7 pwrgood_pp0_out_A $end
-$var wire 1 {7 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[122] $end
-$var wire 1 |7 A $end
-$var wire 1 }7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ~7 Z $end
-$scope module base $end
-$var wire 1 |7 A $end
-$var wire 1 }7 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ~7 Z $end
-$var wire 1 !8 pwrgood_pp0_out_A $end
-$var wire 1 "8 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[123] $end
-$var wire 1 #8 A $end
-$var wire 1 $8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 %8 Z $end
-$scope module base $end
-$var wire 1 #8 A $end
-$var wire 1 $8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 %8 Z $end
-$var wire 1 &8 pwrgood_pp0_out_A $end
-$var wire 1 '8 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[124] $end
-$var wire 1 (8 A $end
-$var wire 1 )8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 *8 Z $end
-$scope module base $end
-$var wire 1 (8 A $end
-$var wire 1 )8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 *8 Z $end
-$var wire 1 +8 pwrgood_pp0_out_A $end
-$var wire 1 ,8 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[125] $end
-$var wire 1 -8 A $end
-$var wire 1 .8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 /8 Z $end
-$scope module base $end
-$var wire 1 -8 A $end
-$var wire 1 .8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 /8 Z $end
-$var wire 1 08 pwrgood_pp0_out_A $end
-$var wire 1 18 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[126] $end
-$var wire 1 28 A $end
-$var wire 1 38 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 48 Z $end
-$scope module base $end
-$var wire 1 28 A $end
-$var wire 1 38 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 48 Z $end
-$var wire 1 58 pwrgood_pp0_out_A $end
-$var wire 1 68 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module la_buf[127] $end
-$var wire 1 78 A $end
-$var wire 1 88 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 98 Z $end
-$scope module base $end
-$var wire 1 78 A $end
-$var wire 1 88 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 98 Z $end
-$var wire 1 :8 pwrgood_pp0_out_A $end
-$var wire 1 ;8 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[0] $end
-$var wire 1 <8 A $end
-$var wire 1 =8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 >8 Z $end
-$scope module base $end
-$var wire 1 <8 A $end
-$var wire 1 =8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 >8 Z $end
-$var wire 1 ?8 pwrgood_pp0_out_A $end
-$var wire 1 @8 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[1] $end
-$var wire 1 A8 A $end
-$var wire 1 B8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 C8 Z $end
-$scope module base $end
-$var wire 1 A8 A $end
-$var wire 1 B8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 C8 Z $end
-$var wire 1 D8 pwrgood_pp0_out_A $end
-$var wire 1 E8 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[2] $end
-$var wire 1 F8 A $end
-$var wire 1 G8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 H8 Z $end
-$scope module base $end
-$var wire 1 F8 A $end
-$var wire 1 G8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 H8 Z $end
-$var wire 1 I8 pwrgood_pp0_out_A $end
-$var wire 1 J8 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[3] $end
-$var wire 1 K8 A $end
-$var wire 1 L8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 M8 Z $end
-$scope module base $end
-$var wire 1 K8 A $end
-$var wire 1 L8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 M8 Z $end
-$var wire 1 N8 pwrgood_pp0_out_A $end
-$var wire 1 O8 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[4] $end
-$var wire 1 P8 A $end
-$var wire 1 Q8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 R8 Z $end
-$scope module base $end
-$var wire 1 P8 A $end
-$var wire 1 Q8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 R8 Z $end
-$var wire 1 S8 pwrgood_pp0_out_A $end
-$var wire 1 T8 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[5] $end
-$var wire 1 U8 A $end
-$var wire 1 V8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 W8 Z $end
-$scope module base $end
-$var wire 1 U8 A $end
-$var wire 1 V8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 W8 Z $end
-$var wire 1 X8 pwrgood_pp0_out_A $end
-$var wire 1 Y8 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[6] $end
-$var wire 1 Z8 A $end
-$var wire 1 [8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 \8 Z $end
-$scope module base $end
-$var wire 1 Z8 A $end
-$var wire 1 [8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 \8 Z $end
-$var wire 1 ]8 pwrgood_pp0_out_A $end
-$var wire 1 ^8 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[7] $end
-$var wire 1 _8 A $end
-$var wire 1 `8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 a8 Z $end
-$scope module base $end
-$var wire 1 _8 A $end
-$var wire 1 `8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 a8 Z $end
-$var wire 1 b8 pwrgood_pp0_out_A $end
-$var wire 1 c8 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[8] $end
-$var wire 1 d8 A $end
-$var wire 1 e8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 f8 Z $end
-$scope module base $end
-$var wire 1 d8 A $end
-$var wire 1 e8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 f8 Z $end
-$var wire 1 g8 pwrgood_pp0_out_A $end
-$var wire 1 h8 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[9] $end
-$var wire 1 i8 A $end
-$var wire 1 j8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 k8 Z $end
-$scope module base $end
-$var wire 1 i8 A $end
-$var wire 1 j8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 k8 Z $end
-$var wire 1 l8 pwrgood_pp0_out_A $end
-$var wire 1 m8 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[10] $end
-$var wire 1 n8 A $end
-$var wire 1 o8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 p8 Z $end
-$scope module base $end
-$var wire 1 n8 A $end
-$var wire 1 o8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 p8 Z $end
-$var wire 1 q8 pwrgood_pp0_out_A $end
-$var wire 1 r8 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[11] $end
-$var wire 1 s8 A $end
-$var wire 1 t8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 u8 Z $end
-$scope module base $end
-$var wire 1 s8 A $end
-$var wire 1 t8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 u8 Z $end
-$var wire 1 v8 pwrgood_pp0_out_A $end
-$var wire 1 w8 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[12] $end
-$var wire 1 x8 A $end
-$var wire 1 y8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 z8 Z $end
-$scope module base $end
-$var wire 1 x8 A $end
-$var wire 1 y8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 z8 Z $end
-$var wire 1 {8 pwrgood_pp0_out_A $end
-$var wire 1 |8 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[13] $end
-$var wire 1 }8 A $end
-$var wire 1 ~8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 !9 Z $end
-$scope module base $end
-$var wire 1 }8 A $end
-$var wire 1 ~8 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 !9 Z $end
-$var wire 1 "9 pwrgood_pp0_out_A $end
-$var wire 1 #9 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[14] $end
-$var wire 1 $9 A $end
-$var wire 1 %9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 &9 Z $end
-$scope module base $end
-$var wire 1 $9 A $end
-$var wire 1 %9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 &9 Z $end
-$var wire 1 '9 pwrgood_pp0_out_A $end
-$var wire 1 (9 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[15] $end
-$var wire 1 )9 A $end
-$var wire 1 *9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 +9 Z $end
-$scope module base $end
-$var wire 1 )9 A $end
-$var wire 1 *9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 +9 Z $end
-$var wire 1 ,9 pwrgood_pp0_out_A $end
-$var wire 1 -9 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[16] $end
-$var wire 1 .9 A $end
-$var wire 1 /9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 09 Z $end
-$scope module base $end
-$var wire 1 .9 A $end
-$var wire 1 /9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 09 Z $end
-$var wire 1 19 pwrgood_pp0_out_A $end
-$var wire 1 29 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[17] $end
-$var wire 1 39 A $end
-$var wire 1 49 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 59 Z $end
-$scope module base $end
-$var wire 1 39 A $end
-$var wire 1 49 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 59 Z $end
-$var wire 1 69 pwrgood_pp0_out_A $end
-$var wire 1 79 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[18] $end
-$var wire 1 89 A $end
-$var wire 1 99 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 :9 Z $end
-$scope module base $end
-$var wire 1 89 A $end
-$var wire 1 99 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 :9 Z $end
-$var wire 1 ;9 pwrgood_pp0_out_A $end
-$var wire 1 <9 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[19] $end
-$var wire 1 =9 A $end
-$var wire 1 >9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ?9 Z $end
-$scope module base $end
-$var wire 1 =9 A $end
-$var wire 1 >9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ?9 Z $end
-$var wire 1 @9 pwrgood_pp0_out_A $end
-$var wire 1 A9 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[20] $end
-$var wire 1 B9 A $end
-$var wire 1 C9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 D9 Z $end
-$scope module base $end
-$var wire 1 B9 A $end
-$var wire 1 C9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 D9 Z $end
-$var wire 1 E9 pwrgood_pp0_out_A $end
-$var wire 1 F9 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[21] $end
-$var wire 1 G9 A $end
-$var wire 1 H9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 I9 Z $end
-$scope module base $end
-$var wire 1 G9 A $end
-$var wire 1 H9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 I9 Z $end
-$var wire 1 J9 pwrgood_pp0_out_A $end
-$var wire 1 K9 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[22] $end
-$var wire 1 L9 A $end
-$var wire 1 M9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 N9 Z $end
-$scope module base $end
-$var wire 1 L9 A $end
-$var wire 1 M9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 N9 Z $end
-$var wire 1 O9 pwrgood_pp0_out_A $end
-$var wire 1 P9 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[23] $end
-$var wire 1 Q9 A $end
-$var wire 1 R9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 S9 Z $end
-$scope module base $end
-$var wire 1 Q9 A $end
-$var wire 1 R9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 S9 Z $end
-$var wire 1 T9 pwrgood_pp0_out_A $end
-$var wire 1 U9 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[24] $end
-$var wire 1 V9 A $end
-$var wire 1 W9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 X9 Z $end
-$scope module base $end
-$var wire 1 V9 A $end
-$var wire 1 W9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 X9 Z $end
-$var wire 1 Y9 pwrgood_pp0_out_A $end
-$var wire 1 Z9 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[25] $end
-$var wire 1 [9 A $end
-$var wire 1 \9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ]9 Z $end
-$scope module base $end
-$var wire 1 [9 A $end
-$var wire 1 \9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ]9 Z $end
-$var wire 1 ^9 pwrgood_pp0_out_A $end
-$var wire 1 _9 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[26] $end
-$var wire 1 `9 A $end
-$var wire 1 a9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 b9 Z $end
-$scope module base $end
-$var wire 1 `9 A $end
-$var wire 1 a9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 b9 Z $end
-$var wire 1 c9 pwrgood_pp0_out_A $end
-$var wire 1 d9 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[27] $end
-$var wire 1 e9 A $end
-$var wire 1 f9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 g9 Z $end
-$scope module base $end
-$var wire 1 e9 A $end
-$var wire 1 f9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 g9 Z $end
-$var wire 1 h9 pwrgood_pp0_out_A $end
-$var wire 1 i9 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[28] $end
-$var wire 1 j9 A $end
-$var wire 1 k9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 l9 Z $end
-$scope module base $end
-$var wire 1 j9 A $end
-$var wire 1 k9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 l9 Z $end
-$var wire 1 m9 pwrgood_pp0_out_A $end
-$var wire 1 n9 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[29] $end
-$var wire 1 o9 A $end
-$var wire 1 p9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 q9 Z $end
-$scope module base $end
-$var wire 1 o9 A $end
-$var wire 1 p9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 q9 Z $end
-$var wire 1 r9 pwrgood_pp0_out_A $end
-$var wire 1 s9 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[30] $end
-$var wire 1 t9 A $end
-$var wire 1 u9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 v9 Z $end
-$scope module base $end
-$var wire 1 t9 A $end
-$var wire 1 u9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 v9 Z $end
-$var wire 1 w9 pwrgood_pp0_out_A $end
-$var wire 1 x9 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_adr_buf[31] $end
-$var wire 1 y9 A $end
-$var wire 1 z9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 {9 Z $end
-$scope module base $end
-$var wire 1 y9 A $end
-$var wire 1 z9 TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 {9 Z $end
-$var wire 1 |9 pwrgood_pp0_out_A $end
-$var wire 1 }9 pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_clk2_buf $end
-$var wire 1 ~9 A $end
-$var wire 1 !: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 $" Z $end
-$scope module base $end
-$var wire 1 ~9 A $end
-$var wire 1 !: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 $" Z $end
-$var wire 1 ": pwrgood_pp0_out_A $end
-$var wire 1 #: pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_clk_buf $end
-$var wire 1 $: A $end
-$var wire 1 %: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 %" Z $end
-$scope module base $end
-$var wire 1 $: A $end
-$var wire 1 %: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 %" Z $end
-$var wire 1 &: pwrgood_pp0_out_A $end
-$var wire 1 ': pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_cyc_buf $end
-$var wire 1 (: A $end
-$var wire 1 ): TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 #" Z $end
-$scope module base $end
-$var wire 1 (: A $end
-$var wire 1 ): TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 #" Z $end
-$var wire 1 *: pwrgood_pp0_out_A $end
-$var wire 1 +: pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[0] $end
-$var wire 1 ,: A $end
-$var wire 1 -: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 .: Z $end
-$scope module base $end
-$var wire 1 ,: A $end
-$var wire 1 -: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 .: Z $end
-$var wire 1 /: pwrgood_pp0_out_A $end
-$var wire 1 0: pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[1] $end
-$var wire 1 1: A $end
-$var wire 1 2: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 3: Z $end
-$scope module base $end
-$var wire 1 1: A $end
-$var wire 1 2: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 3: Z $end
-$var wire 1 4: pwrgood_pp0_out_A $end
-$var wire 1 5: pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[2] $end
-$var wire 1 6: A $end
-$var wire 1 7: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 8: Z $end
-$scope module base $end
-$var wire 1 6: A $end
-$var wire 1 7: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 8: Z $end
-$var wire 1 9: pwrgood_pp0_out_A $end
-$var wire 1 :: pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[3] $end
-$var wire 1 ;: A $end
-$var wire 1 <: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 =: Z $end
-$scope module base $end
-$var wire 1 ;: A $end
-$var wire 1 <: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 =: Z $end
-$var wire 1 >: pwrgood_pp0_out_A $end
-$var wire 1 ?: pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[4] $end
-$var wire 1 @: A $end
-$var wire 1 A: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 B: Z $end
-$scope module base $end
-$var wire 1 @: A $end
-$var wire 1 A: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 B: Z $end
-$var wire 1 C: pwrgood_pp0_out_A $end
-$var wire 1 D: pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[5] $end
-$var wire 1 E: A $end
-$var wire 1 F: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 G: Z $end
-$scope module base $end
-$var wire 1 E: A $end
-$var wire 1 F: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 G: Z $end
-$var wire 1 H: pwrgood_pp0_out_A $end
-$var wire 1 I: pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[6] $end
-$var wire 1 J: A $end
-$var wire 1 K: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 L: Z $end
-$scope module base $end
-$var wire 1 J: A $end
-$var wire 1 K: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 L: Z $end
-$var wire 1 M: pwrgood_pp0_out_A $end
-$var wire 1 N: pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[7] $end
-$var wire 1 O: A $end
-$var wire 1 P: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 Q: Z $end
-$scope module base $end
-$var wire 1 O: A $end
-$var wire 1 P: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 Q: Z $end
-$var wire 1 R: pwrgood_pp0_out_A $end
-$var wire 1 S: pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[8] $end
-$var wire 1 T: A $end
-$var wire 1 U: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 V: Z $end
-$scope module base $end
-$var wire 1 T: A $end
-$var wire 1 U: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 V: Z $end
-$var wire 1 W: pwrgood_pp0_out_A $end
-$var wire 1 X: pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[9] $end
-$var wire 1 Y: A $end
-$var wire 1 Z: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 [: Z $end
-$scope module base $end
-$var wire 1 Y: A $end
-$var wire 1 Z: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 [: Z $end
-$var wire 1 \: pwrgood_pp0_out_A $end
-$var wire 1 ]: pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[10] $end
-$var wire 1 ^: A $end
-$var wire 1 _: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 `: Z $end
-$scope module base $end
-$var wire 1 ^: A $end
-$var wire 1 _: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 `: Z $end
-$var wire 1 a: pwrgood_pp0_out_A $end
-$var wire 1 b: pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[11] $end
-$var wire 1 c: A $end
-$var wire 1 d: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 e: Z $end
-$scope module base $end
-$var wire 1 c: A $end
-$var wire 1 d: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 e: Z $end
-$var wire 1 f: pwrgood_pp0_out_A $end
-$var wire 1 g: pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[12] $end
-$var wire 1 h: A $end
-$var wire 1 i: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 j: Z $end
-$scope module base $end
-$var wire 1 h: A $end
-$var wire 1 i: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 j: Z $end
-$var wire 1 k: pwrgood_pp0_out_A $end
-$var wire 1 l: pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[13] $end
-$var wire 1 m: A $end
-$var wire 1 n: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 o: Z $end
-$scope module base $end
-$var wire 1 m: A $end
-$var wire 1 n: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 o: Z $end
-$var wire 1 p: pwrgood_pp0_out_A $end
-$var wire 1 q: pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[14] $end
-$var wire 1 r: A $end
-$var wire 1 s: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 t: Z $end
-$scope module base $end
-$var wire 1 r: A $end
-$var wire 1 s: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 t: Z $end
-$var wire 1 u: pwrgood_pp0_out_A $end
-$var wire 1 v: pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[15] $end
-$var wire 1 w: A $end
-$var wire 1 x: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 y: Z $end
-$scope module base $end
-$var wire 1 w: A $end
-$var wire 1 x: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 y: Z $end
-$var wire 1 z: pwrgood_pp0_out_A $end
-$var wire 1 {: pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[16] $end
-$var wire 1 |: A $end
-$var wire 1 }: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ~: Z $end
-$scope module base $end
-$var wire 1 |: A $end
-$var wire 1 }: TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ~: Z $end
-$var wire 1 !; pwrgood_pp0_out_A $end
-$var wire 1 "; pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[17] $end
-$var wire 1 #; A $end
-$var wire 1 $; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 %; Z $end
-$scope module base $end
-$var wire 1 #; A $end
-$var wire 1 $; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 %; Z $end
-$var wire 1 &; pwrgood_pp0_out_A $end
-$var wire 1 '; pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[18] $end
-$var wire 1 (; A $end
-$var wire 1 ); TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 *; Z $end
-$scope module base $end
-$var wire 1 (; A $end
-$var wire 1 ); TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 *; Z $end
-$var wire 1 +; pwrgood_pp0_out_A $end
-$var wire 1 ,; pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[19] $end
-$var wire 1 -; A $end
-$var wire 1 .; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 /; Z $end
-$scope module base $end
-$var wire 1 -; A $end
-$var wire 1 .; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 /; Z $end
-$var wire 1 0; pwrgood_pp0_out_A $end
-$var wire 1 1; pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[20] $end
-$var wire 1 2; A $end
-$var wire 1 3; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 4; Z $end
-$scope module base $end
-$var wire 1 2; A $end
-$var wire 1 3; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 4; Z $end
-$var wire 1 5; pwrgood_pp0_out_A $end
-$var wire 1 6; pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[21] $end
-$var wire 1 7; A $end
-$var wire 1 8; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 9; Z $end
-$scope module base $end
-$var wire 1 7; A $end
-$var wire 1 8; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 9; Z $end
-$var wire 1 :; pwrgood_pp0_out_A $end
-$var wire 1 ;; pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[22] $end
-$var wire 1 <; A $end
-$var wire 1 =; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 >; Z $end
-$scope module base $end
-$var wire 1 <; A $end
-$var wire 1 =; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 >; Z $end
-$var wire 1 ?; pwrgood_pp0_out_A $end
-$var wire 1 @; pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[23] $end
-$var wire 1 A; A $end
-$var wire 1 B; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 C; Z $end
-$scope module base $end
-$var wire 1 A; A $end
-$var wire 1 B; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 C; Z $end
-$var wire 1 D; pwrgood_pp0_out_A $end
-$var wire 1 E; pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[24] $end
-$var wire 1 F; A $end
-$var wire 1 G; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 H; Z $end
-$scope module base $end
-$var wire 1 F; A $end
-$var wire 1 G; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 H; Z $end
-$var wire 1 I; pwrgood_pp0_out_A $end
-$var wire 1 J; pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[25] $end
-$var wire 1 K; A $end
-$var wire 1 L; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 M; Z $end
-$scope module base $end
-$var wire 1 K; A $end
-$var wire 1 L; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 M; Z $end
-$var wire 1 N; pwrgood_pp0_out_A $end
-$var wire 1 O; pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[26] $end
-$var wire 1 P; A $end
-$var wire 1 Q; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 R; Z $end
-$scope module base $end
-$var wire 1 P; A $end
-$var wire 1 Q; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 R; Z $end
-$var wire 1 S; pwrgood_pp0_out_A $end
-$var wire 1 T; pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[27] $end
-$var wire 1 U; A $end
-$var wire 1 V; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 W; Z $end
-$scope module base $end
-$var wire 1 U; A $end
-$var wire 1 V; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 W; Z $end
-$var wire 1 X; pwrgood_pp0_out_A $end
-$var wire 1 Y; pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[28] $end
-$var wire 1 Z; A $end
-$var wire 1 [; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 \; Z $end
-$scope module base $end
-$var wire 1 Z; A $end
-$var wire 1 [; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 \; Z $end
-$var wire 1 ]; pwrgood_pp0_out_A $end
-$var wire 1 ^; pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[29] $end
-$var wire 1 _; A $end
-$var wire 1 `; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 a; Z $end
-$scope module base $end
-$var wire 1 _; A $end
-$var wire 1 `; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 a; Z $end
-$var wire 1 b; pwrgood_pp0_out_A $end
-$var wire 1 c; pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[30] $end
-$var wire 1 d; A $end
-$var wire 1 e; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 f; Z $end
-$scope module base $end
-$var wire 1 d; A $end
-$var wire 1 e; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 f; Z $end
-$var wire 1 g; pwrgood_pp0_out_A $end
-$var wire 1 h; pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_dat_buf[31] $end
-$var wire 1 i; A $end
-$var wire 1 j; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 k; Z $end
-$scope module base $end
-$var wire 1 i; A $end
-$var wire 1 j; TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 k; Z $end
-$var wire 1 l; pwrgood_pp0_out_A $end
-$var wire 1 m; pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[0] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 n; LO $end
-$var wire 1 o; HI $end
-$scope module base $end
-$var wire 1 o; HI $end
-$var wire 1 n; LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 p; pulldown0_out_LO $end
-$var wire 1 q; pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[1] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 r; LO $end
-$var wire 1 s; HI $end
-$scope module base $end
-$var wire 1 s; HI $end
-$var wire 1 r; LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 t; pulldown0_out_LO $end
-$var wire 1 u; pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[2] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 v; LO $end
-$var wire 1 w; HI $end
-$scope module base $end
-$var wire 1 w; HI $end
-$var wire 1 v; LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 x; pulldown0_out_LO $end
-$var wire 1 y; pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[3] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 z; LO $end
-$var wire 1 {; HI $end
-$scope module base $end
-$var wire 1 {; HI $end
-$var wire 1 z; LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 |; pulldown0_out_LO $end
-$var wire 1 }; pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[4] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ~; LO $end
-$var wire 1 !< HI $end
-$scope module base $end
-$var wire 1 !< HI $end
-$var wire 1 ~; LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 "< pulldown0_out_LO $end
-$var wire 1 #< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[5] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 $< LO $end
-$var wire 1 %< HI $end
-$scope module base $end
-$var wire 1 %< HI $end
-$var wire 1 $< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 &< pulldown0_out_LO $end
-$var wire 1 '< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[6] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 (< LO $end
-$var wire 1 )< HI $end
-$scope module base $end
-$var wire 1 )< HI $end
-$var wire 1 (< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 *< pulldown0_out_LO $end
-$var wire 1 +< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[7] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ,< LO $end
-$var wire 1 -< HI $end
-$scope module base $end
-$var wire 1 -< HI $end
-$var wire 1 ,< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 .< pulldown0_out_LO $end
-$var wire 1 /< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[8] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 0< LO $end
-$var wire 1 1< HI $end
-$scope module base $end
-$var wire 1 1< HI $end
-$var wire 1 0< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 2< pulldown0_out_LO $end
-$var wire 1 3< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[9] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 4< LO $end
-$var wire 1 5< HI $end
-$scope module base $end
-$var wire 1 5< HI $end
-$var wire 1 4< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 6< pulldown0_out_LO $end
-$var wire 1 7< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[10] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 8< LO $end
-$var wire 1 9< HI $end
-$scope module base $end
-$var wire 1 9< HI $end
-$var wire 1 8< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 :< pulldown0_out_LO $end
-$var wire 1 ;< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[11] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 << LO $end
-$var wire 1 =< HI $end
-$scope module base $end
-$var wire 1 =< HI $end
-$var wire 1 << LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 >< pulldown0_out_LO $end
-$var wire 1 ?< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[12] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 @< LO $end
-$var wire 1 A< HI $end
-$scope module base $end
-$var wire 1 A< HI $end
-$var wire 1 @< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 B< pulldown0_out_LO $end
-$var wire 1 C< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[13] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 D< LO $end
-$var wire 1 E< HI $end
-$scope module base $end
-$var wire 1 E< HI $end
-$var wire 1 D< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 F< pulldown0_out_LO $end
-$var wire 1 G< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[14] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 H< LO $end
-$var wire 1 I< HI $end
-$scope module base $end
-$var wire 1 I< HI $end
-$var wire 1 H< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 J< pulldown0_out_LO $end
-$var wire 1 K< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[15] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 L< LO $end
-$var wire 1 M< HI $end
-$scope module base $end
-$var wire 1 M< HI $end
-$var wire 1 L< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 N< pulldown0_out_LO $end
-$var wire 1 O< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[16] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 P< LO $end
-$var wire 1 Q< HI $end
-$scope module base $end
-$var wire 1 Q< HI $end
-$var wire 1 P< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 R< pulldown0_out_LO $end
-$var wire 1 S< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[17] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 T< LO $end
-$var wire 1 U< HI $end
-$scope module base $end
-$var wire 1 U< HI $end
-$var wire 1 T< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 V< pulldown0_out_LO $end
-$var wire 1 W< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[18] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 X< LO $end
-$var wire 1 Y< HI $end
-$scope module base $end
-$var wire 1 Y< HI $end
-$var wire 1 X< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 Z< pulldown0_out_LO $end
-$var wire 1 [< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[19] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 \< LO $end
-$var wire 1 ]< HI $end
-$scope module base $end
-$var wire 1 ]< HI $end
-$var wire 1 \< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ^< pulldown0_out_LO $end
-$var wire 1 _< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[20] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 `< LO $end
-$var wire 1 a< HI $end
-$scope module base $end
-$var wire 1 a< HI $end
-$var wire 1 `< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 b< pulldown0_out_LO $end
-$var wire 1 c< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[21] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 d< LO $end
-$var wire 1 e< HI $end
-$scope module base $end
-$var wire 1 e< HI $end
-$var wire 1 d< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 f< pulldown0_out_LO $end
-$var wire 1 g< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[22] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 h< LO $end
-$var wire 1 i< HI $end
-$scope module base $end
-$var wire 1 i< HI $end
-$var wire 1 h< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 j< pulldown0_out_LO $end
-$var wire 1 k< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[23] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 l< LO $end
-$var wire 1 m< HI $end
-$scope module base $end
-$var wire 1 m< HI $end
-$var wire 1 l< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 n< pulldown0_out_LO $end
-$var wire 1 o< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[24] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 p< LO $end
-$var wire 1 q< HI $end
-$scope module base $end
-$var wire 1 q< HI $end
-$var wire 1 p< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 r< pulldown0_out_LO $end
-$var wire 1 s< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[25] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 t< LO $end
-$var wire 1 u< HI $end
-$scope module base $end
-$var wire 1 u< HI $end
-$var wire 1 t< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 v< pulldown0_out_LO $end
-$var wire 1 w< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[26] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 x< LO $end
-$var wire 1 y< HI $end
-$scope module base $end
-$var wire 1 y< HI $end
-$var wire 1 x< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 z< pulldown0_out_LO $end
-$var wire 1 {< pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[27] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 |< LO $end
-$var wire 1 }< HI $end
-$scope module base $end
-$var wire 1 }< HI $end
-$var wire 1 |< LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ~< pulldown0_out_LO $end
-$var wire 1 != pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[28] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 "= LO $end
-$var wire 1 #= HI $end
-$scope module base $end
-$var wire 1 #= HI $end
-$var wire 1 "= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 $= pulldown0_out_LO $end
-$var wire 1 %= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[29] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 &= LO $end
-$var wire 1 '= HI $end
-$scope module base $end
-$var wire 1 '= HI $end
-$var wire 1 &= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 (= pulldown0_out_LO $end
-$var wire 1 )= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[30] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 *= LO $end
-$var wire 1 += HI $end
-$scope module base $end
-$var wire 1 += HI $end
-$var wire 1 *= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ,= pulldown0_out_LO $end
-$var wire 1 -= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[31] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 .= LO $end
-$var wire 1 /= HI $end
-$scope module base $end
-$var wire 1 /= HI $end
-$var wire 1 .= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 0= pulldown0_out_LO $end
-$var wire 1 1= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[32] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 2= LO $end
-$var wire 1 3= HI $end
-$scope module base $end
-$var wire 1 3= HI $end
-$var wire 1 2= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 4= pulldown0_out_LO $end
-$var wire 1 5= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[33] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 6= LO $end
-$var wire 1 7= HI $end
-$scope module base $end
-$var wire 1 7= HI $end
-$var wire 1 6= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 8= pulldown0_out_LO $end
-$var wire 1 9= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[34] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 := LO $end
-$var wire 1 ;= HI $end
-$scope module base $end
-$var wire 1 ;= HI $end
-$var wire 1 := LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 <= pulldown0_out_LO $end
-$var wire 1 == pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[35] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 >= LO $end
-$var wire 1 ?= HI $end
-$scope module base $end
-$var wire 1 ?= HI $end
-$var wire 1 >= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 @= pulldown0_out_LO $end
-$var wire 1 A= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[36] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 B= LO $end
-$var wire 1 C= HI $end
-$scope module base $end
-$var wire 1 C= HI $end
-$var wire 1 B= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 D= pulldown0_out_LO $end
-$var wire 1 E= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[37] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 F= LO $end
-$var wire 1 G= HI $end
-$scope module base $end
-$var wire 1 G= HI $end
-$var wire 1 F= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 H= pulldown0_out_LO $end
-$var wire 1 I= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[38] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 J= LO $end
-$var wire 1 K= HI $end
-$scope module base $end
-$var wire 1 K= HI $end
-$var wire 1 J= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 L= pulldown0_out_LO $end
-$var wire 1 M= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[39] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 N= LO $end
-$var wire 1 O= HI $end
-$scope module base $end
-$var wire 1 O= HI $end
-$var wire 1 N= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 P= pulldown0_out_LO $end
-$var wire 1 Q= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[40] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 R= LO $end
-$var wire 1 S= HI $end
-$scope module base $end
-$var wire 1 S= HI $end
-$var wire 1 R= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 T= pulldown0_out_LO $end
-$var wire 1 U= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[41] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 V= LO $end
-$var wire 1 W= HI $end
-$scope module base $end
-$var wire 1 W= HI $end
-$var wire 1 V= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 X= pulldown0_out_LO $end
-$var wire 1 Y= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[42] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 Z= LO $end
-$var wire 1 [= HI $end
-$scope module base $end
-$var wire 1 [= HI $end
-$var wire 1 Z= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 \= pulldown0_out_LO $end
-$var wire 1 ]= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[43] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ^= LO $end
-$var wire 1 _= HI $end
-$scope module base $end
-$var wire 1 _= HI $end
-$var wire 1 ^= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 `= pulldown0_out_LO $end
-$var wire 1 a= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[44] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 b= LO $end
-$var wire 1 c= HI $end
-$scope module base $end
-$var wire 1 c= HI $end
-$var wire 1 b= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 d= pulldown0_out_LO $end
-$var wire 1 e= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[45] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 f= LO $end
-$var wire 1 g= HI $end
-$scope module base $end
-$var wire 1 g= HI $end
-$var wire 1 f= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 h= pulldown0_out_LO $end
-$var wire 1 i= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[46] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 j= LO $end
-$var wire 1 k= HI $end
-$scope module base $end
-$var wire 1 k= HI $end
-$var wire 1 j= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 l= pulldown0_out_LO $end
-$var wire 1 m= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[47] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 n= LO $end
-$var wire 1 o= HI $end
-$scope module base $end
-$var wire 1 o= HI $end
-$var wire 1 n= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 p= pulldown0_out_LO $end
-$var wire 1 q= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[48] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 r= LO $end
-$var wire 1 s= HI $end
-$scope module base $end
-$var wire 1 s= HI $end
-$var wire 1 r= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 t= pulldown0_out_LO $end
-$var wire 1 u= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[49] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 v= LO $end
-$var wire 1 w= HI $end
-$scope module base $end
-$var wire 1 w= HI $end
-$var wire 1 v= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 x= pulldown0_out_LO $end
-$var wire 1 y= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[50] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 z= LO $end
-$var wire 1 {= HI $end
-$scope module base $end
-$var wire 1 {= HI $end
-$var wire 1 z= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 |= pulldown0_out_LO $end
-$var wire 1 }= pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[51] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ~= LO $end
-$var wire 1 !> HI $end
-$scope module base $end
-$var wire 1 !> HI $end
-$var wire 1 ~= LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 "> pulldown0_out_LO $end
-$var wire 1 #> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[52] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 $> LO $end
-$var wire 1 %> HI $end
-$scope module base $end
-$var wire 1 %> HI $end
-$var wire 1 $> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 &> pulldown0_out_LO $end
-$var wire 1 '> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[53] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 (> LO $end
-$var wire 1 )> HI $end
-$scope module base $end
-$var wire 1 )> HI $end
-$var wire 1 (> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 *> pulldown0_out_LO $end
-$var wire 1 +> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[54] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ,> LO $end
-$var wire 1 -> HI $end
-$scope module base $end
-$var wire 1 -> HI $end
-$var wire 1 ,> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 .> pulldown0_out_LO $end
-$var wire 1 /> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[55] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 0> LO $end
-$var wire 1 1> HI $end
-$scope module base $end
-$var wire 1 1> HI $end
-$var wire 1 0> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 2> pulldown0_out_LO $end
-$var wire 1 3> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[56] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 4> LO $end
-$var wire 1 5> HI $end
-$scope module base $end
-$var wire 1 5> HI $end
-$var wire 1 4> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 6> pulldown0_out_LO $end
-$var wire 1 7> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[57] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 8> LO $end
-$var wire 1 9> HI $end
-$scope module base $end
-$var wire 1 9> HI $end
-$var wire 1 8> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 :> pulldown0_out_LO $end
-$var wire 1 ;> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[58] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 <> LO $end
-$var wire 1 => HI $end
-$scope module base $end
-$var wire 1 => HI $end
-$var wire 1 <> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 >> pulldown0_out_LO $end
-$var wire 1 ?> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[59] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 @> LO $end
-$var wire 1 A> HI $end
-$scope module base $end
-$var wire 1 A> HI $end
-$var wire 1 @> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 B> pulldown0_out_LO $end
-$var wire 1 C> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[60] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 D> LO $end
-$var wire 1 E> HI $end
-$scope module base $end
-$var wire 1 E> HI $end
-$var wire 1 D> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 F> pulldown0_out_LO $end
-$var wire 1 G> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[61] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 H> LO $end
-$var wire 1 I> HI $end
-$scope module base $end
-$var wire 1 I> HI $end
-$var wire 1 H> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 J> pulldown0_out_LO $end
-$var wire 1 K> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[62] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 L> LO $end
-$var wire 1 M> HI $end
-$scope module base $end
-$var wire 1 M> HI $end
-$var wire 1 L> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 N> pulldown0_out_LO $end
-$var wire 1 O> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[63] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 P> LO $end
-$var wire 1 Q> HI $end
-$scope module base $end
-$var wire 1 Q> HI $end
-$var wire 1 P> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 R> pulldown0_out_LO $end
-$var wire 1 S> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[64] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 T> LO $end
-$var wire 1 U> HI $end
-$scope module base $end
-$var wire 1 U> HI $end
-$var wire 1 T> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 V> pulldown0_out_LO $end
-$var wire 1 W> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[65] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 X> LO $end
-$var wire 1 Y> HI $end
-$scope module base $end
-$var wire 1 Y> HI $end
-$var wire 1 X> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 Z> pulldown0_out_LO $end
-$var wire 1 [> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[66] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 \> LO $end
-$var wire 1 ]> HI $end
-$scope module base $end
-$var wire 1 ]> HI $end
-$var wire 1 \> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 ^> pulldown0_out_LO $end
-$var wire 1 _> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[67] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 `> LO $end
-$var wire 1 a> HI $end
-$scope module base $end
-$var wire 1 a> HI $end
-$var wire 1 `> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 b> pulldown0_out_LO $end
-$var wire 1 c> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[68] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 d> LO $end
-$var wire 1 e> HI $end
-$scope module base $end
-$var wire 1 e> HI $end
-$var wire 1 d> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 f> pulldown0_out_LO $end
-$var wire 1 g> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[69] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 h> LO $end
-$var wire 1 i> HI $end
-$scope module base $end
-$var wire 1 i> HI $end
-$var wire 1 h> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 j> pulldown0_out_LO $end
-$var wire 1 k> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[70] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 l> LO $end
-$var wire 1 m> HI $end
-$scope module base $end
-$var wire 1 m> HI $end
-$var wire 1 l> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 n> pulldown0_out_LO $end
-$var wire 1 o> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[71] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 p> LO $end
-$var wire 1 q> HI $end
-$scope module base $end
-$var wire 1 q> HI $end
-$var wire 1 p> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 r> pulldown0_out_LO $end
-$var wire 1 s> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[72] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 t> LO $end
-$var wire 1 u> HI $end
-$scope module base $end
-$var wire 1 u> HI $end
-$var wire 1 t> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 v> pulldown0_out_LO $end
-$var wire 1 w> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_logic_high[73] $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 x> LO $end
-$var wire 1 y> HI $end
-$scope module base $end
-$var wire 1 y> HI $end
-$var wire 1 x> LO $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 z> pulldown0_out_LO $end
-$var wire 1 {> pullup0_out_HI $end
-$upscope $end
-$upscope $end
-$scope module mprj_rstn_buf $end
-$var wire 1 |> A $end
-$var wire 1 }> TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 m Z $end
-$scope module base $end
-$var wire 1 |> A $end
-$var wire 1 }> TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 m Z $end
-$var wire 1 ~> pwrgood_pp0_out_A $end
-$var wire 1 !? pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_sel_buf[0] $end
-$var wire 1 "? A $end
-$var wire 1 #? TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 $? Z $end
-$scope module base $end
-$var wire 1 "? A $end
-$var wire 1 #? TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 $? Z $end
-$var wire 1 %? pwrgood_pp0_out_A $end
-$var wire 1 &? pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_sel_buf[1] $end
-$var wire 1 '? A $end
-$var wire 1 (? TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 )? Z $end
-$scope module base $end
-$var wire 1 '? A $end
-$var wire 1 (? TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 )? Z $end
-$var wire 1 *? pwrgood_pp0_out_A $end
-$var wire 1 +? pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_sel_buf[2] $end
-$var wire 1 ,? A $end
-$var wire 1 -? TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 .? Z $end
-$scope module base $end
-$var wire 1 ,? A $end
-$var wire 1 -? TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 .? Z $end
-$var wire 1 /? pwrgood_pp0_out_A $end
-$var wire 1 0? pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_sel_buf[3] $end
-$var wire 1 1? A $end
-$var wire 1 2? TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 3? Z $end
-$scope module base $end
-$var wire 1 1? A $end
-$var wire 1 2? TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 3? Z $end
-$var wire 1 4? pwrgood_pp0_out_A $end
-$var wire 1 5? pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_stb_buf $end
-$var wire 1 6? A $end
-$var wire 1 7? TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 j Z $end
-$scope module base $end
-$var wire 1 6? A $end
-$var wire 1 7? TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 j Z $end
-$var wire 1 8? pwrgood_pp0_out_A $end
-$var wire 1 9? pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$scope module mprj_we_buf $end
-$var wire 1 :? A $end
-$var wire 1 ;? TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 i Z $end
-$scope module base $end
-$var wire 1 :? A $end
-$var wire 1 ;? TE $end
-$var wire 1 ! VGND $end
-$var wire 1 ! VNB $end
-$var wire 1 + VPB $end
-$var wire 1 + VPWR $end
-$var wire 1 i Z $end
-$var wire 1 <? pwrgood_pp0_out_A $end
-$var wire 1 =? pwrgood_pp1_out_TE $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module mprj $end
-$var wire 37 >? io_in [36:0] $end
-$var wire 128 ?? la_data_in [127:0] $end
-$var wire 32 @? la_write [31:0] $end
-$var wire 1 A? valid $end
-$var wire 1 + vccd1 $end
-$var wire 1 + vccd2 $end
-$var wire 1 * vdda1 $end
-$var wire 1 * vdda2 $end
-$var wire 1 ! vssa1 $end
-$var wire 1 ! vssa2 $end
-$var wire 1 ! vssd1 $end
-$var wire 1 ! vssd2 $end
-$var wire 1 %" wb_clk_i $end
-$var wire 1 B? wb_rst_i $end
-$var wire 1 P wbs_ack_o $end
-$var wire 32 C? wbs_adr_i [31:0] $end
-$var wire 1 #" wbs_cyc_i $end
-$var wire 32 D? wbs_dat_i [31:0] $end
-$var wire 32 E? wbs_dat_o [31:0] $end
-$var wire 4 F? wbs_sel_i [3:0] $end
-$var wire 1 j wbs_stb_i $end
-$var wire 1 i wbs_we_i $end
-$var wire 32 G? wdata [31:0] $end
-$var wire 4 H? wstrb [3:0] $end
-$var wire 1 I? wbs_ack_i $end
-$var wire 1 J? rst $end
-$var wire 32 K? rdata [31:0] $end
-$var wire 128 L? la_oen [127:0] $end
-$var wire 128 M? la_data_out [127:0] $end
-$var wire 37 N? io_out [36:0] $end
-$var wire 37 O? io_oeb [36:0] $end
-$var wire 32 P? count [31:0] $end
-$var wire 1 Q? clk $end
-$scope module counter $end
-$var wire 1 Q? clk $end
-$var wire 32 R? la_input [31:0] $end
-$var wire 32 S? la_write [31:0] $end
-$var wire 1 J? reset $end
-$var wire 1 A? valid $end
-$var wire 32 T? wdata [31:0] $end
-$var wire 4 U? wstrb [3:0] $end
-$var reg 32 V? count [31:0] $end
-$var reg 32 W? rdata [31:0] $end
-$var reg 1 I? ready $end
-$scope begin genblk1[0] $end
-$upscope $end
-$scope begin genblk1[1] $end
-$upscope $end
-$scope begin genblk1[2] $end
-$upscope $end
-$scope begin genblk1[3] $end
-$upscope $end
-$scope begin genblk1[4] $end
-$upscope $end
-$scope begin genblk1[5] $end
-$upscope $end
-$scope begin genblk1[6] $end
-$upscope $end
-$scope begin genblk1[7] $end
-$upscope $end
-$scope begin genblk1[8] $end
-$upscope $end
-$scope begin genblk1[9] $end
-$upscope $end
-$scope begin genblk1[10] $end
-$upscope $end
-$scope begin genblk1[11] $end
-$upscope $end
-$scope begin genblk1[12] $end
-$upscope $end
-$scope begin genblk1[13] $end
-$upscope $end
-$scope begin genblk1[14] $end
-$upscope $end
-$scope begin genblk1[15] $end
-$upscope $end
-$scope begin genblk1[16] $end
-$upscope $end
-$scope begin genblk1[17] $end
-$upscope $end
-$scope begin genblk1[18] $end
-$upscope $end
-$scope begin genblk1[19] $end
-$upscope $end
-$scope begin genblk1[20] $end
-$upscope $end
-$scope begin genblk1[21] $end
-$upscope $end
-$scope begin genblk1[22] $end
-$upscope $end
-$scope begin genblk1[23] $end
-$upscope $end
-$scope begin genblk1[24] $end
-$upscope $end
-$scope begin genblk1[25] $end
-$upscope $end
-$scope begin genblk1[26] $end
-$upscope $end
-$scope begin genblk1[27] $end
-$upscope $end
-$scope begin genblk1[28] $end
-$upscope $end
-$scope begin genblk1[29] $end
-$upscope $end
-$scope begin genblk1[30] $end
-$upscope $end
-$scope begin genblk1[31] $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module padframe $end
-$var wire 1 X? analog_a $end
-$var wire 1 Y? analog_b $end
-$var wire 1 J clock $end
-$var wire 1 " flash_clk $end
-$var wire 1 K flash_clk_ieb_core $end
-$var wire 1 # flash_csb $end
-$var wire 1 L flash_csb_ieb_core $end
-$var wire 1 $ flash_io0 $end
-$var wire 1 % flash_io1 $end
-$var wire 1 & gpio $end
-$var wire 37 Z? mprj_io [36:0] $end
-$var wire 37 [? mprj_io_analog_en [36:0] $end
-$var wire 37 \? mprj_io_analog_pol [36:0] $end
-$var wire 37 ]? mprj_io_analog_sel [36:0] $end
-$var wire 111 ^? mprj_io_dm [110:0] $end
-$var wire 37 _? mprj_io_enh [36:0] $end
-$var wire 37 `? mprj_io_hldh_n [36:0] $end
-$var wire 37 a? mprj_io_holdover [36:0] $end
-$var wire 37 b? mprj_io_ib_mode_sel [36:0] $end
-$var wire 37 c? mprj_io_inp_dis [36:0] $end
-$var wire 37 d? mprj_io_oeb [36:0] $end
-$var wire 37 e? mprj_io_out [36:0] $end
-$var wire 37 f? mprj_io_slow_sel [36:0] $end
-$var wire 37 g? mprj_io_vtrip_sel [36:0] $end
-$var wire 1 h? por $end
-$var wire 1 W resetb $end
-$var wire 1 + vccd $end
-$var wire 1 + vccd1 $end
-$var wire 1 + vccd2 $end
-$var wire 1 * vdda $end
-$var wire 1 * vdda1 $end
-$var wire 1 * vdda2 $end
-$var wire 1 * vddio $end
-$var wire 1 i? vddio_q $end
-$var wire 1 ! vssa $end
-$var wire 1 ! vssa1 $end
-$var wire 1 ! vssa2 $end
-$var wire 1 ! vssd $end
-$var wire 1 ! vssd1 $end
-$var wire 1 ! vssd2 $end
-$var wire 1 ! vssio $end
-$var wire 1 j? vssio_q $end
-$var wire 1 k? xresloop $end
-$var wire 1 f resetb_core_h $end
-$var wire 1 h porb_h $end
-$var wire 37 l? mprj_io_in [36:0] $end
-$var wire 1 m? loop_gpio $end
-$var wire 1 n? loop_flash_io1 $end
-$var wire 1 o? loop_flash_io0 $end
-$var wire 1 p? loop_flash_csb $end
-$var wire 1 q? loop_flash_clk $end
-$var wire 1 r? loop_clock $end
-$var wire 1 /" gpio_outenb_core $end
-$var wire 1 0" gpio_out_core $end
-$var wire 1 1" gpio_mode1_core $end
-$var wire 1 2" gpio_mode0_core $end
-$var wire 1 3" gpio_inenb_core $end
-$var wire 1 4" gpio_in_core $end
-$var wire 1 5" flash_io1_oeb_core $end
-$var wire 3 s? flash_io1_mode [2:0] $end
-$var wire 1 6" flash_io1_ieb_core $end
-$var wire 1 7" flash_io1_do_core $end
-$var wire 1 8" flash_io1_di_core $end
-$var wire 1 9" flash_io0_oeb_core $end
-$var wire 3 t? flash_io0_mode [2:0] $end
-$var wire 1 :" flash_io0_ieb_core $end
-$var wire 1 ;" flash_io0_do_core $end
-$var wire 1 <" flash_io0_di_core $end
-$var wire 1 =" flash_csb_oeb_core $end
-$var wire 1 >" flash_csb_core $end
-$var wire 1 ?" flash_clk_oeb_core $end
-$var wire 1 @" flash_clk_core $end
-$var wire 3 u? dm_all [2:0] $end
-$var wire 1 A" clock_core $end
-$scope module clock_pad $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ! ANALOG_EN $end
-$var wire 1 ! ANALOG_POL $end
-$var wire 1 ! ANALOG_SEL $end
-$var wire 3 v? DM [2:0] $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 * HLD_H_N $end
-$var wire 1 ! HLD_OVR $end
-$var wire 1 ! IB_MODE_SEL $end
-$var wire 1 h? INP_DIS $end
-$var wire 1 + OE_N $end
-$var wire 1 ! OUT $end
-$var wire 1 J PAD $end
-$var wire 1 w? PAD_A_ESD_0_H $end
-$var wire 1 x? PAD_A_ESD_1_H $end
-$var wire 1 y? PAD_A_NOESD_H $end
-$var wire 1 ! SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 ! VTRIP_SEL $end
-$var wire 1 r? TIE_LO_ESD $end
-$var wire 1 z? TIE_HI_ESD $end
-$var wire 1 {? IN_H $end
-$var wire 1 A" IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var wire 1 r? ENABLE_INP_H $end
-$var wire 1 h ENABLE_H $end
-$scope module gpiov2_base $end
-$var event 1 |? event_error_vswitch5 $end
-$var event 1 }? event_error_vswitch4 $end
-$var event 1 ~? event_error_vswitch3 $end
-$var event 1 !@ event_error_vswitch2 $end
-$var event 1 "@ event_error_vswitch1 $end
-$var event 1 #@ event_error_vddio_q2 $end
-$var event 1 $@ event_error_vddio_q1 $end
-$var event 1 %@ event_error_vdda_vddioq_vswitch2 $end
-$var event 1 &@ event_error_vdda3 $end
-$var event 1 '@ event_error_vdda2 $end
-$var event 1 (@ event_error_vdda $end
-$var event 1 )@ event_error_supply_good $end
-$var event 1 *@ event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ! ANALOG_EN $end
-$var wire 1 ! ANALOG_POL $end
-$var wire 1 ! ANALOG_SEL $end
-$var wire 3 +@ DM [2:0] $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 * HLD_H_N $end
-$var wire 1 ! HLD_OVR $end
-$var wire 1 ! IB_MODE_SEL $end
-$var wire 1 h? INP_DIS $end
-$var wire 1 + OE_N $end
-$var wire 1 ! OUT $end
-$var wire 1 J PAD $end
-$var wire 1 w? PAD_A_ESD_0_H $end
-$var wire 1 x? PAD_A_ESD_1_H $end
-$var wire 1 y? PAD_A_NOESD_H $end
-$var wire 1 ! SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 ! VTRIP_SEL $end
-$var wire 3 ,@ dm_buf [2:0] $end
-$var wire 1 -@ error_enable_vddio $end
-$var wire 1 .@ error_supply_good $end
-$var wire 1 /@ error_vdda $end
-$var wire 1 0@ error_vdda2 $end
-$var wire 1 1@ error_vdda3 $end
-$var wire 1 2@ error_vdda_vddioq_vswitch2 $end
-$var wire 1 3@ error_vddio_q1 $end
-$var wire 1 4@ error_vddio_q2 $end
-$var wire 1 5@ error_vswitch1 $end
-$var wire 1 6@ error_vswitch2 $end
-$var wire 1 7@ error_vswitch3 $end
-$var wire 1 8@ error_vswitch4 $end
-$var wire 1 9@ error_vswitch5 $end
-$var wire 1 :@ functional_mode_amux $end
-$var wire 1 ;@ hld_h_n_buf $end
-$var wire 1 <@ hld_ovr_buf $end
-$var wire 1 =@ ib_mode_sel_buf $end
-$var wire 1 >@ inp_dis_buf $end
-$var wire 1 ?@ invalid_controls_amux $end
-$var wire 1 @@ oe_n_buf $end
-$var wire 1 A@ out_buf $end
-$var wire 1 B@ pad_tristate $end
-$var wire 1 C@ pwr_good_active_mode $end
-$var wire 1 D@ pwr_good_active_mode_vdda $end
-$var wire 1 E@ pwr_good_amux $end
-$var wire 1 F@ pwr_good_analog_en_vdda $end
-$var wire 1 G@ pwr_good_analog_en_vddio_q $end
-$var wire 1 H@ pwr_good_analog_en_vswitch $end
-$var wire 1 I@ pwr_good_hold_mode $end
-$var wire 1 J@ pwr_good_hold_mode_vdda $end
-$var wire 1 K@ pwr_good_hold_ovr_mode $end
-$var wire 1 L@ pwr_good_inpbuff_hv $end
-$var wire 1 M@ pwr_good_inpbuff_lv $end
-$var wire 1 N@ pwr_good_output_driver $end
-$var wire 1 O@ slow_buf $end
-$var wire 1 P@ vtrip_sel_buf $end
-$var wire 1 Q@ x_on_analog_en_vdda $end
-$var wire 1 R@ x_on_analog_en_vddio_q $end
-$var wire 1 S@ x_on_analog_en_vswitch $end
-$var wire 1 T@ x_on_in_hv $end
-$var wire 1 U@ x_on_in_lv $end
-$var wire 1 V@ x_on_pad $end
-$var wire 1 W@ zero_on_analog_en_vdda $end
-$var wire 1 X@ zero_on_analog_en_vddio_q $end
-$var wire 1 Y@ zero_on_analog_en_vswitch $end
-$var wire 1 Z@ pwr_good_amux_vccd $end
-$var wire 1 [@ enable_pad_vssio_q $end
-$var wire 1 \@ enable_pad_vddio_q $end
-$var wire 1 ]@ enable_pad_amuxbus_b $end
-$var wire 1 ^@ enable_pad_amuxbus_a $end
-$var wire 1 _@ disable_inp_buff_lv $end
-$var wire 1 `@ disable_inp_buff $end
-$var wire 3 a@ amux_select [2:0] $end
-$var wire 1 r? TIE_LO_ESD $end
-$var wire 1 z? TIE_HI_ESD $end
-$var wire 1 {? IN_H $end
-$var wire 1 A" IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var wire 1 r? ENABLE_INP_H $end
-$var wire 1 h ENABLE_H $end
-$var reg 1 b@ analog_en_final $end
-$var reg 1 c@ analog_en_vdda $end
-$var reg 1 d@ analog_en_vddio_q $end
-$var reg 1 e@ analog_en_vswitch $end
-$var reg 1 f@ dis_err_msgs $end
-$var reg 3 g@ dm_final [2:0] $end
-$var reg 1 h@ hld_ovr_final $end
-$var reg 1 i@ ib_mode_sel_final $end
-$var reg 1 j@ inp_dis_final $end
-$var reg 1 k@ notifier_dm $end
-$var reg 1 l@ notifier_enable_h $end
-$var reg 1 m@ notifier_hld_ovr $end
-$var reg 1 n@ notifier_ib_mode_sel $end
-$var reg 1 o@ notifier_inp_dis $end
-$var reg 1 p@ notifier_oe_n $end
-$var reg 1 q@ notifier_out $end
-$var reg 1 r@ notifier_slow $end
-$var reg 1 s@ notifier_vtrip_sel $end
-$var reg 1 t@ oe_n_final $end
-$var reg 1 u@ out_final $end
-$var reg 1 v@ slow_final $end
-$var reg 1 w@ vtrip_sel_final $end
-$var integer 32 x@ msg_count_pad [31:0] $end
-$var integer 32 y@ msg_count_pad1 [31:0] $end
-$var integer 32 z@ msg_count_pad10 [31:0] $end
-$var integer 32 {@ msg_count_pad11 [31:0] $end
-$var integer 32 |@ msg_count_pad12 [31:0] $end
-$var integer 32 }@ msg_count_pad2 [31:0] $end
-$var integer 32 ~@ msg_count_pad3 [31:0] $end
-$var integer 32 !A msg_count_pad4 [31:0] $end
-$var integer 32 "A msg_count_pad5 [31:0] $end
-$var integer 32 #A msg_count_pad6 [31:0] $end
-$var integer 32 $A msg_count_pad7 [31:0] $end
-$var integer 32 %A msg_count_pad8 [31:0] $end
-$var integer 32 &A msg_count_pad9 [31:0] $end
-$var integer 32 'A slow_0_delay [31:0] $end
-$var integer 32 (A slow_1_delay [31:0] $end
-$var integer 32 )A slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module flash_clk_pad $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ! ANALOG_EN $end
-$var wire 1 ! ANALOG_POL $end
-$var wire 1 ! ANALOG_SEL $end
-$var wire 3 *A DM [2:0] $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 * HLD_H_N $end
-$var wire 1 ! HLD_OVR $end
-$var wire 1 ! IB_MODE_SEL $end
-$var wire 1 K INP_DIS $end
-$var wire 1 " PAD $end
-$var wire 1 +A PAD_A_ESD_0_H $end
-$var wire 1 ,A PAD_A_ESD_1_H $end
-$var wire 1 -A PAD_A_NOESD_H $end
-$var wire 1 ! SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 ! VTRIP_SEL $end
-$var wire 1 q? TIE_LO_ESD $end
-$var wire 1 .A TIE_HI_ESD $end
-$var wire 1 @" OUT $end
-$var wire 1 ?" OE_N $end
-$var wire 1 /A IN_H $end
-$var wire 1 0A IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var wire 1 q? ENABLE_INP_H $end
-$var wire 1 h ENABLE_H $end
-$scope module gpiov2_base $end
-$var event 1 1A event_error_vswitch5 $end
-$var event 1 2A event_error_vswitch4 $end
-$var event 1 3A event_error_vswitch3 $end
-$var event 1 4A event_error_vswitch2 $end
-$var event 1 5A event_error_vswitch1 $end
-$var event 1 6A event_error_vddio_q2 $end
-$var event 1 7A event_error_vddio_q1 $end
-$var event 1 8A event_error_vdda_vddioq_vswitch2 $end
-$var event 1 9A event_error_vdda3 $end
-$var event 1 :A event_error_vdda2 $end
-$var event 1 ;A event_error_vdda $end
-$var event 1 <A event_error_supply_good $end
-$var event 1 =A event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ! ANALOG_EN $end
-$var wire 1 ! ANALOG_POL $end
-$var wire 1 ! ANALOG_SEL $end
-$var wire 3 >A DM [2:0] $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 * HLD_H_N $end
-$var wire 1 ! HLD_OVR $end
-$var wire 1 ! IB_MODE_SEL $end
-$var wire 1 K INP_DIS $end
-$var wire 1 " PAD $end
-$var wire 1 +A PAD_A_ESD_0_H $end
-$var wire 1 ,A PAD_A_ESD_1_H $end
-$var wire 1 -A PAD_A_NOESD_H $end
-$var wire 1 ! SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 ! VTRIP_SEL $end
-$var wire 3 ?A dm_buf [2:0] $end
-$var wire 1 @A error_enable_vddio $end
-$var wire 1 AA error_supply_good $end
-$var wire 1 BA error_vdda $end
-$var wire 1 CA error_vdda2 $end
-$var wire 1 DA error_vdda3 $end
-$var wire 1 EA error_vdda_vddioq_vswitch2 $end
-$var wire 1 FA error_vddio_q1 $end
-$var wire 1 GA error_vddio_q2 $end
-$var wire 1 HA error_vswitch1 $end
-$var wire 1 IA error_vswitch2 $end
-$var wire 1 JA error_vswitch3 $end
-$var wire 1 KA error_vswitch4 $end
-$var wire 1 LA error_vswitch5 $end
-$var wire 1 MA functional_mode_amux $end
-$var wire 1 NA hld_h_n_buf $end
-$var wire 1 OA hld_ovr_buf $end
-$var wire 1 PA ib_mode_sel_buf $end
-$var wire 1 QA inp_dis_buf $end
-$var wire 1 RA invalid_controls_amux $end
-$var wire 1 SA oe_n_buf $end
-$var wire 1 TA out_buf $end
-$var wire 1 UA pad_tristate $end
-$var wire 1 VA pwr_good_active_mode $end
-$var wire 1 WA pwr_good_active_mode_vdda $end
-$var wire 1 XA pwr_good_amux $end
-$var wire 1 YA pwr_good_analog_en_vdda $end
-$var wire 1 ZA pwr_good_analog_en_vddio_q $end
-$var wire 1 [A pwr_good_analog_en_vswitch $end
-$var wire 1 \A pwr_good_hold_mode $end
-$var wire 1 ]A pwr_good_hold_mode_vdda $end
-$var wire 1 ^A pwr_good_hold_ovr_mode $end
-$var wire 1 _A pwr_good_inpbuff_hv $end
-$var wire 1 `A pwr_good_inpbuff_lv $end
-$var wire 1 aA pwr_good_output_driver $end
-$var wire 1 bA slow_buf $end
-$var wire 1 cA vtrip_sel_buf $end
-$var wire 1 dA x_on_analog_en_vdda $end
-$var wire 1 eA x_on_analog_en_vddio_q $end
-$var wire 1 fA x_on_analog_en_vswitch $end
-$var wire 1 gA x_on_in_hv $end
-$var wire 1 hA x_on_in_lv $end
-$var wire 1 iA x_on_pad $end
-$var wire 1 jA zero_on_analog_en_vdda $end
-$var wire 1 kA zero_on_analog_en_vddio_q $end
-$var wire 1 lA zero_on_analog_en_vswitch $end
-$var wire 1 mA pwr_good_amux_vccd $end
-$var wire 1 nA enable_pad_vssio_q $end
-$var wire 1 oA enable_pad_vddio_q $end
-$var wire 1 pA enable_pad_amuxbus_b $end
-$var wire 1 qA enable_pad_amuxbus_a $end
-$var wire 1 rA disable_inp_buff_lv $end
-$var wire 1 sA disable_inp_buff $end
-$var wire 3 tA amux_select [2:0] $end
-$var wire 1 q? TIE_LO_ESD $end
-$var wire 1 .A TIE_HI_ESD $end
-$var wire 1 @" OUT $end
-$var wire 1 ?" OE_N $end
-$var wire 1 /A IN_H $end
-$var wire 1 0A IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var wire 1 q? ENABLE_INP_H $end
-$var wire 1 h ENABLE_H $end
-$var reg 1 uA analog_en_final $end
-$var reg 1 vA analog_en_vdda $end
-$var reg 1 wA analog_en_vddio_q $end
-$var reg 1 xA analog_en_vswitch $end
-$var reg 1 yA dis_err_msgs $end
-$var reg 3 zA dm_final [2:0] $end
-$var reg 1 {A hld_ovr_final $end
-$var reg 1 |A ib_mode_sel_final $end
-$var reg 1 }A inp_dis_final $end
-$var reg 1 ~A notifier_dm $end
-$var reg 1 !B notifier_enable_h $end
-$var reg 1 "B notifier_hld_ovr $end
-$var reg 1 #B notifier_ib_mode_sel $end
-$var reg 1 $B notifier_inp_dis $end
-$var reg 1 %B notifier_oe_n $end
-$var reg 1 &B notifier_out $end
-$var reg 1 'B notifier_slow $end
-$var reg 1 (B notifier_vtrip_sel $end
-$var reg 1 )B oe_n_final $end
-$var reg 1 *B out_final $end
-$var reg 1 +B slow_final $end
-$var reg 1 ,B vtrip_sel_final $end
-$var integer 32 -B msg_count_pad [31:0] $end
-$var integer 32 .B msg_count_pad1 [31:0] $end
-$var integer 32 /B msg_count_pad10 [31:0] $end
-$var integer 32 0B msg_count_pad11 [31:0] $end
-$var integer 32 1B msg_count_pad12 [31:0] $end
-$var integer 32 2B msg_count_pad2 [31:0] $end
-$var integer 32 3B msg_count_pad3 [31:0] $end
-$var integer 32 4B msg_count_pad4 [31:0] $end
-$var integer 32 5B msg_count_pad5 [31:0] $end
-$var integer 32 6B msg_count_pad6 [31:0] $end
-$var integer 32 7B msg_count_pad7 [31:0] $end
-$var integer 32 8B msg_count_pad8 [31:0] $end
-$var integer 32 9B msg_count_pad9 [31:0] $end
-$var integer 32 :B slow_0_delay [31:0] $end
-$var integer 32 ;B slow_1_delay [31:0] $end
-$var integer 32 <B slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module flash_csb_pad $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ! ANALOG_EN $end
-$var wire 1 ! ANALOG_POL $end
-$var wire 1 ! ANALOG_SEL $end
-$var wire 3 =B DM [2:0] $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 * HLD_H_N $end
-$var wire 1 ! HLD_OVR $end
-$var wire 1 ! IB_MODE_SEL $end
-$var wire 1 L INP_DIS $end
-$var wire 1 # PAD $end
-$var wire 1 >B PAD_A_ESD_0_H $end
-$var wire 1 ?B PAD_A_ESD_1_H $end
-$var wire 1 @B PAD_A_NOESD_H $end
-$var wire 1 ! SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 ! VTRIP_SEL $end
-$var wire 1 p? TIE_LO_ESD $end
-$var wire 1 AB TIE_HI_ESD $end
-$var wire 1 >" OUT $end
-$var wire 1 =" OE_N $end
-$var wire 1 BB IN_H $end
-$var wire 1 CB IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var wire 1 p? ENABLE_INP_H $end
-$var wire 1 h ENABLE_H $end
-$scope module gpiov2_base $end
-$var event 1 DB event_error_vswitch5 $end
-$var event 1 EB event_error_vswitch4 $end
-$var event 1 FB event_error_vswitch3 $end
-$var event 1 GB event_error_vswitch2 $end
-$var event 1 HB event_error_vswitch1 $end
-$var event 1 IB event_error_vddio_q2 $end
-$var event 1 JB event_error_vddio_q1 $end
-$var event 1 KB event_error_vdda_vddioq_vswitch2 $end
-$var event 1 LB event_error_vdda3 $end
-$var event 1 MB event_error_vdda2 $end
-$var event 1 NB event_error_vdda $end
-$var event 1 OB event_error_supply_good $end
-$var event 1 PB event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ! ANALOG_EN $end
-$var wire 1 ! ANALOG_POL $end
-$var wire 1 ! ANALOG_SEL $end
-$var wire 3 QB DM [2:0] $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 * HLD_H_N $end
-$var wire 1 ! HLD_OVR $end
-$var wire 1 ! IB_MODE_SEL $end
-$var wire 1 L INP_DIS $end
-$var wire 1 # PAD $end
-$var wire 1 >B PAD_A_ESD_0_H $end
-$var wire 1 ?B PAD_A_ESD_1_H $end
-$var wire 1 @B PAD_A_NOESD_H $end
-$var wire 1 ! SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 ! VTRIP_SEL $end
-$var wire 3 RB dm_buf [2:0] $end
-$var wire 1 SB error_enable_vddio $end
-$var wire 1 TB error_supply_good $end
-$var wire 1 UB error_vdda $end
-$var wire 1 VB error_vdda2 $end
-$var wire 1 WB error_vdda3 $end
-$var wire 1 XB error_vdda_vddioq_vswitch2 $end
-$var wire 1 YB error_vddio_q1 $end
-$var wire 1 ZB error_vddio_q2 $end
-$var wire 1 [B error_vswitch1 $end
-$var wire 1 \B error_vswitch2 $end
-$var wire 1 ]B error_vswitch3 $end
-$var wire 1 ^B error_vswitch4 $end
-$var wire 1 _B error_vswitch5 $end
-$var wire 1 `B functional_mode_amux $end
-$var wire 1 aB hld_h_n_buf $end
-$var wire 1 bB hld_ovr_buf $end
-$var wire 1 cB ib_mode_sel_buf $end
-$var wire 1 dB inp_dis_buf $end
-$var wire 1 eB invalid_controls_amux $end
-$var wire 1 fB oe_n_buf $end
-$var wire 1 gB out_buf $end
-$var wire 1 hB pad_tristate $end
-$var wire 1 iB pwr_good_active_mode $end
-$var wire 1 jB pwr_good_active_mode_vdda $end
-$var wire 1 kB pwr_good_amux $end
-$var wire 1 lB pwr_good_analog_en_vdda $end
-$var wire 1 mB pwr_good_analog_en_vddio_q $end
-$var wire 1 nB pwr_good_analog_en_vswitch $end
-$var wire 1 oB pwr_good_hold_mode $end
-$var wire 1 pB pwr_good_hold_mode_vdda $end
-$var wire 1 qB pwr_good_hold_ovr_mode $end
-$var wire 1 rB pwr_good_inpbuff_hv $end
-$var wire 1 sB pwr_good_inpbuff_lv $end
-$var wire 1 tB pwr_good_output_driver $end
-$var wire 1 uB slow_buf $end
-$var wire 1 vB vtrip_sel_buf $end
-$var wire 1 wB x_on_analog_en_vdda $end
-$var wire 1 xB x_on_analog_en_vddio_q $end
-$var wire 1 yB x_on_analog_en_vswitch $end
-$var wire 1 zB x_on_in_hv $end
-$var wire 1 {B x_on_in_lv $end
-$var wire 1 |B x_on_pad $end
-$var wire 1 }B zero_on_analog_en_vdda $end
-$var wire 1 ~B zero_on_analog_en_vddio_q $end
-$var wire 1 !C zero_on_analog_en_vswitch $end
-$var wire 1 "C pwr_good_amux_vccd $end
-$var wire 1 #C enable_pad_vssio_q $end
-$var wire 1 $C enable_pad_vddio_q $end
-$var wire 1 %C enable_pad_amuxbus_b $end
-$var wire 1 &C enable_pad_amuxbus_a $end
-$var wire 1 'C disable_inp_buff_lv $end
-$var wire 1 (C disable_inp_buff $end
-$var wire 3 )C amux_select [2:0] $end
-$var wire 1 p? TIE_LO_ESD $end
-$var wire 1 AB TIE_HI_ESD $end
-$var wire 1 >" OUT $end
-$var wire 1 =" OE_N $end
-$var wire 1 BB IN_H $end
-$var wire 1 CB IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var wire 1 p? ENABLE_INP_H $end
-$var wire 1 h ENABLE_H $end
-$var reg 1 *C analog_en_final $end
-$var reg 1 +C analog_en_vdda $end
-$var reg 1 ,C analog_en_vddio_q $end
-$var reg 1 -C analog_en_vswitch $end
-$var reg 1 .C dis_err_msgs $end
-$var reg 3 /C dm_final [2:0] $end
-$var reg 1 0C hld_ovr_final $end
-$var reg 1 1C ib_mode_sel_final $end
-$var reg 1 2C inp_dis_final $end
-$var reg 1 3C notifier_dm $end
-$var reg 1 4C notifier_enable_h $end
-$var reg 1 5C notifier_hld_ovr $end
-$var reg 1 6C notifier_ib_mode_sel $end
-$var reg 1 7C notifier_inp_dis $end
-$var reg 1 8C notifier_oe_n $end
-$var reg 1 9C notifier_out $end
-$var reg 1 :C notifier_slow $end
-$var reg 1 ;C notifier_vtrip_sel $end
-$var reg 1 <C oe_n_final $end
-$var reg 1 =C out_final $end
-$var reg 1 >C slow_final $end
-$var reg 1 ?C vtrip_sel_final $end
-$var integer 32 @C msg_count_pad [31:0] $end
-$var integer 32 AC msg_count_pad1 [31:0] $end
-$var integer 32 BC msg_count_pad10 [31:0] $end
-$var integer 32 CC msg_count_pad11 [31:0] $end
-$var integer 32 DC msg_count_pad12 [31:0] $end
-$var integer 32 EC msg_count_pad2 [31:0] $end
-$var integer 32 FC msg_count_pad3 [31:0] $end
-$var integer 32 GC msg_count_pad4 [31:0] $end
-$var integer 32 HC msg_count_pad5 [31:0] $end
-$var integer 32 IC msg_count_pad6 [31:0] $end
-$var integer 32 JC msg_count_pad7 [31:0] $end
-$var integer 32 KC msg_count_pad8 [31:0] $end
-$var integer 32 LC msg_count_pad9 [31:0] $end
-$var integer 32 MC slow_0_delay [31:0] $end
-$var integer 32 NC slow_1_delay [31:0] $end
-$var integer 32 OC slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module flash_io0_pad $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ! ANALOG_EN $end
-$var wire 1 ! ANALOG_POL $end
-$var wire 1 ! ANALOG_SEL $end
-$var wire 3 PC DM [2:0] $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 * HLD_H_N $end
-$var wire 1 ! HLD_OVR $end
-$var wire 1 ! IB_MODE_SEL $end
-$var wire 1 $ PAD $end
-$var wire 1 QC PAD_A_ESD_0_H $end
-$var wire 1 RC PAD_A_ESD_1_H $end
-$var wire 1 SC PAD_A_NOESD_H $end
-$var wire 1 ! SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 ! VTRIP_SEL $end
-$var wire 1 o? TIE_LO_ESD $end
-$var wire 1 TC TIE_HI_ESD $end
-$var wire 1 ;" OUT $end
-$var wire 1 9" OE_N $end
-$var wire 1 UC IN_H $end
-$var wire 1 :" INP_DIS $end
-$var wire 1 <" IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var wire 1 o? ENABLE_INP_H $end
-$var wire 1 h ENABLE_H $end
-$scope module gpiov2_base $end
-$var event 1 VC event_error_vswitch5 $end
-$var event 1 WC event_error_vswitch4 $end
-$var event 1 XC event_error_vswitch3 $end
-$var event 1 YC event_error_vswitch2 $end
-$var event 1 ZC event_error_vswitch1 $end
-$var event 1 [C event_error_vddio_q2 $end
-$var event 1 \C event_error_vddio_q1 $end
-$var event 1 ]C event_error_vdda_vddioq_vswitch2 $end
-$var event 1 ^C event_error_vdda3 $end
-$var event 1 _C event_error_vdda2 $end
-$var event 1 `C event_error_vdda $end
-$var event 1 aC event_error_supply_good $end
-$var event 1 bC event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ! ANALOG_EN $end
-$var wire 1 ! ANALOG_POL $end
-$var wire 1 ! ANALOG_SEL $end
-$var wire 3 cC DM [2:0] $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 * HLD_H_N $end
-$var wire 1 ! HLD_OVR $end
-$var wire 1 ! IB_MODE_SEL $end
-$var wire 1 $ PAD $end
-$var wire 1 QC PAD_A_ESD_0_H $end
-$var wire 1 RC PAD_A_ESD_1_H $end
-$var wire 1 SC PAD_A_NOESD_H $end
-$var wire 1 ! SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 ! VTRIP_SEL $end
-$var wire 3 dC dm_buf [2:0] $end
-$var wire 1 eC error_enable_vddio $end
-$var wire 1 fC error_supply_good $end
-$var wire 1 gC error_vdda $end
-$var wire 1 hC error_vdda2 $end
-$var wire 1 iC error_vdda3 $end
-$var wire 1 jC error_vdda_vddioq_vswitch2 $end
-$var wire 1 kC error_vddio_q1 $end
-$var wire 1 lC error_vddio_q2 $end
-$var wire 1 mC error_vswitch1 $end
-$var wire 1 nC error_vswitch2 $end
-$var wire 1 oC error_vswitch3 $end
-$var wire 1 pC error_vswitch4 $end
-$var wire 1 qC error_vswitch5 $end
-$var wire 1 rC functional_mode_amux $end
-$var wire 1 sC hld_h_n_buf $end
-$var wire 1 tC hld_ovr_buf $end
-$var wire 1 uC ib_mode_sel_buf $end
-$var wire 1 vC inp_dis_buf $end
-$var wire 1 wC invalid_controls_amux $end
-$var wire 1 xC oe_n_buf $end
-$var wire 1 yC out_buf $end
-$var wire 1 zC pad_tristate $end
-$var wire 1 {C pwr_good_active_mode $end
-$var wire 1 |C pwr_good_active_mode_vdda $end
-$var wire 1 }C pwr_good_amux $end
-$var wire 1 ~C pwr_good_analog_en_vdda $end
-$var wire 1 !D pwr_good_analog_en_vddio_q $end
-$var wire 1 "D pwr_good_analog_en_vswitch $end
-$var wire 1 #D pwr_good_hold_mode $end
-$var wire 1 $D pwr_good_hold_mode_vdda $end
-$var wire 1 %D pwr_good_hold_ovr_mode $end
-$var wire 1 &D pwr_good_inpbuff_hv $end
-$var wire 1 'D pwr_good_inpbuff_lv $end
-$var wire 1 (D pwr_good_output_driver $end
-$var wire 1 )D slow_buf $end
-$var wire 1 *D vtrip_sel_buf $end
-$var wire 1 +D x_on_analog_en_vdda $end
-$var wire 1 ,D x_on_analog_en_vddio_q $end
-$var wire 1 -D x_on_analog_en_vswitch $end
-$var wire 1 .D x_on_in_hv $end
-$var wire 1 /D x_on_in_lv $end
-$var wire 1 0D x_on_pad $end
-$var wire 1 1D zero_on_analog_en_vdda $end
-$var wire 1 2D zero_on_analog_en_vddio_q $end
-$var wire 1 3D zero_on_analog_en_vswitch $end
-$var wire 1 4D pwr_good_amux_vccd $end
-$var wire 1 5D enable_pad_vssio_q $end
-$var wire 1 6D enable_pad_vddio_q $end
-$var wire 1 7D enable_pad_amuxbus_b $end
-$var wire 1 8D enable_pad_amuxbus_a $end
-$var wire 1 9D disable_inp_buff_lv $end
-$var wire 1 :D disable_inp_buff $end
-$var wire 3 ;D amux_select [2:0] $end
-$var wire 1 o? TIE_LO_ESD $end
-$var wire 1 TC TIE_HI_ESD $end
-$var wire 1 ;" OUT $end
-$var wire 1 9" OE_N $end
-$var wire 1 UC IN_H $end
-$var wire 1 :" INP_DIS $end
-$var wire 1 <" IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var wire 1 o? ENABLE_INP_H $end
-$var wire 1 h ENABLE_H $end
-$var reg 1 <D analog_en_final $end
-$var reg 1 =D analog_en_vdda $end
-$var reg 1 >D analog_en_vddio_q $end
-$var reg 1 ?D analog_en_vswitch $end
-$var reg 1 @D dis_err_msgs $end
-$var reg 3 AD dm_final [2:0] $end
-$var reg 1 BD hld_ovr_final $end
-$var reg 1 CD ib_mode_sel_final $end
-$var reg 1 DD inp_dis_final $end
-$var reg 1 ED notifier_dm $end
-$var reg 1 FD notifier_enable_h $end
-$var reg 1 GD notifier_hld_ovr $end
-$var reg 1 HD notifier_ib_mode_sel $end
-$var reg 1 ID notifier_inp_dis $end
-$var reg 1 JD notifier_oe_n $end
-$var reg 1 KD notifier_out $end
-$var reg 1 LD notifier_slow $end
-$var reg 1 MD notifier_vtrip_sel $end
-$var reg 1 ND oe_n_final $end
-$var reg 1 OD out_final $end
-$var reg 1 PD slow_final $end
-$var reg 1 QD vtrip_sel_final $end
-$var integer 32 RD msg_count_pad [31:0] $end
-$var integer 32 SD msg_count_pad1 [31:0] $end
-$var integer 32 TD msg_count_pad10 [31:0] $end
-$var integer 32 UD msg_count_pad11 [31:0] $end
-$var integer 32 VD msg_count_pad12 [31:0] $end
-$var integer 32 WD msg_count_pad2 [31:0] $end
-$var integer 32 XD msg_count_pad3 [31:0] $end
-$var integer 32 YD msg_count_pad4 [31:0] $end
-$var integer 32 ZD msg_count_pad5 [31:0] $end
-$var integer 32 [D msg_count_pad6 [31:0] $end
-$var integer 32 \D msg_count_pad7 [31:0] $end
-$var integer 32 ]D msg_count_pad8 [31:0] $end
-$var integer 32 ^D msg_count_pad9 [31:0] $end
-$var integer 32 _D slow_0_delay [31:0] $end
-$var integer 32 `D slow_1_delay [31:0] $end
-$var integer 32 aD slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module flash_io1_pad $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ! ANALOG_EN $end
-$var wire 1 ! ANALOG_POL $end
-$var wire 1 ! ANALOG_SEL $end
-$var wire 3 bD DM [2:0] $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 * HLD_H_N $end
-$var wire 1 ! HLD_OVR $end
-$var wire 1 ! IB_MODE_SEL $end
-$var wire 1 % PAD $end
-$var wire 1 cD PAD_A_ESD_0_H $end
-$var wire 1 dD PAD_A_ESD_1_H $end
-$var wire 1 eD PAD_A_NOESD_H $end
-$var wire 1 ! SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 ! VTRIP_SEL $end
-$var wire 1 n? TIE_LO_ESD $end
-$var wire 1 fD TIE_HI_ESD $end
-$var wire 1 7" OUT $end
-$var wire 1 5" OE_N $end
-$var wire 1 gD IN_H $end
-$var wire 1 6" INP_DIS $end
-$var wire 1 8" IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var wire 1 n? ENABLE_INP_H $end
-$var wire 1 h ENABLE_H $end
-$scope module gpiov2_base $end
-$var event 1 hD event_error_vswitch5 $end
-$var event 1 iD event_error_vswitch4 $end
-$var event 1 jD event_error_vswitch3 $end
-$var event 1 kD event_error_vswitch2 $end
-$var event 1 lD event_error_vswitch1 $end
-$var event 1 mD event_error_vddio_q2 $end
-$var event 1 nD event_error_vddio_q1 $end
-$var event 1 oD event_error_vdda_vddioq_vswitch2 $end
-$var event 1 pD event_error_vdda3 $end
-$var event 1 qD event_error_vdda2 $end
-$var event 1 rD event_error_vdda $end
-$var event 1 sD event_error_supply_good $end
-$var event 1 tD event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ! ANALOG_EN $end
-$var wire 1 ! ANALOG_POL $end
-$var wire 1 ! ANALOG_SEL $end
-$var wire 3 uD DM [2:0] $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 * HLD_H_N $end
-$var wire 1 ! HLD_OVR $end
-$var wire 1 ! IB_MODE_SEL $end
-$var wire 1 % PAD $end
-$var wire 1 cD PAD_A_ESD_0_H $end
-$var wire 1 dD PAD_A_ESD_1_H $end
-$var wire 1 eD PAD_A_NOESD_H $end
-$var wire 1 ! SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 ! VTRIP_SEL $end
-$var wire 3 vD dm_buf [2:0] $end
-$var wire 1 wD error_enable_vddio $end
-$var wire 1 xD error_supply_good $end
-$var wire 1 yD error_vdda $end
-$var wire 1 zD error_vdda2 $end
-$var wire 1 {D error_vdda3 $end
-$var wire 1 |D error_vdda_vddioq_vswitch2 $end
-$var wire 1 }D error_vddio_q1 $end
-$var wire 1 ~D error_vddio_q2 $end
-$var wire 1 !E error_vswitch1 $end
-$var wire 1 "E error_vswitch2 $end
-$var wire 1 #E error_vswitch3 $end
-$var wire 1 $E error_vswitch4 $end
-$var wire 1 %E error_vswitch5 $end
-$var wire 1 &E functional_mode_amux $end
-$var wire 1 'E hld_h_n_buf $end
-$var wire 1 (E hld_ovr_buf $end
-$var wire 1 )E ib_mode_sel_buf $end
-$var wire 1 *E inp_dis_buf $end
-$var wire 1 +E invalid_controls_amux $end
-$var wire 1 ,E oe_n_buf $end
-$var wire 1 -E out_buf $end
-$var wire 1 .E pad_tristate $end
-$var wire 1 /E pwr_good_active_mode $end
-$var wire 1 0E pwr_good_active_mode_vdda $end
-$var wire 1 1E pwr_good_amux $end
-$var wire 1 2E pwr_good_analog_en_vdda $end
-$var wire 1 3E pwr_good_analog_en_vddio_q $end
-$var wire 1 4E pwr_good_analog_en_vswitch $end
-$var wire 1 5E pwr_good_hold_mode $end
-$var wire 1 6E pwr_good_hold_mode_vdda $end
-$var wire 1 7E pwr_good_hold_ovr_mode $end
-$var wire 1 8E pwr_good_inpbuff_hv $end
-$var wire 1 9E pwr_good_inpbuff_lv $end
-$var wire 1 :E pwr_good_output_driver $end
-$var wire 1 ;E slow_buf $end
-$var wire 1 <E vtrip_sel_buf $end
-$var wire 1 =E x_on_analog_en_vdda $end
-$var wire 1 >E x_on_analog_en_vddio_q $end
-$var wire 1 ?E x_on_analog_en_vswitch $end
-$var wire 1 @E x_on_in_hv $end
-$var wire 1 AE x_on_in_lv $end
-$var wire 1 BE x_on_pad $end
-$var wire 1 CE zero_on_analog_en_vdda $end
-$var wire 1 DE zero_on_analog_en_vddio_q $end
-$var wire 1 EE zero_on_analog_en_vswitch $end
-$var wire 1 FE pwr_good_amux_vccd $end
-$var wire 1 GE enable_pad_vssio_q $end
-$var wire 1 HE enable_pad_vddio_q $end
-$var wire 1 IE enable_pad_amuxbus_b $end
-$var wire 1 JE enable_pad_amuxbus_a $end
-$var wire 1 KE disable_inp_buff_lv $end
-$var wire 1 LE disable_inp_buff $end
-$var wire 3 ME amux_select [2:0] $end
-$var wire 1 n? TIE_LO_ESD $end
-$var wire 1 fD TIE_HI_ESD $end
-$var wire 1 7" OUT $end
-$var wire 1 5" OE_N $end
-$var wire 1 gD IN_H $end
-$var wire 1 6" INP_DIS $end
-$var wire 1 8" IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var wire 1 n? ENABLE_INP_H $end
-$var wire 1 h ENABLE_H $end
-$var reg 1 NE analog_en_final $end
-$var reg 1 OE analog_en_vdda $end
-$var reg 1 PE analog_en_vddio_q $end
-$var reg 1 QE analog_en_vswitch $end
-$var reg 1 RE dis_err_msgs $end
-$var reg 3 SE dm_final [2:0] $end
-$var reg 1 TE hld_ovr_final $end
-$var reg 1 UE ib_mode_sel_final $end
-$var reg 1 VE inp_dis_final $end
-$var reg 1 WE notifier_dm $end
-$var reg 1 XE notifier_enable_h $end
-$var reg 1 YE notifier_hld_ovr $end
-$var reg 1 ZE notifier_ib_mode_sel $end
-$var reg 1 [E notifier_inp_dis $end
-$var reg 1 \E notifier_oe_n $end
-$var reg 1 ]E notifier_out $end
-$var reg 1 ^E notifier_slow $end
-$var reg 1 _E notifier_vtrip_sel $end
-$var reg 1 `E oe_n_final $end
-$var reg 1 aE out_final $end
-$var reg 1 bE slow_final $end
-$var reg 1 cE vtrip_sel_final $end
-$var integer 32 dE msg_count_pad [31:0] $end
-$var integer 32 eE msg_count_pad1 [31:0] $end
-$var integer 32 fE msg_count_pad10 [31:0] $end
-$var integer 32 gE msg_count_pad11 [31:0] $end
-$var integer 32 hE msg_count_pad12 [31:0] $end
-$var integer 32 iE msg_count_pad2 [31:0] $end
-$var integer 32 jE msg_count_pad3 [31:0] $end
-$var integer 32 kE msg_count_pad4 [31:0] $end
-$var integer 32 lE msg_count_pad5 [31:0] $end
-$var integer 32 mE msg_count_pad6 [31:0] $end
-$var integer 32 nE msg_count_pad7 [31:0] $end
-$var integer 32 oE msg_count_pad8 [31:0] $end
-$var integer 32 pE msg_count_pad9 [31:0] $end
-$var integer 32 qE slow_0_delay [31:0] $end
-$var integer 32 rE slow_1_delay [31:0] $end
-$var integer 32 sE slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module gpio_pad $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ! ANALOG_EN $end
-$var wire 1 ! ANALOG_POL $end
-$var wire 1 ! ANALOG_SEL $end
-$var wire 3 tE DM [2:0] $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 * HLD_H_N $end
-$var wire 1 ! HLD_OVR $end
-$var wire 1 ! IB_MODE_SEL $end
-$var wire 1 & PAD $end
-$var wire 1 uE PAD_A_ESD_0_H $end
-$var wire 1 vE PAD_A_ESD_1_H $end
-$var wire 1 wE PAD_A_NOESD_H $end
-$var wire 1 ! SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 ! VTRIP_SEL $end
-$var wire 1 m? TIE_LO_ESD $end
-$var wire 1 xE TIE_HI_ESD $end
-$var wire 1 0" OUT $end
-$var wire 1 /" OE_N $end
-$var wire 1 yE IN_H $end
-$var wire 1 3" INP_DIS $end
-$var wire 1 4" IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var wire 1 m? ENABLE_INP_H $end
-$var wire 1 h ENABLE_H $end
-$scope module gpiov2_base $end
-$var event 1 zE event_error_vswitch5 $end
-$var event 1 {E event_error_vswitch4 $end
-$var event 1 |E event_error_vswitch3 $end
-$var event 1 }E event_error_vswitch2 $end
-$var event 1 ~E event_error_vswitch1 $end
-$var event 1 !F event_error_vddio_q2 $end
-$var event 1 "F event_error_vddio_q1 $end
-$var event 1 #F event_error_vdda_vddioq_vswitch2 $end
-$var event 1 $F event_error_vdda3 $end
-$var event 1 %F event_error_vdda2 $end
-$var event 1 &F event_error_vdda $end
-$var event 1 'F event_error_supply_good $end
-$var event 1 (F event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ! ANALOG_EN $end
-$var wire 1 ! ANALOG_POL $end
-$var wire 1 ! ANALOG_SEL $end
-$var wire 3 )F DM [2:0] $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 * HLD_H_N $end
-$var wire 1 ! HLD_OVR $end
-$var wire 1 ! IB_MODE_SEL $end
-$var wire 1 & PAD $end
-$var wire 1 uE PAD_A_ESD_0_H $end
-$var wire 1 vE PAD_A_ESD_1_H $end
-$var wire 1 wE PAD_A_NOESD_H $end
-$var wire 1 ! SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 ! VTRIP_SEL $end
-$var wire 3 *F dm_buf [2:0] $end
-$var wire 1 +F error_enable_vddio $end
-$var wire 1 ,F error_supply_good $end
-$var wire 1 -F error_vdda $end
-$var wire 1 .F error_vdda2 $end
-$var wire 1 /F error_vdda3 $end
-$var wire 1 0F error_vdda_vddioq_vswitch2 $end
-$var wire 1 1F error_vddio_q1 $end
-$var wire 1 2F error_vddio_q2 $end
-$var wire 1 3F error_vswitch1 $end
-$var wire 1 4F error_vswitch2 $end
-$var wire 1 5F error_vswitch3 $end
-$var wire 1 6F error_vswitch4 $end
-$var wire 1 7F error_vswitch5 $end
-$var wire 1 8F functional_mode_amux $end
-$var wire 1 9F hld_h_n_buf $end
-$var wire 1 :F hld_ovr_buf $end
-$var wire 1 ;F ib_mode_sel_buf $end
-$var wire 1 <F inp_dis_buf $end
-$var wire 1 =F invalid_controls_amux $end
-$var wire 1 >F oe_n_buf $end
-$var wire 1 ?F out_buf $end
-$var wire 1 @F pad_tristate $end
-$var wire 1 AF pwr_good_active_mode $end
-$var wire 1 BF pwr_good_active_mode_vdda $end
-$var wire 1 CF pwr_good_amux $end
-$var wire 1 DF pwr_good_analog_en_vdda $end
-$var wire 1 EF pwr_good_analog_en_vddio_q $end
-$var wire 1 FF pwr_good_analog_en_vswitch $end
-$var wire 1 GF pwr_good_hold_mode $end
-$var wire 1 HF pwr_good_hold_mode_vdda $end
-$var wire 1 IF pwr_good_hold_ovr_mode $end
-$var wire 1 JF pwr_good_inpbuff_hv $end
-$var wire 1 KF pwr_good_inpbuff_lv $end
-$var wire 1 LF pwr_good_output_driver $end
-$var wire 1 MF slow_buf $end
-$var wire 1 NF vtrip_sel_buf $end
-$var wire 1 OF x_on_analog_en_vdda $end
-$var wire 1 PF x_on_analog_en_vddio_q $end
-$var wire 1 QF x_on_analog_en_vswitch $end
-$var wire 1 RF x_on_in_hv $end
-$var wire 1 SF x_on_in_lv $end
-$var wire 1 TF x_on_pad $end
-$var wire 1 UF zero_on_analog_en_vdda $end
-$var wire 1 VF zero_on_analog_en_vddio_q $end
-$var wire 1 WF zero_on_analog_en_vswitch $end
-$var wire 1 XF pwr_good_amux_vccd $end
-$var wire 1 YF enable_pad_vssio_q $end
-$var wire 1 ZF enable_pad_vddio_q $end
-$var wire 1 [F enable_pad_amuxbus_b $end
-$var wire 1 \F enable_pad_amuxbus_a $end
-$var wire 1 ]F disable_inp_buff_lv $end
-$var wire 1 ^F disable_inp_buff $end
-$var wire 3 _F amux_select [2:0] $end
-$var wire 1 m? TIE_LO_ESD $end
-$var wire 1 xE TIE_HI_ESD $end
-$var wire 1 0" OUT $end
-$var wire 1 /" OE_N $end
-$var wire 1 yE IN_H $end
-$var wire 1 3" INP_DIS $end
-$var wire 1 4" IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var wire 1 m? ENABLE_INP_H $end
-$var wire 1 h ENABLE_H $end
-$var reg 1 `F analog_en_final $end
-$var reg 1 aF analog_en_vdda $end
-$var reg 1 bF analog_en_vddio_q $end
-$var reg 1 cF analog_en_vswitch $end
-$var reg 1 dF dis_err_msgs $end
-$var reg 3 eF dm_final [2:0] $end
-$var reg 1 fF hld_ovr_final $end
-$var reg 1 gF ib_mode_sel_final $end
-$var reg 1 hF inp_dis_final $end
-$var reg 1 iF notifier_dm $end
-$var reg 1 jF notifier_enable_h $end
-$var reg 1 kF notifier_hld_ovr $end
-$var reg 1 lF notifier_ib_mode_sel $end
-$var reg 1 mF notifier_inp_dis $end
-$var reg 1 nF notifier_oe_n $end
-$var reg 1 oF notifier_out $end
-$var reg 1 pF notifier_slow $end
-$var reg 1 qF notifier_vtrip_sel $end
-$var reg 1 rF oe_n_final $end
-$var reg 1 sF out_final $end
-$var reg 1 tF slow_final $end
-$var reg 1 uF vtrip_sel_final $end
-$var integer 32 vF msg_count_pad [31:0] $end
-$var integer 32 wF msg_count_pad1 [31:0] $end
-$var integer 32 xF msg_count_pad10 [31:0] $end
-$var integer 32 yF msg_count_pad11 [31:0] $end
-$var integer 32 zF msg_count_pad12 [31:0] $end
-$var integer 32 {F msg_count_pad2 [31:0] $end
-$var integer 32 |F msg_count_pad3 [31:0] $end
-$var integer 32 }F msg_count_pad4 [31:0] $end
-$var integer 32 ~F msg_count_pad5 [31:0] $end
-$var integer 32 !G msg_count_pad6 [31:0] $end
-$var integer 32 "G msg_count_pad7 [31:0] $end
-$var integer 32 #G msg_count_pad8 [31:0] $end
-$var integer 32 $G msg_count_pad9 [31:0] $end
-$var integer 32 %G slow_0_delay [31:0] $end
-$var integer 32 &G slow_1_delay [31:0] $end
-$var integer 32 'G slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module mgmt_corner[0] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$upscope $end
-$scope module mgmt_corner[1] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$upscope $end
-$scope module mgmt_vccd_lvclamp_pad $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ! BDY2_B2B $end
-$var wire 1 + DRN_LVC1 $end
-$var wire 1 + DRN_LVC2 $end
-$var wire 1 ! SRC_BDY_LVC1 $end
-$var wire 1 ! SRC_BDY_LVC2 $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$scope module sky130_fd_io__top_power_lvc_base $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ! BDY2_B2B $end
-$var wire 1 + DRN_LVC1 $end
-$var wire 1 + DRN_LVC2 $end
-$var wire 1 (G OGC_LVC $end
-$var wire 1 )G P_CORE $end
-$var wire 1 + P_PAD $end
-$var wire 1 ! SRC_BDY_LVC1 $end
-$var wire 1 ! SRC_BDY_LVC2 $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$upscope $end
-$upscope $end
-$scope module mgmt_vdda_hvclamp_pad $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 * DRN_HVC $end
-$var wire 1 ! SRC_BDY_HVC $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$scope module sky130_fd_io__top_power_hvc_base $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 * DRN_HVC $end
-$var wire 1 *G OGC_HVC $end
-$var wire 1 +G P_CORE $end
-$var wire 1 * P_PAD $end
-$var wire 1 ! SRC_BDY_HVC $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$upscope $end
-$upscope $end
-$scope module mgmt_vddio_hvclamp_pad[0] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 * DRN_HVC $end
-$var wire 1 ! SRC_BDY_HVC $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$scope module sky130_fd_io__top_power_hvc_base $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 * DRN_HVC $end
-$var wire 1 ,G OGC_HVC $end
-$var wire 1 -G P_CORE $end
-$var wire 1 * P_PAD $end
-$var wire 1 ! SRC_BDY_HVC $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$upscope $end
-$upscope $end
-$scope module mgmt_vddio_hvclamp_pad[1] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 * DRN_HVC $end
-$var wire 1 ! SRC_BDY_HVC $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$scope module sky130_fd_io__top_power_hvc_base $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 * DRN_HVC $end
-$var wire 1 .G OGC_HVC $end
-$var wire 1 /G P_CORE $end
-$var wire 1 * P_PAD $end
-$var wire 1 ! SRC_BDY_HVC $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$upscope $end
-$upscope $end
-$scope module mgmt_vssa_hvclamp_pad $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 * DRN_HVC $end
-$var wire 1 ! SRC_BDY_HVC $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$scope module sky130_fd_io__top_ground_hvc_base $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 * DRN_HVC $end
-$var wire 1 0G G_CORE $end
-$var wire 1 ! G_PAD $end
-$var wire 1 1G OGC_HVC $end
-$var wire 1 ! SRC_BDY_HVC $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$upscope $end
-$upscope $end
-$scope module mgmt_vssd_lvclmap_pad $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ! BDY2_B2B $end
-$var wire 1 + DRN_LVC1 $end
-$var wire 1 + DRN_LVC2 $end
-$var wire 1 ! SRC_BDY_LVC1 $end
-$var wire 1 ! SRC_BDY_LVC2 $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$scope module sky130_fd_io__top_ground_lvc_base $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ! BDY2_B2B $end
-$var wire 1 + DRN_LVC1 $end
-$var wire 1 + DRN_LVC2 $end
-$var wire 1 2G G_CORE $end
-$var wire 1 ! G_PAD $end
-$var wire 1 3G OGC_LVC $end
-$var wire 1 ! SRC_BDY_LVC1 $end
-$var wire 1 ! SRC_BDY_LVC2 $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$upscope $end
-$upscope $end
-$scope module mgmt_vssio_hvclamp_pad[0] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 * DRN_HVC $end
-$var wire 1 ! SRC_BDY_HVC $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$scope module sky130_fd_io__top_ground_hvc_base $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 * DRN_HVC $end
-$var wire 1 4G G_CORE $end
-$var wire 1 ! G_PAD $end
-$var wire 1 5G OGC_HVC $end
-$var wire 1 ! SRC_BDY_HVC $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$upscope $end
-$upscope $end
-$scope module mgmt_vssio_hvclamp_pad[1] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 * DRN_HVC $end
-$var wire 1 ! SRC_BDY_HVC $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$scope module sky130_fd_io__top_ground_hvc_base $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 * DRN_HVC $end
-$var wire 1 6G G_CORE $end
-$var wire 1 ! G_PAD $end
-$var wire 1 7G OGC_HVC $end
-$var wire 1 ! SRC_BDY_HVC $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$upscope $end
-$upscope $end
-$scope module mprj_pads $end
-$var wire 1 X? analog_a $end
-$var wire 1 Y? analog_b $end
-$var wire 37 8G analog_en [36:0] $end
-$var wire 37 9G analog_pol [36:0] $end
-$var wire 37 :G analog_sel [36:0] $end
-$var wire 111 ;G dm [110:0] $end
-$var wire 37 <G enh [36:0] $end
-$var wire 37 =G hldh_n [36:0] $end
-$var wire 37 >G holdover [36:0] $end
-$var wire 37 ?G ib_mode_sel [36:0] $end
-$var wire 37 @G inp_dis [36:0] $end
-$var wire 37 AG io [36:0] $end
-$var wire 37 BG io_out [36:0] $end
-$var wire 37 CG oeb [36:0] $end
-$var wire 1 h? por $end
-$var wire 37 DG slow_sel [36:0] $end
-$var wire 1 + vccd $end
-$var wire 1 + vccd1 $end
-$var wire 1 + vccd2 $end
-$var wire 1 EG vdda $end
-$var wire 1 * vdda1 $end
-$var wire 1 * vdda2 $end
-$var wire 1 * vddio $end
-$var wire 1 i? vddio_q $end
-$var wire 1 FG vssa $end
-$var wire 1 ! vssa1 $end
-$var wire 1 ! vssa2 $end
-$var wire 1 ! vssd $end
-$var wire 1 ! vssd1 $end
-$var wire 1 ! vssd2 $end
-$var wire 1 ! vssio $end
-$var wire 1 j? vssio_q $end
-$var wire 37 GG vtrip_sel [36:0] $end
-$var wire 1 h porb_h $end
-$var wire 37 HG loop1_io [36:0] $end
-$var wire 37 IG io_in [36:0] $end
-$scope module area1_io_pad[0] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 JG ANALOG_EN $end
-$var wire 1 KG ANALOG_POL $end
-$var wire 1 LG ANALOG_SEL $end
-$var wire 3 MG DM [2:0] $end
-$var wire 1 NG ENABLE_H $end
-$var wire 1 OG ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 PG HLD_H_N $end
-$var wire 1 QG HLD_OVR $end
-$var wire 1 RG IB_MODE_SEL $end
-$var wire 1 SG INP_DIS $end
-$var wire 1 TG OE_N $end
-$var wire 1 UG OUT $end
-$var wire 1 VG PAD $end
-$var wire 1 WG PAD_A_ESD_0_H $end
-$var wire 1 XG PAD_A_ESD_1_H $end
-$var wire 1 YG PAD_A_NOESD_H $end
-$var wire 1 ZG SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 [G VTRIP_SEL $end
-$var wire 1 \G TIE_LO_ESD $end
-$var wire 1 ]G TIE_HI_ESD $end
-$var wire 1 ^G IN_H $end
-$var wire 1 _G IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 `G event_error_vswitch5 $end
-$var event 1 aG event_error_vswitch4 $end
-$var event 1 bG event_error_vswitch3 $end
-$var event 1 cG event_error_vswitch2 $end
-$var event 1 dG event_error_vswitch1 $end
-$var event 1 eG event_error_vddio_q2 $end
-$var event 1 fG event_error_vddio_q1 $end
-$var event 1 gG event_error_vdda_vddioq_vswitch2 $end
-$var event 1 hG event_error_vdda3 $end
-$var event 1 iG event_error_vdda2 $end
-$var event 1 jG event_error_vdda $end
-$var event 1 kG event_error_supply_good $end
-$var event 1 lG event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 JG ANALOG_EN $end
-$var wire 1 KG ANALOG_POL $end
-$var wire 1 LG ANALOG_SEL $end
-$var wire 3 mG DM [2:0] $end
-$var wire 1 NG ENABLE_H $end
-$var wire 1 OG ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 PG HLD_H_N $end
-$var wire 1 QG HLD_OVR $end
-$var wire 1 RG IB_MODE_SEL $end
-$var wire 1 SG INP_DIS $end
-$var wire 1 TG OE_N $end
-$var wire 1 UG OUT $end
-$var wire 1 VG PAD $end
-$var wire 1 WG PAD_A_ESD_0_H $end
-$var wire 1 XG PAD_A_ESD_1_H $end
-$var wire 1 YG PAD_A_NOESD_H $end
-$var wire 1 ZG SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 [G VTRIP_SEL $end
-$var wire 3 nG dm_buf [2:0] $end
-$var wire 1 oG error_enable_vddio $end
-$var wire 1 pG error_supply_good $end
-$var wire 1 qG error_vdda $end
-$var wire 1 rG error_vdda2 $end
-$var wire 1 sG error_vdda3 $end
-$var wire 1 tG error_vdda_vddioq_vswitch2 $end
-$var wire 1 uG error_vddio_q1 $end
-$var wire 1 vG error_vddio_q2 $end
-$var wire 1 wG error_vswitch1 $end
-$var wire 1 xG error_vswitch2 $end
-$var wire 1 yG error_vswitch3 $end
-$var wire 1 zG error_vswitch4 $end
-$var wire 1 {G error_vswitch5 $end
-$var wire 1 |G functional_mode_amux $end
-$var wire 1 }G hld_h_n_buf $end
-$var wire 1 ~G hld_ovr_buf $end
-$var wire 1 !H ib_mode_sel_buf $end
-$var wire 1 "H inp_dis_buf $end
-$var wire 1 #H invalid_controls_amux $end
-$var wire 1 $H oe_n_buf $end
-$var wire 1 %H out_buf $end
-$var wire 1 &H pad_tristate $end
-$var wire 1 'H pwr_good_active_mode $end
-$var wire 1 (H pwr_good_active_mode_vdda $end
-$var wire 1 )H pwr_good_amux $end
-$var wire 1 *H pwr_good_analog_en_vdda $end
-$var wire 1 +H pwr_good_analog_en_vddio_q $end
-$var wire 1 ,H pwr_good_analog_en_vswitch $end
-$var wire 1 -H pwr_good_hold_mode $end
-$var wire 1 .H pwr_good_hold_mode_vdda $end
-$var wire 1 /H pwr_good_hold_ovr_mode $end
-$var wire 1 0H pwr_good_inpbuff_hv $end
-$var wire 1 1H pwr_good_inpbuff_lv $end
-$var wire 1 2H pwr_good_output_driver $end
-$var wire 1 3H slow_buf $end
-$var wire 1 4H vtrip_sel_buf $end
-$var wire 1 5H x_on_analog_en_vdda $end
-$var wire 1 6H x_on_analog_en_vddio_q $end
-$var wire 1 7H x_on_analog_en_vswitch $end
-$var wire 1 8H x_on_in_hv $end
-$var wire 1 9H x_on_in_lv $end
-$var wire 1 :H x_on_pad $end
-$var wire 1 ;H zero_on_analog_en_vdda $end
-$var wire 1 <H zero_on_analog_en_vddio_q $end
-$var wire 1 =H zero_on_analog_en_vswitch $end
-$var wire 1 >H pwr_good_amux_vccd $end
-$var wire 1 ?H enable_pad_vssio_q $end
-$var wire 1 @H enable_pad_vddio_q $end
-$var wire 1 AH enable_pad_amuxbus_b $end
-$var wire 1 BH enable_pad_amuxbus_a $end
-$var wire 1 CH disable_inp_buff_lv $end
-$var wire 1 DH disable_inp_buff $end
-$var wire 3 EH amux_select [2:0] $end
-$var wire 1 \G TIE_LO_ESD $end
-$var wire 1 ]G TIE_HI_ESD $end
-$var wire 1 ^G IN_H $end
-$var wire 1 _G IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 FH analog_en_final $end
-$var reg 1 GH analog_en_vdda $end
-$var reg 1 HH analog_en_vddio_q $end
-$var reg 1 IH analog_en_vswitch $end
-$var reg 1 JH dis_err_msgs $end
-$var reg 3 KH dm_final [2:0] $end
-$var reg 1 LH hld_ovr_final $end
-$var reg 1 MH ib_mode_sel_final $end
-$var reg 1 NH inp_dis_final $end
-$var reg 1 OH notifier_dm $end
-$var reg 1 PH notifier_enable_h $end
-$var reg 1 QH notifier_hld_ovr $end
-$var reg 1 RH notifier_ib_mode_sel $end
-$var reg 1 SH notifier_inp_dis $end
-$var reg 1 TH notifier_oe_n $end
-$var reg 1 UH notifier_out $end
-$var reg 1 VH notifier_slow $end
-$var reg 1 WH notifier_vtrip_sel $end
-$var reg 1 XH oe_n_final $end
-$var reg 1 YH out_final $end
-$var reg 1 ZH slow_final $end
-$var reg 1 [H vtrip_sel_final $end
-$var integer 32 \H msg_count_pad [31:0] $end
-$var integer 32 ]H msg_count_pad1 [31:0] $end
-$var integer 32 ^H msg_count_pad10 [31:0] $end
-$var integer 32 _H msg_count_pad11 [31:0] $end
-$var integer 32 `H msg_count_pad12 [31:0] $end
-$var integer 32 aH msg_count_pad2 [31:0] $end
-$var integer 32 bH msg_count_pad3 [31:0] $end
-$var integer 32 cH msg_count_pad4 [31:0] $end
-$var integer 32 dH msg_count_pad5 [31:0] $end
-$var integer 32 eH msg_count_pad6 [31:0] $end
-$var integer 32 fH msg_count_pad7 [31:0] $end
-$var integer 32 gH msg_count_pad8 [31:0] $end
-$var integer 32 hH msg_count_pad9 [31:0] $end
-$var integer 32 iH slow_0_delay [31:0] $end
-$var integer 32 jH slow_1_delay [31:0] $end
-$var integer 32 kH slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area1_io_pad[1] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 lH ANALOG_EN $end
-$var wire 1 mH ANALOG_POL $end
-$var wire 1 nH ANALOG_SEL $end
-$var wire 3 oH DM [2:0] $end
-$var wire 1 pH ENABLE_H $end
-$var wire 1 qH ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 rH HLD_H_N $end
-$var wire 1 sH HLD_OVR $end
-$var wire 1 tH IB_MODE_SEL $end
-$var wire 1 uH INP_DIS $end
-$var wire 1 vH OE_N $end
-$var wire 1 wH OUT $end
-$var wire 1 xH PAD $end
-$var wire 1 yH PAD_A_ESD_0_H $end
-$var wire 1 zH PAD_A_ESD_1_H $end
-$var wire 1 {H PAD_A_NOESD_H $end
-$var wire 1 |H SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 }H VTRIP_SEL $end
-$var wire 1 ~H TIE_LO_ESD $end
-$var wire 1 !I TIE_HI_ESD $end
-$var wire 1 "I IN_H $end
-$var wire 1 #I IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 $I event_error_vswitch5 $end
-$var event 1 %I event_error_vswitch4 $end
-$var event 1 &I event_error_vswitch3 $end
-$var event 1 'I event_error_vswitch2 $end
-$var event 1 (I event_error_vswitch1 $end
-$var event 1 )I event_error_vddio_q2 $end
-$var event 1 *I event_error_vddio_q1 $end
-$var event 1 +I event_error_vdda_vddioq_vswitch2 $end
-$var event 1 ,I event_error_vdda3 $end
-$var event 1 -I event_error_vdda2 $end
-$var event 1 .I event_error_vdda $end
-$var event 1 /I event_error_supply_good $end
-$var event 1 0I event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 lH ANALOG_EN $end
-$var wire 1 mH ANALOG_POL $end
-$var wire 1 nH ANALOG_SEL $end
-$var wire 3 1I DM [2:0] $end
-$var wire 1 pH ENABLE_H $end
-$var wire 1 qH ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 rH HLD_H_N $end
-$var wire 1 sH HLD_OVR $end
-$var wire 1 tH IB_MODE_SEL $end
-$var wire 1 uH INP_DIS $end
-$var wire 1 vH OE_N $end
-$var wire 1 wH OUT $end
-$var wire 1 xH PAD $end
-$var wire 1 yH PAD_A_ESD_0_H $end
-$var wire 1 zH PAD_A_ESD_1_H $end
-$var wire 1 {H PAD_A_NOESD_H $end
-$var wire 1 |H SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 }H VTRIP_SEL $end
-$var wire 3 2I dm_buf [2:0] $end
-$var wire 1 3I error_enable_vddio $end
-$var wire 1 4I error_supply_good $end
-$var wire 1 5I error_vdda $end
-$var wire 1 6I error_vdda2 $end
-$var wire 1 7I error_vdda3 $end
-$var wire 1 8I error_vdda_vddioq_vswitch2 $end
-$var wire 1 9I error_vddio_q1 $end
-$var wire 1 :I error_vddio_q2 $end
-$var wire 1 ;I error_vswitch1 $end
-$var wire 1 <I error_vswitch2 $end
-$var wire 1 =I error_vswitch3 $end
-$var wire 1 >I error_vswitch4 $end
-$var wire 1 ?I error_vswitch5 $end
-$var wire 1 @I functional_mode_amux $end
-$var wire 1 AI hld_h_n_buf $end
-$var wire 1 BI hld_ovr_buf $end
-$var wire 1 CI ib_mode_sel_buf $end
-$var wire 1 DI inp_dis_buf $end
-$var wire 1 EI invalid_controls_amux $end
-$var wire 1 FI oe_n_buf $end
-$var wire 1 GI out_buf $end
-$var wire 1 HI pad_tristate $end
-$var wire 1 II pwr_good_active_mode $end
-$var wire 1 JI pwr_good_active_mode_vdda $end
-$var wire 1 KI pwr_good_amux $end
-$var wire 1 LI pwr_good_analog_en_vdda $end
-$var wire 1 MI pwr_good_analog_en_vddio_q $end
-$var wire 1 NI pwr_good_analog_en_vswitch $end
-$var wire 1 OI pwr_good_hold_mode $end
-$var wire 1 PI pwr_good_hold_mode_vdda $end
-$var wire 1 QI pwr_good_hold_ovr_mode $end
-$var wire 1 RI pwr_good_inpbuff_hv $end
-$var wire 1 SI pwr_good_inpbuff_lv $end
-$var wire 1 TI pwr_good_output_driver $end
-$var wire 1 UI slow_buf $end
-$var wire 1 VI vtrip_sel_buf $end
-$var wire 1 WI x_on_analog_en_vdda $end
-$var wire 1 XI x_on_analog_en_vddio_q $end
-$var wire 1 YI x_on_analog_en_vswitch $end
-$var wire 1 ZI x_on_in_hv $end
-$var wire 1 [I x_on_in_lv $end
-$var wire 1 \I x_on_pad $end
-$var wire 1 ]I zero_on_analog_en_vdda $end
-$var wire 1 ^I zero_on_analog_en_vddio_q $end
-$var wire 1 _I zero_on_analog_en_vswitch $end
-$var wire 1 `I pwr_good_amux_vccd $end
-$var wire 1 aI enable_pad_vssio_q $end
-$var wire 1 bI enable_pad_vddio_q $end
-$var wire 1 cI enable_pad_amuxbus_b $end
-$var wire 1 dI enable_pad_amuxbus_a $end
-$var wire 1 eI disable_inp_buff_lv $end
-$var wire 1 fI disable_inp_buff $end
-$var wire 3 gI amux_select [2:0] $end
-$var wire 1 ~H TIE_LO_ESD $end
-$var wire 1 !I TIE_HI_ESD $end
-$var wire 1 "I IN_H $end
-$var wire 1 #I IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 hI analog_en_final $end
-$var reg 1 iI analog_en_vdda $end
-$var reg 1 jI analog_en_vddio_q $end
-$var reg 1 kI analog_en_vswitch $end
-$var reg 1 lI dis_err_msgs $end
-$var reg 3 mI dm_final [2:0] $end
-$var reg 1 nI hld_ovr_final $end
-$var reg 1 oI ib_mode_sel_final $end
-$var reg 1 pI inp_dis_final $end
-$var reg 1 qI notifier_dm $end
-$var reg 1 rI notifier_enable_h $end
-$var reg 1 sI notifier_hld_ovr $end
-$var reg 1 tI notifier_ib_mode_sel $end
-$var reg 1 uI notifier_inp_dis $end
-$var reg 1 vI notifier_oe_n $end
-$var reg 1 wI notifier_out $end
-$var reg 1 xI notifier_slow $end
-$var reg 1 yI notifier_vtrip_sel $end
-$var reg 1 zI oe_n_final $end
-$var reg 1 {I out_final $end
-$var reg 1 |I slow_final $end
-$var reg 1 }I vtrip_sel_final $end
-$var integer 32 ~I msg_count_pad [31:0] $end
-$var integer 32 !J msg_count_pad1 [31:0] $end
-$var integer 32 "J msg_count_pad10 [31:0] $end
-$var integer 32 #J msg_count_pad11 [31:0] $end
-$var integer 32 $J msg_count_pad12 [31:0] $end
-$var integer 32 %J msg_count_pad2 [31:0] $end
-$var integer 32 &J msg_count_pad3 [31:0] $end
-$var integer 32 'J msg_count_pad4 [31:0] $end
-$var integer 32 (J msg_count_pad5 [31:0] $end
-$var integer 32 )J msg_count_pad6 [31:0] $end
-$var integer 32 *J msg_count_pad7 [31:0] $end
-$var integer 32 +J msg_count_pad8 [31:0] $end
-$var integer 32 ,J msg_count_pad9 [31:0] $end
-$var integer 32 -J slow_0_delay [31:0] $end
-$var integer 32 .J slow_1_delay [31:0] $end
-$var integer 32 /J slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area1_io_pad[2] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 0J ANALOG_EN $end
-$var wire 1 1J ANALOG_POL $end
-$var wire 1 2J ANALOG_SEL $end
-$var wire 3 3J DM [2:0] $end
-$var wire 1 4J ENABLE_H $end
-$var wire 1 5J ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 6J HLD_H_N $end
-$var wire 1 7J HLD_OVR $end
-$var wire 1 8J IB_MODE_SEL $end
-$var wire 1 9J INP_DIS $end
-$var wire 1 :J OE_N $end
-$var wire 1 ;J OUT $end
-$var wire 1 <J PAD $end
-$var wire 1 =J PAD_A_ESD_0_H $end
-$var wire 1 >J PAD_A_ESD_1_H $end
-$var wire 1 ?J PAD_A_NOESD_H $end
-$var wire 1 @J SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 AJ VTRIP_SEL $end
-$var wire 1 BJ TIE_LO_ESD $end
-$var wire 1 CJ TIE_HI_ESD $end
-$var wire 1 DJ IN_H $end
-$var wire 1 EJ IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 FJ event_error_vswitch5 $end
-$var event 1 GJ event_error_vswitch4 $end
-$var event 1 HJ event_error_vswitch3 $end
-$var event 1 IJ event_error_vswitch2 $end
-$var event 1 JJ event_error_vswitch1 $end
-$var event 1 KJ event_error_vddio_q2 $end
-$var event 1 LJ event_error_vddio_q1 $end
-$var event 1 MJ event_error_vdda_vddioq_vswitch2 $end
-$var event 1 NJ event_error_vdda3 $end
-$var event 1 OJ event_error_vdda2 $end
-$var event 1 PJ event_error_vdda $end
-$var event 1 QJ event_error_supply_good $end
-$var event 1 RJ event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 0J ANALOG_EN $end
-$var wire 1 1J ANALOG_POL $end
-$var wire 1 2J ANALOG_SEL $end
-$var wire 3 SJ DM [2:0] $end
-$var wire 1 4J ENABLE_H $end
-$var wire 1 5J ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 6J HLD_H_N $end
-$var wire 1 7J HLD_OVR $end
-$var wire 1 8J IB_MODE_SEL $end
-$var wire 1 9J INP_DIS $end
-$var wire 1 :J OE_N $end
-$var wire 1 ;J OUT $end
-$var wire 1 <J PAD $end
-$var wire 1 =J PAD_A_ESD_0_H $end
-$var wire 1 >J PAD_A_ESD_1_H $end
-$var wire 1 ?J PAD_A_NOESD_H $end
-$var wire 1 @J SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 AJ VTRIP_SEL $end
-$var wire 3 TJ dm_buf [2:0] $end
-$var wire 1 UJ error_enable_vddio $end
-$var wire 1 VJ error_supply_good $end
-$var wire 1 WJ error_vdda $end
-$var wire 1 XJ error_vdda2 $end
-$var wire 1 YJ error_vdda3 $end
-$var wire 1 ZJ error_vdda_vddioq_vswitch2 $end
-$var wire 1 [J error_vddio_q1 $end
-$var wire 1 \J error_vddio_q2 $end
-$var wire 1 ]J error_vswitch1 $end
-$var wire 1 ^J error_vswitch2 $end
-$var wire 1 _J error_vswitch3 $end
-$var wire 1 `J error_vswitch4 $end
-$var wire 1 aJ error_vswitch5 $end
-$var wire 1 bJ functional_mode_amux $end
-$var wire 1 cJ hld_h_n_buf $end
-$var wire 1 dJ hld_ovr_buf $end
-$var wire 1 eJ ib_mode_sel_buf $end
-$var wire 1 fJ inp_dis_buf $end
-$var wire 1 gJ invalid_controls_amux $end
-$var wire 1 hJ oe_n_buf $end
-$var wire 1 iJ out_buf $end
-$var wire 1 jJ pad_tristate $end
-$var wire 1 kJ pwr_good_active_mode $end
-$var wire 1 lJ pwr_good_active_mode_vdda $end
-$var wire 1 mJ pwr_good_amux $end
-$var wire 1 nJ pwr_good_analog_en_vdda $end
-$var wire 1 oJ pwr_good_analog_en_vddio_q $end
-$var wire 1 pJ pwr_good_analog_en_vswitch $end
-$var wire 1 qJ pwr_good_hold_mode $end
-$var wire 1 rJ pwr_good_hold_mode_vdda $end
-$var wire 1 sJ pwr_good_hold_ovr_mode $end
-$var wire 1 tJ pwr_good_inpbuff_hv $end
-$var wire 1 uJ pwr_good_inpbuff_lv $end
-$var wire 1 vJ pwr_good_output_driver $end
-$var wire 1 wJ slow_buf $end
-$var wire 1 xJ vtrip_sel_buf $end
-$var wire 1 yJ x_on_analog_en_vdda $end
-$var wire 1 zJ x_on_analog_en_vddio_q $end
-$var wire 1 {J x_on_analog_en_vswitch $end
-$var wire 1 |J x_on_in_hv $end
-$var wire 1 }J x_on_in_lv $end
-$var wire 1 ~J x_on_pad $end
-$var wire 1 !K zero_on_analog_en_vdda $end
-$var wire 1 "K zero_on_analog_en_vddio_q $end
-$var wire 1 #K zero_on_analog_en_vswitch $end
-$var wire 1 $K pwr_good_amux_vccd $end
-$var wire 1 %K enable_pad_vssio_q $end
-$var wire 1 &K enable_pad_vddio_q $end
-$var wire 1 'K enable_pad_amuxbus_b $end
-$var wire 1 (K enable_pad_amuxbus_a $end
-$var wire 1 )K disable_inp_buff_lv $end
-$var wire 1 *K disable_inp_buff $end
-$var wire 3 +K amux_select [2:0] $end
-$var wire 1 BJ TIE_LO_ESD $end
-$var wire 1 CJ TIE_HI_ESD $end
-$var wire 1 DJ IN_H $end
-$var wire 1 EJ IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 ,K analog_en_final $end
-$var reg 1 -K analog_en_vdda $end
-$var reg 1 .K analog_en_vddio_q $end
-$var reg 1 /K analog_en_vswitch $end
-$var reg 1 0K dis_err_msgs $end
-$var reg 3 1K dm_final [2:0] $end
-$var reg 1 2K hld_ovr_final $end
-$var reg 1 3K ib_mode_sel_final $end
-$var reg 1 4K inp_dis_final $end
-$var reg 1 5K notifier_dm $end
-$var reg 1 6K notifier_enable_h $end
-$var reg 1 7K notifier_hld_ovr $end
-$var reg 1 8K notifier_ib_mode_sel $end
-$var reg 1 9K notifier_inp_dis $end
-$var reg 1 :K notifier_oe_n $end
-$var reg 1 ;K notifier_out $end
-$var reg 1 <K notifier_slow $end
-$var reg 1 =K notifier_vtrip_sel $end
-$var reg 1 >K oe_n_final $end
-$var reg 1 ?K out_final $end
-$var reg 1 @K slow_final $end
-$var reg 1 AK vtrip_sel_final $end
-$var integer 32 BK msg_count_pad [31:0] $end
-$var integer 32 CK msg_count_pad1 [31:0] $end
-$var integer 32 DK msg_count_pad10 [31:0] $end
-$var integer 32 EK msg_count_pad11 [31:0] $end
-$var integer 32 FK msg_count_pad12 [31:0] $end
-$var integer 32 GK msg_count_pad2 [31:0] $end
-$var integer 32 HK msg_count_pad3 [31:0] $end
-$var integer 32 IK msg_count_pad4 [31:0] $end
-$var integer 32 JK msg_count_pad5 [31:0] $end
-$var integer 32 KK msg_count_pad6 [31:0] $end
-$var integer 32 LK msg_count_pad7 [31:0] $end
-$var integer 32 MK msg_count_pad8 [31:0] $end
-$var integer 32 NK msg_count_pad9 [31:0] $end
-$var integer 32 OK slow_0_delay [31:0] $end
-$var integer 32 PK slow_1_delay [31:0] $end
-$var integer 32 QK slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area1_io_pad[3] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 RK ANALOG_EN $end
-$var wire 1 SK ANALOG_POL $end
-$var wire 1 TK ANALOG_SEL $end
-$var wire 3 UK DM [2:0] $end
-$var wire 1 VK ENABLE_H $end
-$var wire 1 WK ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 XK HLD_H_N $end
-$var wire 1 YK HLD_OVR $end
-$var wire 1 ZK IB_MODE_SEL $end
-$var wire 1 [K INP_DIS $end
-$var wire 1 \K OE_N $end
-$var wire 1 ]K OUT $end
-$var wire 1 ^K PAD $end
-$var wire 1 _K PAD_A_ESD_0_H $end
-$var wire 1 `K PAD_A_ESD_1_H $end
-$var wire 1 aK PAD_A_NOESD_H $end
-$var wire 1 bK SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 cK VTRIP_SEL $end
-$var wire 1 dK TIE_LO_ESD $end
-$var wire 1 eK TIE_HI_ESD $end
-$var wire 1 fK IN_H $end
-$var wire 1 gK IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 hK event_error_vswitch5 $end
-$var event 1 iK event_error_vswitch4 $end
-$var event 1 jK event_error_vswitch3 $end
-$var event 1 kK event_error_vswitch2 $end
-$var event 1 lK event_error_vswitch1 $end
-$var event 1 mK event_error_vddio_q2 $end
-$var event 1 nK event_error_vddio_q1 $end
-$var event 1 oK event_error_vdda_vddioq_vswitch2 $end
-$var event 1 pK event_error_vdda3 $end
-$var event 1 qK event_error_vdda2 $end
-$var event 1 rK event_error_vdda $end
-$var event 1 sK event_error_supply_good $end
-$var event 1 tK event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 RK ANALOG_EN $end
-$var wire 1 SK ANALOG_POL $end
-$var wire 1 TK ANALOG_SEL $end
-$var wire 3 uK DM [2:0] $end
-$var wire 1 VK ENABLE_H $end
-$var wire 1 WK ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 XK HLD_H_N $end
-$var wire 1 YK HLD_OVR $end
-$var wire 1 ZK IB_MODE_SEL $end
-$var wire 1 [K INP_DIS $end
-$var wire 1 \K OE_N $end
-$var wire 1 ]K OUT $end
-$var wire 1 ^K PAD $end
-$var wire 1 _K PAD_A_ESD_0_H $end
-$var wire 1 `K PAD_A_ESD_1_H $end
-$var wire 1 aK PAD_A_NOESD_H $end
-$var wire 1 bK SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 cK VTRIP_SEL $end
-$var wire 3 vK dm_buf [2:0] $end
-$var wire 1 wK error_enable_vddio $end
-$var wire 1 xK error_supply_good $end
-$var wire 1 yK error_vdda $end
-$var wire 1 zK error_vdda2 $end
-$var wire 1 {K error_vdda3 $end
-$var wire 1 |K error_vdda_vddioq_vswitch2 $end
-$var wire 1 }K error_vddio_q1 $end
-$var wire 1 ~K error_vddio_q2 $end
-$var wire 1 !L error_vswitch1 $end
-$var wire 1 "L error_vswitch2 $end
-$var wire 1 #L error_vswitch3 $end
-$var wire 1 $L error_vswitch4 $end
-$var wire 1 %L error_vswitch5 $end
-$var wire 1 &L functional_mode_amux $end
-$var wire 1 'L hld_h_n_buf $end
-$var wire 1 (L hld_ovr_buf $end
-$var wire 1 )L ib_mode_sel_buf $end
-$var wire 1 *L inp_dis_buf $end
-$var wire 1 +L invalid_controls_amux $end
-$var wire 1 ,L oe_n_buf $end
-$var wire 1 -L out_buf $end
-$var wire 1 .L pad_tristate $end
-$var wire 1 /L pwr_good_active_mode $end
-$var wire 1 0L pwr_good_active_mode_vdda $end
-$var wire 1 1L pwr_good_amux $end
-$var wire 1 2L pwr_good_analog_en_vdda $end
-$var wire 1 3L pwr_good_analog_en_vddio_q $end
-$var wire 1 4L pwr_good_analog_en_vswitch $end
-$var wire 1 5L pwr_good_hold_mode $end
-$var wire 1 6L pwr_good_hold_mode_vdda $end
-$var wire 1 7L pwr_good_hold_ovr_mode $end
-$var wire 1 8L pwr_good_inpbuff_hv $end
-$var wire 1 9L pwr_good_inpbuff_lv $end
-$var wire 1 :L pwr_good_output_driver $end
-$var wire 1 ;L slow_buf $end
-$var wire 1 <L vtrip_sel_buf $end
-$var wire 1 =L x_on_analog_en_vdda $end
-$var wire 1 >L x_on_analog_en_vddio_q $end
-$var wire 1 ?L x_on_analog_en_vswitch $end
-$var wire 1 @L x_on_in_hv $end
-$var wire 1 AL x_on_in_lv $end
-$var wire 1 BL x_on_pad $end
-$var wire 1 CL zero_on_analog_en_vdda $end
-$var wire 1 DL zero_on_analog_en_vddio_q $end
-$var wire 1 EL zero_on_analog_en_vswitch $end
-$var wire 1 FL pwr_good_amux_vccd $end
-$var wire 1 GL enable_pad_vssio_q $end
-$var wire 1 HL enable_pad_vddio_q $end
-$var wire 1 IL enable_pad_amuxbus_b $end
-$var wire 1 JL enable_pad_amuxbus_a $end
-$var wire 1 KL disable_inp_buff_lv $end
-$var wire 1 LL disable_inp_buff $end
-$var wire 3 ML amux_select [2:0] $end
-$var wire 1 dK TIE_LO_ESD $end
-$var wire 1 eK TIE_HI_ESD $end
-$var wire 1 fK IN_H $end
-$var wire 1 gK IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 NL analog_en_final $end
-$var reg 1 OL analog_en_vdda $end
-$var reg 1 PL analog_en_vddio_q $end
-$var reg 1 QL analog_en_vswitch $end
-$var reg 1 RL dis_err_msgs $end
-$var reg 3 SL dm_final [2:0] $end
-$var reg 1 TL hld_ovr_final $end
-$var reg 1 UL ib_mode_sel_final $end
-$var reg 1 VL inp_dis_final $end
-$var reg 1 WL notifier_dm $end
-$var reg 1 XL notifier_enable_h $end
-$var reg 1 YL notifier_hld_ovr $end
-$var reg 1 ZL notifier_ib_mode_sel $end
-$var reg 1 [L notifier_inp_dis $end
-$var reg 1 \L notifier_oe_n $end
-$var reg 1 ]L notifier_out $end
-$var reg 1 ^L notifier_slow $end
-$var reg 1 _L notifier_vtrip_sel $end
-$var reg 1 `L oe_n_final $end
-$var reg 1 aL out_final $end
-$var reg 1 bL slow_final $end
-$var reg 1 cL vtrip_sel_final $end
-$var integer 32 dL msg_count_pad [31:0] $end
-$var integer 32 eL msg_count_pad1 [31:0] $end
-$var integer 32 fL msg_count_pad10 [31:0] $end
-$var integer 32 gL msg_count_pad11 [31:0] $end
-$var integer 32 hL msg_count_pad12 [31:0] $end
-$var integer 32 iL msg_count_pad2 [31:0] $end
-$var integer 32 jL msg_count_pad3 [31:0] $end
-$var integer 32 kL msg_count_pad4 [31:0] $end
-$var integer 32 lL msg_count_pad5 [31:0] $end
-$var integer 32 mL msg_count_pad6 [31:0] $end
-$var integer 32 nL msg_count_pad7 [31:0] $end
-$var integer 32 oL msg_count_pad8 [31:0] $end
-$var integer 32 pL msg_count_pad9 [31:0] $end
-$var integer 32 qL slow_0_delay [31:0] $end
-$var integer 32 rL slow_1_delay [31:0] $end
-$var integer 32 sL slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area1_io_pad[4] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 tL ANALOG_EN $end
-$var wire 1 uL ANALOG_POL $end
-$var wire 1 vL ANALOG_SEL $end
-$var wire 3 wL DM [2:0] $end
-$var wire 1 xL ENABLE_H $end
-$var wire 1 yL ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 zL HLD_H_N $end
-$var wire 1 {L HLD_OVR $end
-$var wire 1 |L IB_MODE_SEL $end
-$var wire 1 }L INP_DIS $end
-$var wire 1 ~L OE_N $end
-$var wire 1 !M OUT $end
-$var wire 1 "M PAD $end
-$var wire 1 #M PAD_A_ESD_0_H $end
-$var wire 1 $M PAD_A_ESD_1_H $end
-$var wire 1 %M PAD_A_NOESD_H $end
-$var wire 1 &M SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 'M VTRIP_SEL $end
-$var wire 1 (M TIE_LO_ESD $end
-$var wire 1 )M TIE_HI_ESD $end
-$var wire 1 *M IN_H $end
-$var wire 1 +M IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 ,M event_error_vswitch5 $end
-$var event 1 -M event_error_vswitch4 $end
-$var event 1 .M event_error_vswitch3 $end
-$var event 1 /M event_error_vswitch2 $end
-$var event 1 0M event_error_vswitch1 $end
-$var event 1 1M event_error_vddio_q2 $end
-$var event 1 2M event_error_vddio_q1 $end
-$var event 1 3M event_error_vdda_vddioq_vswitch2 $end
-$var event 1 4M event_error_vdda3 $end
-$var event 1 5M event_error_vdda2 $end
-$var event 1 6M event_error_vdda $end
-$var event 1 7M event_error_supply_good $end
-$var event 1 8M event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 tL ANALOG_EN $end
-$var wire 1 uL ANALOG_POL $end
-$var wire 1 vL ANALOG_SEL $end
-$var wire 3 9M DM [2:0] $end
-$var wire 1 xL ENABLE_H $end
-$var wire 1 yL ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 zL HLD_H_N $end
-$var wire 1 {L HLD_OVR $end
-$var wire 1 |L IB_MODE_SEL $end
-$var wire 1 }L INP_DIS $end
-$var wire 1 ~L OE_N $end
-$var wire 1 !M OUT $end
-$var wire 1 "M PAD $end
-$var wire 1 #M PAD_A_ESD_0_H $end
-$var wire 1 $M PAD_A_ESD_1_H $end
-$var wire 1 %M PAD_A_NOESD_H $end
-$var wire 1 &M SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 'M VTRIP_SEL $end
-$var wire 3 :M dm_buf [2:0] $end
-$var wire 1 ;M error_enable_vddio $end
-$var wire 1 <M error_supply_good $end
-$var wire 1 =M error_vdda $end
-$var wire 1 >M error_vdda2 $end
-$var wire 1 ?M error_vdda3 $end
-$var wire 1 @M error_vdda_vddioq_vswitch2 $end
-$var wire 1 AM error_vddio_q1 $end
-$var wire 1 BM error_vddio_q2 $end
-$var wire 1 CM error_vswitch1 $end
-$var wire 1 DM error_vswitch2 $end
-$var wire 1 EM error_vswitch3 $end
-$var wire 1 FM error_vswitch4 $end
-$var wire 1 GM error_vswitch5 $end
-$var wire 1 HM functional_mode_amux $end
-$var wire 1 IM hld_h_n_buf $end
-$var wire 1 JM hld_ovr_buf $end
-$var wire 1 KM ib_mode_sel_buf $end
-$var wire 1 LM inp_dis_buf $end
-$var wire 1 MM invalid_controls_amux $end
-$var wire 1 NM oe_n_buf $end
-$var wire 1 OM out_buf $end
-$var wire 1 PM pad_tristate $end
-$var wire 1 QM pwr_good_active_mode $end
-$var wire 1 RM pwr_good_active_mode_vdda $end
-$var wire 1 SM pwr_good_amux $end
-$var wire 1 TM pwr_good_analog_en_vdda $end
-$var wire 1 UM pwr_good_analog_en_vddio_q $end
-$var wire 1 VM pwr_good_analog_en_vswitch $end
-$var wire 1 WM pwr_good_hold_mode $end
-$var wire 1 XM pwr_good_hold_mode_vdda $end
-$var wire 1 YM pwr_good_hold_ovr_mode $end
-$var wire 1 ZM pwr_good_inpbuff_hv $end
-$var wire 1 [M pwr_good_inpbuff_lv $end
-$var wire 1 \M pwr_good_output_driver $end
-$var wire 1 ]M slow_buf $end
-$var wire 1 ^M vtrip_sel_buf $end
-$var wire 1 _M x_on_analog_en_vdda $end
-$var wire 1 `M x_on_analog_en_vddio_q $end
-$var wire 1 aM x_on_analog_en_vswitch $end
-$var wire 1 bM x_on_in_hv $end
-$var wire 1 cM x_on_in_lv $end
-$var wire 1 dM x_on_pad $end
-$var wire 1 eM zero_on_analog_en_vdda $end
-$var wire 1 fM zero_on_analog_en_vddio_q $end
-$var wire 1 gM zero_on_analog_en_vswitch $end
-$var wire 1 hM pwr_good_amux_vccd $end
-$var wire 1 iM enable_pad_vssio_q $end
-$var wire 1 jM enable_pad_vddio_q $end
-$var wire 1 kM enable_pad_amuxbus_b $end
-$var wire 1 lM enable_pad_amuxbus_a $end
-$var wire 1 mM disable_inp_buff_lv $end
-$var wire 1 nM disable_inp_buff $end
-$var wire 3 oM amux_select [2:0] $end
-$var wire 1 (M TIE_LO_ESD $end
-$var wire 1 )M TIE_HI_ESD $end
-$var wire 1 *M IN_H $end
-$var wire 1 +M IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 pM analog_en_final $end
-$var reg 1 qM analog_en_vdda $end
-$var reg 1 rM analog_en_vddio_q $end
-$var reg 1 sM analog_en_vswitch $end
-$var reg 1 tM dis_err_msgs $end
-$var reg 3 uM dm_final [2:0] $end
-$var reg 1 vM hld_ovr_final $end
-$var reg 1 wM ib_mode_sel_final $end
-$var reg 1 xM inp_dis_final $end
-$var reg 1 yM notifier_dm $end
-$var reg 1 zM notifier_enable_h $end
-$var reg 1 {M notifier_hld_ovr $end
-$var reg 1 |M notifier_ib_mode_sel $end
-$var reg 1 }M notifier_inp_dis $end
-$var reg 1 ~M notifier_oe_n $end
-$var reg 1 !N notifier_out $end
-$var reg 1 "N notifier_slow $end
-$var reg 1 #N notifier_vtrip_sel $end
-$var reg 1 $N oe_n_final $end
-$var reg 1 %N out_final $end
-$var reg 1 &N slow_final $end
-$var reg 1 'N vtrip_sel_final $end
-$var integer 32 (N msg_count_pad [31:0] $end
-$var integer 32 )N msg_count_pad1 [31:0] $end
-$var integer 32 *N msg_count_pad10 [31:0] $end
-$var integer 32 +N msg_count_pad11 [31:0] $end
-$var integer 32 ,N msg_count_pad12 [31:0] $end
-$var integer 32 -N msg_count_pad2 [31:0] $end
-$var integer 32 .N msg_count_pad3 [31:0] $end
-$var integer 32 /N msg_count_pad4 [31:0] $end
-$var integer 32 0N msg_count_pad5 [31:0] $end
-$var integer 32 1N msg_count_pad6 [31:0] $end
-$var integer 32 2N msg_count_pad7 [31:0] $end
-$var integer 32 3N msg_count_pad8 [31:0] $end
-$var integer 32 4N msg_count_pad9 [31:0] $end
-$var integer 32 5N slow_0_delay [31:0] $end
-$var integer 32 6N slow_1_delay [31:0] $end
-$var integer 32 7N slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area1_io_pad[5] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 8N ANALOG_EN $end
-$var wire 1 9N ANALOG_POL $end
-$var wire 1 :N ANALOG_SEL $end
-$var wire 3 ;N DM [2:0] $end
-$var wire 1 <N ENABLE_H $end
-$var wire 1 =N ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 >N HLD_H_N $end
-$var wire 1 ?N HLD_OVR $end
-$var wire 1 @N IB_MODE_SEL $end
-$var wire 1 AN INP_DIS $end
-$var wire 1 BN OE_N $end
-$var wire 1 CN OUT $end
-$var wire 1 DN PAD $end
-$var wire 1 EN PAD_A_ESD_0_H $end
-$var wire 1 FN PAD_A_ESD_1_H $end
-$var wire 1 GN PAD_A_NOESD_H $end
-$var wire 1 HN SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 IN VTRIP_SEL $end
-$var wire 1 JN TIE_LO_ESD $end
-$var wire 1 KN TIE_HI_ESD $end
-$var wire 1 LN IN_H $end
-$var wire 1 MN IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 NN event_error_vswitch5 $end
-$var event 1 ON event_error_vswitch4 $end
-$var event 1 PN event_error_vswitch3 $end
-$var event 1 QN event_error_vswitch2 $end
-$var event 1 RN event_error_vswitch1 $end
-$var event 1 SN event_error_vddio_q2 $end
-$var event 1 TN event_error_vddio_q1 $end
-$var event 1 UN event_error_vdda_vddioq_vswitch2 $end
-$var event 1 VN event_error_vdda3 $end
-$var event 1 WN event_error_vdda2 $end
-$var event 1 XN event_error_vdda $end
-$var event 1 YN event_error_supply_good $end
-$var event 1 ZN event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 8N ANALOG_EN $end
-$var wire 1 9N ANALOG_POL $end
-$var wire 1 :N ANALOG_SEL $end
-$var wire 3 [N DM [2:0] $end
-$var wire 1 <N ENABLE_H $end
-$var wire 1 =N ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 >N HLD_H_N $end
-$var wire 1 ?N HLD_OVR $end
-$var wire 1 @N IB_MODE_SEL $end
-$var wire 1 AN INP_DIS $end
-$var wire 1 BN OE_N $end
-$var wire 1 CN OUT $end
-$var wire 1 DN PAD $end
-$var wire 1 EN PAD_A_ESD_0_H $end
-$var wire 1 FN PAD_A_ESD_1_H $end
-$var wire 1 GN PAD_A_NOESD_H $end
-$var wire 1 HN SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 IN VTRIP_SEL $end
-$var wire 3 \N dm_buf [2:0] $end
-$var wire 1 ]N error_enable_vddio $end
-$var wire 1 ^N error_supply_good $end
-$var wire 1 _N error_vdda $end
-$var wire 1 `N error_vdda2 $end
-$var wire 1 aN error_vdda3 $end
-$var wire 1 bN error_vdda_vddioq_vswitch2 $end
-$var wire 1 cN error_vddio_q1 $end
-$var wire 1 dN error_vddio_q2 $end
-$var wire 1 eN error_vswitch1 $end
-$var wire 1 fN error_vswitch2 $end
-$var wire 1 gN error_vswitch3 $end
-$var wire 1 hN error_vswitch4 $end
-$var wire 1 iN error_vswitch5 $end
-$var wire 1 jN functional_mode_amux $end
-$var wire 1 kN hld_h_n_buf $end
-$var wire 1 lN hld_ovr_buf $end
-$var wire 1 mN ib_mode_sel_buf $end
-$var wire 1 nN inp_dis_buf $end
-$var wire 1 oN invalid_controls_amux $end
-$var wire 1 pN oe_n_buf $end
-$var wire 1 qN out_buf $end
-$var wire 1 rN pad_tristate $end
-$var wire 1 sN pwr_good_active_mode $end
-$var wire 1 tN pwr_good_active_mode_vdda $end
-$var wire 1 uN pwr_good_amux $end
-$var wire 1 vN pwr_good_analog_en_vdda $end
-$var wire 1 wN pwr_good_analog_en_vddio_q $end
-$var wire 1 xN pwr_good_analog_en_vswitch $end
-$var wire 1 yN pwr_good_hold_mode $end
-$var wire 1 zN pwr_good_hold_mode_vdda $end
-$var wire 1 {N pwr_good_hold_ovr_mode $end
-$var wire 1 |N pwr_good_inpbuff_hv $end
-$var wire 1 }N pwr_good_inpbuff_lv $end
-$var wire 1 ~N pwr_good_output_driver $end
-$var wire 1 !O slow_buf $end
-$var wire 1 "O vtrip_sel_buf $end
-$var wire 1 #O x_on_analog_en_vdda $end
-$var wire 1 $O x_on_analog_en_vddio_q $end
-$var wire 1 %O x_on_analog_en_vswitch $end
-$var wire 1 &O x_on_in_hv $end
-$var wire 1 'O x_on_in_lv $end
-$var wire 1 (O x_on_pad $end
-$var wire 1 )O zero_on_analog_en_vdda $end
-$var wire 1 *O zero_on_analog_en_vddio_q $end
-$var wire 1 +O zero_on_analog_en_vswitch $end
-$var wire 1 ,O pwr_good_amux_vccd $end
-$var wire 1 -O enable_pad_vssio_q $end
-$var wire 1 .O enable_pad_vddio_q $end
-$var wire 1 /O enable_pad_amuxbus_b $end
-$var wire 1 0O enable_pad_amuxbus_a $end
-$var wire 1 1O disable_inp_buff_lv $end
-$var wire 1 2O disable_inp_buff $end
-$var wire 3 3O amux_select [2:0] $end
-$var wire 1 JN TIE_LO_ESD $end
-$var wire 1 KN TIE_HI_ESD $end
-$var wire 1 LN IN_H $end
-$var wire 1 MN IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 4O analog_en_final $end
-$var reg 1 5O analog_en_vdda $end
-$var reg 1 6O analog_en_vddio_q $end
-$var reg 1 7O analog_en_vswitch $end
-$var reg 1 8O dis_err_msgs $end
-$var reg 3 9O dm_final [2:0] $end
-$var reg 1 :O hld_ovr_final $end
-$var reg 1 ;O ib_mode_sel_final $end
-$var reg 1 <O inp_dis_final $end
-$var reg 1 =O notifier_dm $end
-$var reg 1 >O notifier_enable_h $end
-$var reg 1 ?O notifier_hld_ovr $end
-$var reg 1 @O notifier_ib_mode_sel $end
-$var reg 1 AO notifier_inp_dis $end
-$var reg 1 BO notifier_oe_n $end
-$var reg 1 CO notifier_out $end
-$var reg 1 DO notifier_slow $end
-$var reg 1 EO notifier_vtrip_sel $end
-$var reg 1 FO oe_n_final $end
-$var reg 1 GO out_final $end
-$var reg 1 HO slow_final $end
-$var reg 1 IO vtrip_sel_final $end
-$var integer 32 JO msg_count_pad [31:0] $end
-$var integer 32 KO msg_count_pad1 [31:0] $end
-$var integer 32 LO msg_count_pad10 [31:0] $end
-$var integer 32 MO msg_count_pad11 [31:0] $end
-$var integer 32 NO msg_count_pad12 [31:0] $end
-$var integer 32 OO msg_count_pad2 [31:0] $end
-$var integer 32 PO msg_count_pad3 [31:0] $end
-$var integer 32 QO msg_count_pad4 [31:0] $end
-$var integer 32 RO msg_count_pad5 [31:0] $end
-$var integer 32 SO msg_count_pad6 [31:0] $end
-$var integer 32 TO msg_count_pad7 [31:0] $end
-$var integer 32 UO msg_count_pad8 [31:0] $end
-$var integer 32 VO msg_count_pad9 [31:0] $end
-$var integer 32 WO slow_0_delay [31:0] $end
-$var integer 32 XO slow_1_delay [31:0] $end
-$var integer 32 YO slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area1_io_pad[6] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ZO ANALOG_EN $end
-$var wire 1 [O ANALOG_POL $end
-$var wire 1 \O ANALOG_SEL $end
-$var wire 3 ]O DM [2:0] $end
-$var wire 1 ^O ENABLE_H $end
-$var wire 1 _O ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 `O HLD_H_N $end
-$var wire 1 aO HLD_OVR $end
-$var wire 1 bO IB_MODE_SEL $end
-$var wire 1 cO INP_DIS $end
-$var wire 1 dO OE_N $end
-$var wire 1 eO OUT $end
-$var wire 1 fO PAD $end
-$var wire 1 gO PAD_A_ESD_0_H $end
-$var wire 1 hO PAD_A_ESD_1_H $end
-$var wire 1 iO PAD_A_NOESD_H $end
-$var wire 1 jO SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 kO VTRIP_SEL $end
-$var wire 1 lO TIE_LO_ESD $end
-$var wire 1 mO TIE_HI_ESD $end
-$var wire 1 nO IN_H $end
-$var wire 1 oO IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 pO event_error_vswitch5 $end
-$var event 1 qO event_error_vswitch4 $end
-$var event 1 rO event_error_vswitch3 $end
-$var event 1 sO event_error_vswitch2 $end
-$var event 1 tO event_error_vswitch1 $end
-$var event 1 uO event_error_vddio_q2 $end
-$var event 1 vO event_error_vddio_q1 $end
-$var event 1 wO event_error_vdda_vddioq_vswitch2 $end
-$var event 1 xO event_error_vdda3 $end
-$var event 1 yO event_error_vdda2 $end
-$var event 1 zO event_error_vdda $end
-$var event 1 {O event_error_supply_good $end
-$var event 1 |O event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ZO ANALOG_EN $end
-$var wire 1 [O ANALOG_POL $end
-$var wire 1 \O ANALOG_SEL $end
-$var wire 3 }O DM [2:0] $end
-$var wire 1 ^O ENABLE_H $end
-$var wire 1 _O ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 `O HLD_H_N $end
-$var wire 1 aO HLD_OVR $end
-$var wire 1 bO IB_MODE_SEL $end
-$var wire 1 cO INP_DIS $end
-$var wire 1 dO OE_N $end
-$var wire 1 eO OUT $end
-$var wire 1 fO PAD $end
-$var wire 1 gO PAD_A_ESD_0_H $end
-$var wire 1 hO PAD_A_ESD_1_H $end
-$var wire 1 iO PAD_A_NOESD_H $end
-$var wire 1 jO SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 kO VTRIP_SEL $end
-$var wire 3 ~O dm_buf [2:0] $end
-$var wire 1 !P error_enable_vddio $end
-$var wire 1 "P error_supply_good $end
-$var wire 1 #P error_vdda $end
-$var wire 1 $P error_vdda2 $end
-$var wire 1 %P error_vdda3 $end
-$var wire 1 &P error_vdda_vddioq_vswitch2 $end
-$var wire 1 'P error_vddio_q1 $end
-$var wire 1 (P error_vddio_q2 $end
-$var wire 1 )P error_vswitch1 $end
-$var wire 1 *P error_vswitch2 $end
-$var wire 1 +P error_vswitch3 $end
-$var wire 1 ,P error_vswitch4 $end
-$var wire 1 -P error_vswitch5 $end
-$var wire 1 .P functional_mode_amux $end
-$var wire 1 /P hld_h_n_buf $end
-$var wire 1 0P hld_ovr_buf $end
-$var wire 1 1P ib_mode_sel_buf $end
-$var wire 1 2P inp_dis_buf $end
-$var wire 1 3P invalid_controls_amux $end
-$var wire 1 4P oe_n_buf $end
-$var wire 1 5P out_buf $end
-$var wire 1 6P pad_tristate $end
-$var wire 1 7P pwr_good_active_mode $end
-$var wire 1 8P pwr_good_active_mode_vdda $end
-$var wire 1 9P pwr_good_amux $end
-$var wire 1 :P pwr_good_analog_en_vdda $end
-$var wire 1 ;P pwr_good_analog_en_vddio_q $end
-$var wire 1 <P pwr_good_analog_en_vswitch $end
-$var wire 1 =P pwr_good_hold_mode $end
-$var wire 1 >P pwr_good_hold_mode_vdda $end
-$var wire 1 ?P pwr_good_hold_ovr_mode $end
-$var wire 1 @P pwr_good_inpbuff_hv $end
-$var wire 1 AP pwr_good_inpbuff_lv $end
-$var wire 1 BP pwr_good_output_driver $end
-$var wire 1 CP slow_buf $end
-$var wire 1 DP vtrip_sel_buf $end
-$var wire 1 EP x_on_analog_en_vdda $end
-$var wire 1 FP x_on_analog_en_vddio_q $end
-$var wire 1 GP x_on_analog_en_vswitch $end
-$var wire 1 HP x_on_in_hv $end
-$var wire 1 IP x_on_in_lv $end
-$var wire 1 JP x_on_pad $end
-$var wire 1 KP zero_on_analog_en_vdda $end
-$var wire 1 LP zero_on_analog_en_vddio_q $end
-$var wire 1 MP zero_on_analog_en_vswitch $end
-$var wire 1 NP pwr_good_amux_vccd $end
-$var wire 1 OP enable_pad_vssio_q $end
-$var wire 1 PP enable_pad_vddio_q $end
-$var wire 1 QP enable_pad_amuxbus_b $end
-$var wire 1 RP enable_pad_amuxbus_a $end
-$var wire 1 SP disable_inp_buff_lv $end
-$var wire 1 TP disable_inp_buff $end
-$var wire 3 UP amux_select [2:0] $end
-$var wire 1 lO TIE_LO_ESD $end
-$var wire 1 mO TIE_HI_ESD $end
-$var wire 1 nO IN_H $end
-$var wire 1 oO IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 VP analog_en_final $end
-$var reg 1 WP analog_en_vdda $end
-$var reg 1 XP analog_en_vddio_q $end
-$var reg 1 YP analog_en_vswitch $end
-$var reg 1 ZP dis_err_msgs $end
-$var reg 3 [P dm_final [2:0] $end
-$var reg 1 \P hld_ovr_final $end
-$var reg 1 ]P ib_mode_sel_final $end
-$var reg 1 ^P inp_dis_final $end
-$var reg 1 _P notifier_dm $end
-$var reg 1 `P notifier_enable_h $end
-$var reg 1 aP notifier_hld_ovr $end
-$var reg 1 bP notifier_ib_mode_sel $end
-$var reg 1 cP notifier_inp_dis $end
-$var reg 1 dP notifier_oe_n $end
-$var reg 1 eP notifier_out $end
-$var reg 1 fP notifier_slow $end
-$var reg 1 gP notifier_vtrip_sel $end
-$var reg 1 hP oe_n_final $end
-$var reg 1 iP out_final $end
-$var reg 1 jP slow_final $end
-$var reg 1 kP vtrip_sel_final $end
-$var integer 32 lP msg_count_pad [31:0] $end
-$var integer 32 mP msg_count_pad1 [31:0] $end
-$var integer 32 nP msg_count_pad10 [31:0] $end
-$var integer 32 oP msg_count_pad11 [31:0] $end
-$var integer 32 pP msg_count_pad12 [31:0] $end
-$var integer 32 qP msg_count_pad2 [31:0] $end
-$var integer 32 rP msg_count_pad3 [31:0] $end
-$var integer 32 sP msg_count_pad4 [31:0] $end
-$var integer 32 tP msg_count_pad5 [31:0] $end
-$var integer 32 uP msg_count_pad6 [31:0] $end
-$var integer 32 vP msg_count_pad7 [31:0] $end
-$var integer 32 wP msg_count_pad8 [31:0] $end
-$var integer 32 xP msg_count_pad9 [31:0] $end
-$var integer 32 yP slow_0_delay [31:0] $end
-$var integer 32 zP slow_1_delay [31:0] $end
-$var integer 32 {P slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area1_io_pad[7] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 |P ANALOG_EN $end
-$var wire 1 }P ANALOG_POL $end
-$var wire 1 ~P ANALOG_SEL $end
-$var wire 3 !Q DM [2:0] $end
-$var wire 1 "Q ENABLE_H $end
-$var wire 1 #Q ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 $Q HLD_H_N $end
-$var wire 1 %Q HLD_OVR $end
-$var wire 1 &Q IB_MODE_SEL $end
-$var wire 1 'Q INP_DIS $end
-$var wire 1 (Q OE_N $end
-$var wire 1 )Q OUT $end
-$var wire 1 *Q PAD $end
-$var wire 1 +Q PAD_A_ESD_0_H $end
-$var wire 1 ,Q PAD_A_ESD_1_H $end
-$var wire 1 -Q PAD_A_NOESD_H $end
-$var wire 1 .Q SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 /Q VTRIP_SEL $end
-$var wire 1 0Q TIE_LO_ESD $end
-$var wire 1 1Q TIE_HI_ESD $end
-$var wire 1 2Q IN_H $end
-$var wire 1 3Q IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 4Q event_error_vswitch5 $end
-$var event 1 5Q event_error_vswitch4 $end
-$var event 1 6Q event_error_vswitch3 $end
-$var event 1 7Q event_error_vswitch2 $end
-$var event 1 8Q event_error_vswitch1 $end
-$var event 1 9Q event_error_vddio_q2 $end
-$var event 1 :Q event_error_vddio_q1 $end
-$var event 1 ;Q event_error_vdda_vddioq_vswitch2 $end
-$var event 1 <Q event_error_vdda3 $end
-$var event 1 =Q event_error_vdda2 $end
-$var event 1 >Q event_error_vdda $end
-$var event 1 ?Q event_error_supply_good $end
-$var event 1 @Q event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 |P ANALOG_EN $end
-$var wire 1 }P ANALOG_POL $end
-$var wire 1 ~P ANALOG_SEL $end
-$var wire 3 AQ DM [2:0] $end
-$var wire 1 "Q ENABLE_H $end
-$var wire 1 #Q ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 $Q HLD_H_N $end
-$var wire 1 %Q HLD_OVR $end
-$var wire 1 &Q IB_MODE_SEL $end
-$var wire 1 'Q INP_DIS $end
-$var wire 1 (Q OE_N $end
-$var wire 1 )Q OUT $end
-$var wire 1 *Q PAD $end
-$var wire 1 +Q PAD_A_ESD_0_H $end
-$var wire 1 ,Q PAD_A_ESD_1_H $end
-$var wire 1 -Q PAD_A_NOESD_H $end
-$var wire 1 .Q SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 /Q VTRIP_SEL $end
-$var wire 3 BQ dm_buf [2:0] $end
-$var wire 1 CQ error_enable_vddio $end
-$var wire 1 DQ error_supply_good $end
-$var wire 1 EQ error_vdda $end
-$var wire 1 FQ error_vdda2 $end
-$var wire 1 GQ error_vdda3 $end
-$var wire 1 HQ error_vdda_vddioq_vswitch2 $end
-$var wire 1 IQ error_vddio_q1 $end
-$var wire 1 JQ error_vddio_q2 $end
-$var wire 1 KQ error_vswitch1 $end
-$var wire 1 LQ error_vswitch2 $end
-$var wire 1 MQ error_vswitch3 $end
-$var wire 1 NQ error_vswitch4 $end
-$var wire 1 OQ error_vswitch5 $end
-$var wire 1 PQ functional_mode_amux $end
-$var wire 1 QQ hld_h_n_buf $end
-$var wire 1 RQ hld_ovr_buf $end
-$var wire 1 SQ ib_mode_sel_buf $end
-$var wire 1 TQ inp_dis_buf $end
-$var wire 1 UQ invalid_controls_amux $end
-$var wire 1 VQ oe_n_buf $end
-$var wire 1 WQ out_buf $end
-$var wire 1 XQ pad_tristate $end
-$var wire 1 YQ pwr_good_active_mode $end
-$var wire 1 ZQ pwr_good_active_mode_vdda $end
-$var wire 1 [Q pwr_good_amux $end
-$var wire 1 \Q pwr_good_analog_en_vdda $end
-$var wire 1 ]Q pwr_good_analog_en_vddio_q $end
-$var wire 1 ^Q pwr_good_analog_en_vswitch $end
-$var wire 1 _Q pwr_good_hold_mode $end
-$var wire 1 `Q pwr_good_hold_mode_vdda $end
-$var wire 1 aQ pwr_good_hold_ovr_mode $end
-$var wire 1 bQ pwr_good_inpbuff_hv $end
-$var wire 1 cQ pwr_good_inpbuff_lv $end
-$var wire 1 dQ pwr_good_output_driver $end
-$var wire 1 eQ slow_buf $end
-$var wire 1 fQ vtrip_sel_buf $end
-$var wire 1 gQ x_on_analog_en_vdda $end
-$var wire 1 hQ x_on_analog_en_vddio_q $end
-$var wire 1 iQ x_on_analog_en_vswitch $end
-$var wire 1 jQ x_on_in_hv $end
-$var wire 1 kQ x_on_in_lv $end
-$var wire 1 lQ x_on_pad $end
-$var wire 1 mQ zero_on_analog_en_vdda $end
-$var wire 1 nQ zero_on_analog_en_vddio_q $end
-$var wire 1 oQ zero_on_analog_en_vswitch $end
-$var wire 1 pQ pwr_good_amux_vccd $end
-$var wire 1 qQ enable_pad_vssio_q $end
-$var wire 1 rQ enable_pad_vddio_q $end
-$var wire 1 sQ enable_pad_amuxbus_b $end
-$var wire 1 tQ enable_pad_amuxbus_a $end
-$var wire 1 uQ disable_inp_buff_lv $end
-$var wire 1 vQ disable_inp_buff $end
-$var wire 3 wQ amux_select [2:0] $end
-$var wire 1 0Q TIE_LO_ESD $end
-$var wire 1 1Q TIE_HI_ESD $end
-$var wire 1 2Q IN_H $end
-$var wire 1 3Q IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 xQ analog_en_final $end
-$var reg 1 yQ analog_en_vdda $end
-$var reg 1 zQ analog_en_vddio_q $end
-$var reg 1 {Q analog_en_vswitch $end
-$var reg 1 |Q dis_err_msgs $end
-$var reg 3 }Q dm_final [2:0] $end
-$var reg 1 ~Q hld_ovr_final $end
-$var reg 1 !R ib_mode_sel_final $end
-$var reg 1 "R inp_dis_final $end
-$var reg 1 #R notifier_dm $end
-$var reg 1 $R notifier_enable_h $end
-$var reg 1 %R notifier_hld_ovr $end
-$var reg 1 &R notifier_ib_mode_sel $end
-$var reg 1 'R notifier_inp_dis $end
-$var reg 1 (R notifier_oe_n $end
-$var reg 1 )R notifier_out $end
-$var reg 1 *R notifier_slow $end
-$var reg 1 +R notifier_vtrip_sel $end
-$var reg 1 ,R oe_n_final $end
-$var reg 1 -R out_final $end
-$var reg 1 .R slow_final $end
-$var reg 1 /R vtrip_sel_final $end
-$var integer 32 0R msg_count_pad [31:0] $end
-$var integer 32 1R msg_count_pad1 [31:0] $end
-$var integer 32 2R msg_count_pad10 [31:0] $end
-$var integer 32 3R msg_count_pad11 [31:0] $end
-$var integer 32 4R msg_count_pad12 [31:0] $end
-$var integer 32 5R msg_count_pad2 [31:0] $end
-$var integer 32 6R msg_count_pad3 [31:0] $end
-$var integer 32 7R msg_count_pad4 [31:0] $end
-$var integer 32 8R msg_count_pad5 [31:0] $end
-$var integer 32 9R msg_count_pad6 [31:0] $end
-$var integer 32 :R msg_count_pad7 [31:0] $end
-$var integer 32 ;R msg_count_pad8 [31:0] $end
-$var integer 32 <R msg_count_pad9 [31:0] $end
-$var integer 32 =R slow_0_delay [31:0] $end
-$var integer 32 >R slow_1_delay [31:0] $end
-$var integer 32 ?R slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area1_io_pad[8] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 @R ANALOG_EN $end
-$var wire 1 AR ANALOG_POL $end
-$var wire 1 BR ANALOG_SEL $end
-$var wire 3 CR DM [2:0] $end
-$var wire 1 DR ENABLE_H $end
-$var wire 1 ER ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 FR HLD_H_N $end
-$var wire 1 GR HLD_OVR $end
-$var wire 1 HR IB_MODE_SEL $end
-$var wire 1 IR INP_DIS $end
-$var wire 1 JR OE_N $end
-$var wire 1 KR OUT $end
-$var wire 1 LR PAD $end
-$var wire 1 MR PAD_A_ESD_0_H $end
-$var wire 1 NR PAD_A_ESD_1_H $end
-$var wire 1 OR PAD_A_NOESD_H $end
-$var wire 1 PR SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 QR VTRIP_SEL $end
-$var wire 1 RR TIE_LO_ESD $end
-$var wire 1 SR TIE_HI_ESD $end
-$var wire 1 TR IN_H $end
-$var wire 1 UR IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 VR event_error_vswitch5 $end
-$var event 1 WR event_error_vswitch4 $end
-$var event 1 XR event_error_vswitch3 $end
-$var event 1 YR event_error_vswitch2 $end
-$var event 1 ZR event_error_vswitch1 $end
-$var event 1 [R event_error_vddio_q2 $end
-$var event 1 \R event_error_vddio_q1 $end
-$var event 1 ]R event_error_vdda_vddioq_vswitch2 $end
-$var event 1 ^R event_error_vdda3 $end
-$var event 1 _R event_error_vdda2 $end
-$var event 1 `R event_error_vdda $end
-$var event 1 aR event_error_supply_good $end
-$var event 1 bR event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 @R ANALOG_EN $end
-$var wire 1 AR ANALOG_POL $end
-$var wire 1 BR ANALOG_SEL $end
-$var wire 3 cR DM [2:0] $end
-$var wire 1 DR ENABLE_H $end
-$var wire 1 ER ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 FR HLD_H_N $end
-$var wire 1 GR HLD_OVR $end
-$var wire 1 HR IB_MODE_SEL $end
-$var wire 1 IR INP_DIS $end
-$var wire 1 JR OE_N $end
-$var wire 1 KR OUT $end
-$var wire 1 LR PAD $end
-$var wire 1 MR PAD_A_ESD_0_H $end
-$var wire 1 NR PAD_A_ESD_1_H $end
-$var wire 1 OR PAD_A_NOESD_H $end
-$var wire 1 PR SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 QR VTRIP_SEL $end
-$var wire 3 dR dm_buf [2:0] $end
-$var wire 1 eR error_enable_vddio $end
-$var wire 1 fR error_supply_good $end
-$var wire 1 gR error_vdda $end
-$var wire 1 hR error_vdda2 $end
-$var wire 1 iR error_vdda3 $end
-$var wire 1 jR error_vdda_vddioq_vswitch2 $end
-$var wire 1 kR error_vddio_q1 $end
-$var wire 1 lR error_vddio_q2 $end
-$var wire 1 mR error_vswitch1 $end
-$var wire 1 nR error_vswitch2 $end
-$var wire 1 oR error_vswitch3 $end
-$var wire 1 pR error_vswitch4 $end
-$var wire 1 qR error_vswitch5 $end
-$var wire 1 rR functional_mode_amux $end
-$var wire 1 sR hld_h_n_buf $end
-$var wire 1 tR hld_ovr_buf $end
-$var wire 1 uR ib_mode_sel_buf $end
-$var wire 1 vR inp_dis_buf $end
-$var wire 1 wR invalid_controls_amux $end
-$var wire 1 xR oe_n_buf $end
-$var wire 1 yR out_buf $end
-$var wire 1 zR pad_tristate $end
-$var wire 1 {R pwr_good_active_mode $end
-$var wire 1 |R pwr_good_active_mode_vdda $end
-$var wire 1 }R pwr_good_amux $end
-$var wire 1 ~R pwr_good_analog_en_vdda $end
-$var wire 1 !S pwr_good_analog_en_vddio_q $end
-$var wire 1 "S pwr_good_analog_en_vswitch $end
-$var wire 1 #S pwr_good_hold_mode $end
-$var wire 1 $S pwr_good_hold_mode_vdda $end
-$var wire 1 %S pwr_good_hold_ovr_mode $end
-$var wire 1 &S pwr_good_inpbuff_hv $end
-$var wire 1 'S pwr_good_inpbuff_lv $end
-$var wire 1 (S pwr_good_output_driver $end
-$var wire 1 )S slow_buf $end
-$var wire 1 *S vtrip_sel_buf $end
-$var wire 1 +S x_on_analog_en_vdda $end
-$var wire 1 ,S x_on_analog_en_vddio_q $end
-$var wire 1 -S x_on_analog_en_vswitch $end
-$var wire 1 .S x_on_in_hv $end
-$var wire 1 /S x_on_in_lv $end
-$var wire 1 0S x_on_pad $end
-$var wire 1 1S zero_on_analog_en_vdda $end
-$var wire 1 2S zero_on_analog_en_vddio_q $end
-$var wire 1 3S zero_on_analog_en_vswitch $end
-$var wire 1 4S pwr_good_amux_vccd $end
-$var wire 1 5S enable_pad_vssio_q $end
-$var wire 1 6S enable_pad_vddio_q $end
-$var wire 1 7S enable_pad_amuxbus_b $end
-$var wire 1 8S enable_pad_amuxbus_a $end
-$var wire 1 9S disable_inp_buff_lv $end
-$var wire 1 :S disable_inp_buff $end
-$var wire 3 ;S amux_select [2:0] $end
-$var wire 1 RR TIE_LO_ESD $end
-$var wire 1 SR TIE_HI_ESD $end
-$var wire 1 TR IN_H $end
-$var wire 1 UR IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 <S analog_en_final $end
-$var reg 1 =S analog_en_vdda $end
-$var reg 1 >S analog_en_vddio_q $end
-$var reg 1 ?S analog_en_vswitch $end
-$var reg 1 @S dis_err_msgs $end
-$var reg 3 AS dm_final [2:0] $end
-$var reg 1 BS hld_ovr_final $end
-$var reg 1 CS ib_mode_sel_final $end
-$var reg 1 DS inp_dis_final $end
-$var reg 1 ES notifier_dm $end
-$var reg 1 FS notifier_enable_h $end
-$var reg 1 GS notifier_hld_ovr $end
-$var reg 1 HS notifier_ib_mode_sel $end
-$var reg 1 IS notifier_inp_dis $end
-$var reg 1 JS notifier_oe_n $end
-$var reg 1 KS notifier_out $end
-$var reg 1 LS notifier_slow $end
-$var reg 1 MS notifier_vtrip_sel $end
-$var reg 1 NS oe_n_final $end
-$var reg 1 OS out_final $end
-$var reg 1 PS slow_final $end
-$var reg 1 QS vtrip_sel_final $end
-$var integer 32 RS msg_count_pad [31:0] $end
-$var integer 32 SS msg_count_pad1 [31:0] $end
-$var integer 32 TS msg_count_pad10 [31:0] $end
-$var integer 32 US msg_count_pad11 [31:0] $end
-$var integer 32 VS msg_count_pad12 [31:0] $end
-$var integer 32 WS msg_count_pad2 [31:0] $end
-$var integer 32 XS msg_count_pad3 [31:0] $end
-$var integer 32 YS msg_count_pad4 [31:0] $end
-$var integer 32 ZS msg_count_pad5 [31:0] $end
-$var integer 32 [S msg_count_pad6 [31:0] $end
-$var integer 32 \S msg_count_pad7 [31:0] $end
-$var integer 32 ]S msg_count_pad8 [31:0] $end
-$var integer 32 ^S msg_count_pad9 [31:0] $end
-$var integer 32 _S slow_0_delay [31:0] $end
-$var integer 32 `S slow_1_delay [31:0] $end
-$var integer 32 aS slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area1_io_pad[9] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 bS ANALOG_EN $end
-$var wire 1 cS ANALOG_POL $end
-$var wire 1 dS ANALOG_SEL $end
-$var wire 3 eS DM [2:0] $end
-$var wire 1 fS ENABLE_H $end
-$var wire 1 gS ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 hS HLD_H_N $end
-$var wire 1 iS HLD_OVR $end
-$var wire 1 jS IB_MODE_SEL $end
-$var wire 1 kS INP_DIS $end
-$var wire 1 lS OE_N $end
-$var wire 1 mS OUT $end
-$var wire 1 nS PAD $end
-$var wire 1 oS PAD_A_ESD_0_H $end
-$var wire 1 pS PAD_A_ESD_1_H $end
-$var wire 1 qS PAD_A_NOESD_H $end
-$var wire 1 rS SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 sS VTRIP_SEL $end
-$var wire 1 tS TIE_LO_ESD $end
-$var wire 1 uS TIE_HI_ESD $end
-$var wire 1 vS IN_H $end
-$var wire 1 wS IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 xS event_error_vswitch5 $end
-$var event 1 yS event_error_vswitch4 $end
-$var event 1 zS event_error_vswitch3 $end
-$var event 1 {S event_error_vswitch2 $end
-$var event 1 |S event_error_vswitch1 $end
-$var event 1 }S event_error_vddio_q2 $end
-$var event 1 ~S event_error_vddio_q1 $end
-$var event 1 !T event_error_vdda_vddioq_vswitch2 $end
-$var event 1 "T event_error_vdda3 $end
-$var event 1 #T event_error_vdda2 $end
-$var event 1 $T event_error_vdda $end
-$var event 1 %T event_error_supply_good $end
-$var event 1 &T event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 bS ANALOG_EN $end
-$var wire 1 cS ANALOG_POL $end
-$var wire 1 dS ANALOG_SEL $end
-$var wire 3 'T DM [2:0] $end
-$var wire 1 fS ENABLE_H $end
-$var wire 1 gS ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 hS HLD_H_N $end
-$var wire 1 iS HLD_OVR $end
-$var wire 1 jS IB_MODE_SEL $end
-$var wire 1 kS INP_DIS $end
-$var wire 1 lS OE_N $end
-$var wire 1 mS OUT $end
-$var wire 1 nS PAD $end
-$var wire 1 oS PAD_A_ESD_0_H $end
-$var wire 1 pS PAD_A_ESD_1_H $end
-$var wire 1 qS PAD_A_NOESD_H $end
-$var wire 1 rS SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 sS VTRIP_SEL $end
-$var wire 3 (T dm_buf [2:0] $end
-$var wire 1 )T error_enable_vddio $end
-$var wire 1 *T error_supply_good $end
-$var wire 1 +T error_vdda $end
-$var wire 1 ,T error_vdda2 $end
-$var wire 1 -T error_vdda3 $end
-$var wire 1 .T error_vdda_vddioq_vswitch2 $end
-$var wire 1 /T error_vddio_q1 $end
-$var wire 1 0T error_vddio_q2 $end
-$var wire 1 1T error_vswitch1 $end
-$var wire 1 2T error_vswitch2 $end
-$var wire 1 3T error_vswitch3 $end
-$var wire 1 4T error_vswitch4 $end
-$var wire 1 5T error_vswitch5 $end
-$var wire 1 6T functional_mode_amux $end
-$var wire 1 7T hld_h_n_buf $end
-$var wire 1 8T hld_ovr_buf $end
-$var wire 1 9T ib_mode_sel_buf $end
-$var wire 1 :T inp_dis_buf $end
-$var wire 1 ;T invalid_controls_amux $end
-$var wire 1 <T oe_n_buf $end
-$var wire 1 =T out_buf $end
-$var wire 1 >T pad_tristate $end
-$var wire 1 ?T pwr_good_active_mode $end
-$var wire 1 @T pwr_good_active_mode_vdda $end
-$var wire 1 AT pwr_good_amux $end
-$var wire 1 BT pwr_good_analog_en_vdda $end
-$var wire 1 CT pwr_good_analog_en_vddio_q $end
-$var wire 1 DT pwr_good_analog_en_vswitch $end
-$var wire 1 ET pwr_good_hold_mode $end
-$var wire 1 FT pwr_good_hold_mode_vdda $end
-$var wire 1 GT pwr_good_hold_ovr_mode $end
-$var wire 1 HT pwr_good_inpbuff_hv $end
-$var wire 1 IT pwr_good_inpbuff_lv $end
-$var wire 1 JT pwr_good_output_driver $end
-$var wire 1 KT slow_buf $end
-$var wire 1 LT vtrip_sel_buf $end
-$var wire 1 MT x_on_analog_en_vdda $end
-$var wire 1 NT x_on_analog_en_vddio_q $end
-$var wire 1 OT x_on_analog_en_vswitch $end
-$var wire 1 PT x_on_in_hv $end
-$var wire 1 QT x_on_in_lv $end
-$var wire 1 RT x_on_pad $end
-$var wire 1 ST zero_on_analog_en_vdda $end
-$var wire 1 TT zero_on_analog_en_vddio_q $end
-$var wire 1 UT zero_on_analog_en_vswitch $end
-$var wire 1 VT pwr_good_amux_vccd $end
-$var wire 1 WT enable_pad_vssio_q $end
-$var wire 1 XT enable_pad_vddio_q $end
-$var wire 1 YT enable_pad_amuxbus_b $end
-$var wire 1 ZT enable_pad_amuxbus_a $end
-$var wire 1 [T disable_inp_buff_lv $end
-$var wire 1 \T disable_inp_buff $end
-$var wire 3 ]T amux_select [2:0] $end
-$var wire 1 tS TIE_LO_ESD $end
-$var wire 1 uS TIE_HI_ESD $end
-$var wire 1 vS IN_H $end
-$var wire 1 wS IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 ^T analog_en_final $end
-$var reg 1 _T analog_en_vdda $end
-$var reg 1 `T analog_en_vddio_q $end
-$var reg 1 aT analog_en_vswitch $end
-$var reg 1 bT dis_err_msgs $end
-$var reg 3 cT dm_final [2:0] $end
-$var reg 1 dT hld_ovr_final $end
-$var reg 1 eT ib_mode_sel_final $end
-$var reg 1 fT inp_dis_final $end
-$var reg 1 gT notifier_dm $end
-$var reg 1 hT notifier_enable_h $end
-$var reg 1 iT notifier_hld_ovr $end
-$var reg 1 jT notifier_ib_mode_sel $end
-$var reg 1 kT notifier_inp_dis $end
-$var reg 1 lT notifier_oe_n $end
-$var reg 1 mT notifier_out $end
-$var reg 1 nT notifier_slow $end
-$var reg 1 oT notifier_vtrip_sel $end
-$var reg 1 pT oe_n_final $end
-$var reg 1 qT out_final $end
-$var reg 1 rT slow_final $end
-$var reg 1 sT vtrip_sel_final $end
-$var integer 32 tT msg_count_pad [31:0] $end
-$var integer 32 uT msg_count_pad1 [31:0] $end
-$var integer 32 vT msg_count_pad10 [31:0] $end
-$var integer 32 wT msg_count_pad11 [31:0] $end
-$var integer 32 xT msg_count_pad12 [31:0] $end
-$var integer 32 yT msg_count_pad2 [31:0] $end
-$var integer 32 zT msg_count_pad3 [31:0] $end
-$var integer 32 {T msg_count_pad4 [31:0] $end
-$var integer 32 |T msg_count_pad5 [31:0] $end
-$var integer 32 }T msg_count_pad6 [31:0] $end
-$var integer 32 ~T msg_count_pad7 [31:0] $end
-$var integer 32 !U msg_count_pad8 [31:0] $end
-$var integer 32 "U msg_count_pad9 [31:0] $end
-$var integer 32 #U slow_0_delay [31:0] $end
-$var integer 32 $U slow_1_delay [31:0] $end
-$var integer 32 %U slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area1_io_pad[10] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 &U ANALOG_EN $end
-$var wire 1 'U ANALOG_POL $end
-$var wire 1 (U ANALOG_SEL $end
-$var wire 3 )U DM [2:0] $end
-$var wire 1 *U ENABLE_H $end
-$var wire 1 +U ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 ,U HLD_H_N $end
-$var wire 1 -U HLD_OVR $end
-$var wire 1 .U IB_MODE_SEL $end
-$var wire 1 /U INP_DIS $end
-$var wire 1 0U OE_N $end
-$var wire 1 1U OUT $end
-$var wire 1 2U PAD $end
-$var wire 1 3U PAD_A_ESD_0_H $end
-$var wire 1 4U PAD_A_ESD_1_H $end
-$var wire 1 5U PAD_A_NOESD_H $end
-$var wire 1 6U SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 7U VTRIP_SEL $end
-$var wire 1 8U TIE_LO_ESD $end
-$var wire 1 9U TIE_HI_ESD $end
-$var wire 1 :U IN_H $end
-$var wire 1 ;U IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 <U event_error_vswitch5 $end
-$var event 1 =U event_error_vswitch4 $end
-$var event 1 >U event_error_vswitch3 $end
-$var event 1 ?U event_error_vswitch2 $end
-$var event 1 @U event_error_vswitch1 $end
-$var event 1 AU event_error_vddio_q2 $end
-$var event 1 BU event_error_vddio_q1 $end
-$var event 1 CU event_error_vdda_vddioq_vswitch2 $end
-$var event 1 DU event_error_vdda3 $end
-$var event 1 EU event_error_vdda2 $end
-$var event 1 FU event_error_vdda $end
-$var event 1 GU event_error_supply_good $end
-$var event 1 HU event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 &U ANALOG_EN $end
-$var wire 1 'U ANALOG_POL $end
-$var wire 1 (U ANALOG_SEL $end
-$var wire 3 IU DM [2:0] $end
-$var wire 1 *U ENABLE_H $end
-$var wire 1 +U ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 ,U HLD_H_N $end
-$var wire 1 -U HLD_OVR $end
-$var wire 1 .U IB_MODE_SEL $end
-$var wire 1 /U INP_DIS $end
-$var wire 1 0U OE_N $end
-$var wire 1 1U OUT $end
-$var wire 1 2U PAD $end
-$var wire 1 3U PAD_A_ESD_0_H $end
-$var wire 1 4U PAD_A_ESD_1_H $end
-$var wire 1 5U PAD_A_NOESD_H $end
-$var wire 1 6U SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 7U VTRIP_SEL $end
-$var wire 3 JU dm_buf [2:0] $end
-$var wire 1 KU error_enable_vddio $end
-$var wire 1 LU error_supply_good $end
-$var wire 1 MU error_vdda $end
-$var wire 1 NU error_vdda2 $end
-$var wire 1 OU error_vdda3 $end
-$var wire 1 PU error_vdda_vddioq_vswitch2 $end
-$var wire 1 QU error_vddio_q1 $end
-$var wire 1 RU error_vddio_q2 $end
-$var wire 1 SU error_vswitch1 $end
-$var wire 1 TU error_vswitch2 $end
-$var wire 1 UU error_vswitch3 $end
-$var wire 1 VU error_vswitch4 $end
-$var wire 1 WU error_vswitch5 $end
-$var wire 1 XU functional_mode_amux $end
-$var wire 1 YU hld_h_n_buf $end
-$var wire 1 ZU hld_ovr_buf $end
-$var wire 1 [U ib_mode_sel_buf $end
-$var wire 1 \U inp_dis_buf $end
-$var wire 1 ]U invalid_controls_amux $end
-$var wire 1 ^U oe_n_buf $end
-$var wire 1 _U out_buf $end
-$var wire 1 `U pad_tristate $end
-$var wire 1 aU pwr_good_active_mode $end
-$var wire 1 bU pwr_good_active_mode_vdda $end
-$var wire 1 cU pwr_good_amux $end
-$var wire 1 dU pwr_good_analog_en_vdda $end
-$var wire 1 eU pwr_good_analog_en_vddio_q $end
-$var wire 1 fU pwr_good_analog_en_vswitch $end
-$var wire 1 gU pwr_good_hold_mode $end
-$var wire 1 hU pwr_good_hold_mode_vdda $end
-$var wire 1 iU pwr_good_hold_ovr_mode $end
-$var wire 1 jU pwr_good_inpbuff_hv $end
-$var wire 1 kU pwr_good_inpbuff_lv $end
-$var wire 1 lU pwr_good_output_driver $end
-$var wire 1 mU slow_buf $end
-$var wire 1 nU vtrip_sel_buf $end
-$var wire 1 oU x_on_analog_en_vdda $end
-$var wire 1 pU x_on_analog_en_vddio_q $end
-$var wire 1 qU x_on_analog_en_vswitch $end
-$var wire 1 rU x_on_in_hv $end
-$var wire 1 sU x_on_in_lv $end
-$var wire 1 tU x_on_pad $end
-$var wire 1 uU zero_on_analog_en_vdda $end
-$var wire 1 vU zero_on_analog_en_vddio_q $end
-$var wire 1 wU zero_on_analog_en_vswitch $end
-$var wire 1 xU pwr_good_amux_vccd $end
-$var wire 1 yU enable_pad_vssio_q $end
-$var wire 1 zU enable_pad_vddio_q $end
-$var wire 1 {U enable_pad_amuxbus_b $end
-$var wire 1 |U enable_pad_amuxbus_a $end
-$var wire 1 }U disable_inp_buff_lv $end
-$var wire 1 ~U disable_inp_buff $end
-$var wire 3 !V amux_select [2:0] $end
-$var wire 1 8U TIE_LO_ESD $end
-$var wire 1 9U TIE_HI_ESD $end
-$var wire 1 :U IN_H $end
-$var wire 1 ;U IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 "V analog_en_final $end
-$var reg 1 #V analog_en_vdda $end
-$var reg 1 $V analog_en_vddio_q $end
-$var reg 1 %V analog_en_vswitch $end
-$var reg 1 &V dis_err_msgs $end
-$var reg 3 'V dm_final [2:0] $end
-$var reg 1 (V hld_ovr_final $end
-$var reg 1 )V ib_mode_sel_final $end
-$var reg 1 *V inp_dis_final $end
-$var reg 1 +V notifier_dm $end
-$var reg 1 ,V notifier_enable_h $end
-$var reg 1 -V notifier_hld_ovr $end
-$var reg 1 .V notifier_ib_mode_sel $end
-$var reg 1 /V notifier_inp_dis $end
-$var reg 1 0V notifier_oe_n $end
-$var reg 1 1V notifier_out $end
-$var reg 1 2V notifier_slow $end
-$var reg 1 3V notifier_vtrip_sel $end
-$var reg 1 4V oe_n_final $end
-$var reg 1 5V out_final $end
-$var reg 1 6V slow_final $end
-$var reg 1 7V vtrip_sel_final $end
-$var integer 32 8V msg_count_pad [31:0] $end
-$var integer 32 9V msg_count_pad1 [31:0] $end
-$var integer 32 :V msg_count_pad10 [31:0] $end
-$var integer 32 ;V msg_count_pad11 [31:0] $end
-$var integer 32 <V msg_count_pad12 [31:0] $end
-$var integer 32 =V msg_count_pad2 [31:0] $end
-$var integer 32 >V msg_count_pad3 [31:0] $end
-$var integer 32 ?V msg_count_pad4 [31:0] $end
-$var integer 32 @V msg_count_pad5 [31:0] $end
-$var integer 32 AV msg_count_pad6 [31:0] $end
-$var integer 32 BV msg_count_pad7 [31:0] $end
-$var integer 32 CV msg_count_pad8 [31:0] $end
-$var integer 32 DV msg_count_pad9 [31:0] $end
-$var integer 32 EV slow_0_delay [31:0] $end
-$var integer 32 FV slow_1_delay [31:0] $end
-$var integer 32 GV slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area1_io_pad[11] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 HV ANALOG_EN $end
-$var wire 1 IV ANALOG_POL $end
-$var wire 1 JV ANALOG_SEL $end
-$var wire 3 KV DM [2:0] $end
-$var wire 1 LV ENABLE_H $end
-$var wire 1 MV ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 NV HLD_H_N $end
-$var wire 1 OV HLD_OVR $end
-$var wire 1 PV IB_MODE_SEL $end
-$var wire 1 QV INP_DIS $end
-$var wire 1 RV OE_N $end
-$var wire 1 SV OUT $end
-$var wire 1 TV PAD $end
-$var wire 1 UV PAD_A_ESD_0_H $end
-$var wire 1 VV PAD_A_ESD_1_H $end
-$var wire 1 WV PAD_A_NOESD_H $end
-$var wire 1 XV SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 YV VTRIP_SEL $end
-$var wire 1 ZV TIE_LO_ESD $end
-$var wire 1 [V TIE_HI_ESD $end
-$var wire 1 \V IN_H $end
-$var wire 1 ]V IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 ^V event_error_vswitch5 $end
-$var event 1 _V event_error_vswitch4 $end
-$var event 1 `V event_error_vswitch3 $end
-$var event 1 aV event_error_vswitch2 $end
-$var event 1 bV event_error_vswitch1 $end
-$var event 1 cV event_error_vddio_q2 $end
-$var event 1 dV event_error_vddio_q1 $end
-$var event 1 eV event_error_vdda_vddioq_vswitch2 $end
-$var event 1 fV event_error_vdda3 $end
-$var event 1 gV event_error_vdda2 $end
-$var event 1 hV event_error_vdda $end
-$var event 1 iV event_error_supply_good $end
-$var event 1 jV event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 HV ANALOG_EN $end
-$var wire 1 IV ANALOG_POL $end
-$var wire 1 JV ANALOG_SEL $end
-$var wire 3 kV DM [2:0] $end
-$var wire 1 LV ENABLE_H $end
-$var wire 1 MV ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 NV HLD_H_N $end
-$var wire 1 OV HLD_OVR $end
-$var wire 1 PV IB_MODE_SEL $end
-$var wire 1 QV INP_DIS $end
-$var wire 1 RV OE_N $end
-$var wire 1 SV OUT $end
-$var wire 1 TV PAD $end
-$var wire 1 UV PAD_A_ESD_0_H $end
-$var wire 1 VV PAD_A_ESD_1_H $end
-$var wire 1 WV PAD_A_NOESD_H $end
-$var wire 1 XV SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 YV VTRIP_SEL $end
-$var wire 3 lV dm_buf [2:0] $end
-$var wire 1 mV error_enable_vddio $end
-$var wire 1 nV error_supply_good $end
-$var wire 1 oV error_vdda $end
-$var wire 1 pV error_vdda2 $end
-$var wire 1 qV error_vdda3 $end
-$var wire 1 rV error_vdda_vddioq_vswitch2 $end
-$var wire 1 sV error_vddio_q1 $end
-$var wire 1 tV error_vddio_q2 $end
-$var wire 1 uV error_vswitch1 $end
-$var wire 1 vV error_vswitch2 $end
-$var wire 1 wV error_vswitch3 $end
-$var wire 1 xV error_vswitch4 $end
-$var wire 1 yV error_vswitch5 $end
-$var wire 1 zV functional_mode_amux $end
-$var wire 1 {V hld_h_n_buf $end
-$var wire 1 |V hld_ovr_buf $end
-$var wire 1 }V ib_mode_sel_buf $end
-$var wire 1 ~V inp_dis_buf $end
-$var wire 1 !W invalid_controls_amux $end
-$var wire 1 "W oe_n_buf $end
-$var wire 1 #W out_buf $end
-$var wire 1 $W pad_tristate $end
-$var wire 1 %W pwr_good_active_mode $end
-$var wire 1 &W pwr_good_active_mode_vdda $end
-$var wire 1 'W pwr_good_amux $end
-$var wire 1 (W pwr_good_analog_en_vdda $end
-$var wire 1 )W pwr_good_analog_en_vddio_q $end
-$var wire 1 *W pwr_good_analog_en_vswitch $end
-$var wire 1 +W pwr_good_hold_mode $end
-$var wire 1 ,W pwr_good_hold_mode_vdda $end
-$var wire 1 -W pwr_good_hold_ovr_mode $end
-$var wire 1 .W pwr_good_inpbuff_hv $end
-$var wire 1 /W pwr_good_inpbuff_lv $end
-$var wire 1 0W pwr_good_output_driver $end
-$var wire 1 1W slow_buf $end
-$var wire 1 2W vtrip_sel_buf $end
-$var wire 1 3W x_on_analog_en_vdda $end
-$var wire 1 4W x_on_analog_en_vddio_q $end
-$var wire 1 5W x_on_analog_en_vswitch $end
-$var wire 1 6W x_on_in_hv $end
-$var wire 1 7W x_on_in_lv $end
-$var wire 1 8W x_on_pad $end
-$var wire 1 9W zero_on_analog_en_vdda $end
-$var wire 1 :W zero_on_analog_en_vddio_q $end
-$var wire 1 ;W zero_on_analog_en_vswitch $end
-$var wire 1 <W pwr_good_amux_vccd $end
-$var wire 1 =W enable_pad_vssio_q $end
-$var wire 1 >W enable_pad_vddio_q $end
-$var wire 1 ?W enable_pad_amuxbus_b $end
-$var wire 1 @W enable_pad_amuxbus_a $end
-$var wire 1 AW disable_inp_buff_lv $end
-$var wire 1 BW disable_inp_buff $end
-$var wire 3 CW amux_select [2:0] $end
-$var wire 1 ZV TIE_LO_ESD $end
-$var wire 1 [V TIE_HI_ESD $end
-$var wire 1 \V IN_H $end
-$var wire 1 ]V IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 DW analog_en_final $end
-$var reg 1 EW analog_en_vdda $end
-$var reg 1 FW analog_en_vddio_q $end
-$var reg 1 GW analog_en_vswitch $end
-$var reg 1 HW dis_err_msgs $end
-$var reg 3 IW dm_final [2:0] $end
-$var reg 1 JW hld_ovr_final $end
-$var reg 1 KW ib_mode_sel_final $end
-$var reg 1 LW inp_dis_final $end
-$var reg 1 MW notifier_dm $end
-$var reg 1 NW notifier_enable_h $end
-$var reg 1 OW notifier_hld_ovr $end
-$var reg 1 PW notifier_ib_mode_sel $end
-$var reg 1 QW notifier_inp_dis $end
-$var reg 1 RW notifier_oe_n $end
-$var reg 1 SW notifier_out $end
-$var reg 1 TW notifier_slow $end
-$var reg 1 UW notifier_vtrip_sel $end
-$var reg 1 VW oe_n_final $end
-$var reg 1 WW out_final $end
-$var reg 1 XW slow_final $end
-$var reg 1 YW vtrip_sel_final $end
-$var integer 32 ZW msg_count_pad [31:0] $end
-$var integer 32 [W msg_count_pad1 [31:0] $end
-$var integer 32 \W msg_count_pad10 [31:0] $end
-$var integer 32 ]W msg_count_pad11 [31:0] $end
-$var integer 32 ^W msg_count_pad12 [31:0] $end
-$var integer 32 _W msg_count_pad2 [31:0] $end
-$var integer 32 `W msg_count_pad3 [31:0] $end
-$var integer 32 aW msg_count_pad4 [31:0] $end
-$var integer 32 bW msg_count_pad5 [31:0] $end
-$var integer 32 cW msg_count_pad6 [31:0] $end
-$var integer 32 dW msg_count_pad7 [31:0] $end
-$var integer 32 eW msg_count_pad8 [31:0] $end
-$var integer 32 fW msg_count_pad9 [31:0] $end
-$var integer 32 gW slow_0_delay [31:0] $end
-$var integer 32 hW slow_1_delay [31:0] $end
-$var integer 32 iW slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area1_io_pad[12] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 jW ANALOG_EN $end
-$var wire 1 kW ANALOG_POL $end
-$var wire 1 lW ANALOG_SEL $end
-$var wire 3 mW DM [2:0] $end
-$var wire 1 nW ENABLE_H $end
-$var wire 1 oW ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 pW HLD_H_N $end
-$var wire 1 qW HLD_OVR $end
-$var wire 1 rW IB_MODE_SEL $end
-$var wire 1 sW INP_DIS $end
-$var wire 1 tW OE_N $end
-$var wire 1 uW OUT $end
-$var wire 1 vW PAD $end
-$var wire 1 wW PAD_A_ESD_0_H $end
-$var wire 1 xW PAD_A_ESD_1_H $end
-$var wire 1 yW PAD_A_NOESD_H $end
-$var wire 1 zW SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 {W VTRIP_SEL $end
-$var wire 1 |W TIE_LO_ESD $end
-$var wire 1 }W TIE_HI_ESD $end
-$var wire 1 ~W IN_H $end
-$var wire 1 !X IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 "X event_error_vswitch5 $end
-$var event 1 #X event_error_vswitch4 $end
-$var event 1 $X event_error_vswitch3 $end
-$var event 1 %X event_error_vswitch2 $end
-$var event 1 &X event_error_vswitch1 $end
-$var event 1 'X event_error_vddio_q2 $end
-$var event 1 (X event_error_vddio_q1 $end
-$var event 1 )X event_error_vdda_vddioq_vswitch2 $end
-$var event 1 *X event_error_vdda3 $end
-$var event 1 +X event_error_vdda2 $end
-$var event 1 ,X event_error_vdda $end
-$var event 1 -X event_error_supply_good $end
-$var event 1 .X event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 jW ANALOG_EN $end
-$var wire 1 kW ANALOG_POL $end
-$var wire 1 lW ANALOG_SEL $end
-$var wire 3 /X DM [2:0] $end
-$var wire 1 nW ENABLE_H $end
-$var wire 1 oW ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 pW HLD_H_N $end
-$var wire 1 qW HLD_OVR $end
-$var wire 1 rW IB_MODE_SEL $end
-$var wire 1 sW INP_DIS $end
-$var wire 1 tW OE_N $end
-$var wire 1 uW OUT $end
-$var wire 1 vW PAD $end
-$var wire 1 wW PAD_A_ESD_0_H $end
-$var wire 1 xW PAD_A_ESD_1_H $end
-$var wire 1 yW PAD_A_NOESD_H $end
-$var wire 1 zW SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 {W VTRIP_SEL $end
-$var wire 3 0X dm_buf [2:0] $end
-$var wire 1 1X error_enable_vddio $end
-$var wire 1 2X error_supply_good $end
-$var wire 1 3X error_vdda $end
-$var wire 1 4X error_vdda2 $end
-$var wire 1 5X error_vdda3 $end
-$var wire 1 6X error_vdda_vddioq_vswitch2 $end
-$var wire 1 7X error_vddio_q1 $end
-$var wire 1 8X error_vddio_q2 $end
-$var wire 1 9X error_vswitch1 $end
-$var wire 1 :X error_vswitch2 $end
-$var wire 1 ;X error_vswitch3 $end
-$var wire 1 <X error_vswitch4 $end
-$var wire 1 =X error_vswitch5 $end
-$var wire 1 >X functional_mode_amux $end
-$var wire 1 ?X hld_h_n_buf $end
-$var wire 1 @X hld_ovr_buf $end
-$var wire 1 AX ib_mode_sel_buf $end
-$var wire 1 BX inp_dis_buf $end
-$var wire 1 CX invalid_controls_amux $end
-$var wire 1 DX oe_n_buf $end
-$var wire 1 EX out_buf $end
-$var wire 1 FX pad_tristate $end
-$var wire 1 GX pwr_good_active_mode $end
-$var wire 1 HX pwr_good_active_mode_vdda $end
-$var wire 1 IX pwr_good_amux $end
-$var wire 1 JX pwr_good_analog_en_vdda $end
-$var wire 1 KX pwr_good_analog_en_vddio_q $end
-$var wire 1 LX pwr_good_analog_en_vswitch $end
-$var wire 1 MX pwr_good_hold_mode $end
-$var wire 1 NX pwr_good_hold_mode_vdda $end
-$var wire 1 OX pwr_good_hold_ovr_mode $end
-$var wire 1 PX pwr_good_inpbuff_hv $end
-$var wire 1 QX pwr_good_inpbuff_lv $end
-$var wire 1 RX pwr_good_output_driver $end
-$var wire 1 SX slow_buf $end
-$var wire 1 TX vtrip_sel_buf $end
-$var wire 1 UX x_on_analog_en_vdda $end
-$var wire 1 VX x_on_analog_en_vddio_q $end
-$var wire 1 WX x_on_analog_en_vswitch $end
-$var wire 1 XX x_on_in_hv $end
-$var wire 1 YX x_on_in_lv $end
-$var wire 1 ZX x_on_pad $end
-$var wire 1 [X zero_on_analog_en_vdda $end
-$var wire 1 \X zero_on_analog_en_vddio_q $end
-$var wire 1 ]X zero_on_analog_en_vswitch $end
-$var wire 1 ^X pwr_good_amux_vccd $end
-$var wire 1 _X enable_pad_vssio_q $end
-$var wire 1 `X enable_pad_vddio_q $end
-$var wire 1 aX enable_pad_amuxbus_b $end
-$var wire 1 bX enable_pad_amuxbus_a $end
-$var wire 1 cX disable_inp_buff_lv $end
-$var wire 1 dX disable_inp_buff $end
-$var wire 3 eX amux_select [2:0] $end
-$var wire 1 |W TIE_LO_ESD $end
-$var wire 1 }W TIE_HI_ESD $end
-$var wire 1 ~W IN_H $end
-$var wire 1 !X IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 fX analog_en_final $end
-$var reg 1 gX analog_en_vdda $end
-$var reg 1 hX analog_en_vddio_q $end
-$var reg 1 iX analog_en_vswitch $end
-$var reg 1 jX dis_err_msgs $end
-$var reg 3 kX dm_final [2:0] $end
-$var reg 1 lX hld_ovr_final $end
-$var reg 1 mX ib_mode_sel_final $end
-$var reg 1 nX inp_dis_final $end
-$var reg 1 oX notifier_dm $end
-$var reg 1 pX notifier_enable_h $end
-$var reg 1 qX notifier_hld_ovr $end
-$var reg 1 rX notifier_ib_mode_sel $end
-$var reg 1 sX notifier_inp_dis $end
-$var reg 1 tX notifier_oe_n $end
-$var reg 1 uX notifier_out $end
-$var reg 1 vX notifier_slow $end
-$var reg 1 wX notifier_vtrip_sel $end
-$var reg 1 xX oe_n_final $end
-$var reg 1 yX out_final $end
-$var reg 1 zX slow_final $end
-$var reg 1 {X vtrip_sel_final $end
-$var integer 32 |X msg_count_pad [31:0] $end
-$var integer 32 }X msg_count_pad1 [31:0] $end
-$var integer 32 ~X msg_count_pad10 [31:0] $end
-$var integer 32 !Y msg_count_pad11 [31:0] $end
-$var integer 32 "Y msg_count_pad12 [31:0] $end
-$var integer 32 #Y msg_count_pad2 [31:0] $end
-$var integer 32 $Y msg_count_pad3 [31:0] $end
-$var integer 32 %Y msg_count_pad4 [31:0] $end
-$var integer 32 &Y msg_count_pad5 [31:0] $end
-$var integer 32 'Y msg_count_pad6 [31:0] $end
-$var integer 32 (Y msg_count_pad7 [31:0] $end
-$var integer 32 )Y msg_count_pad8 [31:0] $end
-$var integer 32 *Y msg_count_pad9 [31:0] $end
-$var integer 32 +Y slow_0_delay [31:0] $end
-$var integer 32 ,Y slow_1_delay [31:0] $end
-$var integer 32 -Y slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area1_io_pad[13] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 .Y ANALOG_EN $end
-$var wire 1 /Y ANALOG_POL $end
-$var wire 1 0Y ANALOG_SEL $end
-$var wire 3 1Y DM [2:0] $end
-$var wire 1 2Y ENABLE_H $end
-$var wire 1 3Y ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 4Y HLD_H_N $end
-$var wire 1 5Y HLD_OVR $end
-$var wire 1 6Y IB_MODE_SEL $end
-$var wire 1 7Y INP_DIS $end
-$var wire 1 8Y OE_N $end
-$var wire 1 9Y OUT $end
-$var wire 1 :Y PAD $end
-$var wire 1 ;Y PAD_A_ESD_0_H $end
-$var wire 1 <Y PAD_A_ESD_1_H $end
-$var wire 1 =Y PAD_A_NOESD_H $end
-$var wire 1 >Y SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 ?Y VTRIP_SEL $end
-$var wire 1 @Y TIE_LO_ESD $end
-$var wire 1 AY TIE_HI_ESD $end
-$var wire 1 BY IN_H $end
-$var wire 1 CY IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 DY event_error_vswitch5 $end
-$var event 1 EY event_error_vswitch4 $end
-$var event 1 FY event_error_vswitch3 $end
-$var event 1 GY event_error_vswitch2 $end
-$var event 1 HY event_error_vswitch1 $end
-$var event 1 IY event_error_vddio_q2 $end
-$var event 1 JY event_error_vddio_q1 $end
-$var event 1 KY event_error_vdda_vddioq_vswitch2 $end
-$var event 1 LY event_error_vdda3 $end
-$var event 1 MY event_error_vdda2 $end
-$var event 1 NY event_error_vdda $end
-$var event 1 OY event_error_supply_good $end
-$var event 1 PY event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 .Y ANALOG_EN $end
-$var wire 1 /Y ANALOG_POL $end
-$var wire 1 0Y ANALOG_SEL $end
-$var wire 3 QY DM [2:0] $end
-$var wire 1 2Y ENABLE_H $end
-$var wire 1 3Y ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 4Y HLD_H_N $end
-$var wire 1 5Y HLD_OVR $end
-$var wire 1 6Y IB_MODE_SEL $end
-$var wire 1 7Y INP_DIS $end
-$var wire 1 8Y OE_N $end
-$var wire 1 9Y OUT $end
-$var wire 1 :Y PAD $end
-$var wire 1 ;Y PAD_A_ESD_0_H $end
-$var wire 1 <Y PAD_A_ESD_1_H $end
-$var wire 1 =Y PAD_A_NOESD_H $end
-$var wire 1 >Y SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 ?Y VTRIP_SEL $end
-$var wire 3 RY dm_buf [2:0] $end
-$var wire 1 SY error_enable_vddio $end
-$var wire 1 TY error_supply_good $end
-$var wire 1 UY error_vdda $end
-$var wire 1 VY error_vdda2 $end
-$var wire 1 WY error_vdda3 $end
-$var wire 1 XY error_vdda_vddioq_vswitch2 $end
-$var wire 1 YY error_vddio_q1 $end
-$var wire 1 ZY error_vddio_q2 $end
-$var wire 1 [Y error_vswitch1 $end
-$var wire 1 \Y error_vswitch2 $end
-$var wire 1 ]Y error_vswitch3 $end
-$var wire 1 ^Y error_vswitch4 $end
-$var wire 1 _Y error_vswitch5 $end
-$var wire 1 `Y functional_mode_amux $end
-$var wire 1 aY hld_h_n_buf $end
-$var wire 1 bY hld_ovr_buf $end
-$var wire 1 cY ib_mode_sel_buf $end
-$var wire 1 dY inp_dis_buf $end
-$var wire 1 eY invalid_controls_amux $end
-$var wire 1 fY oe_n_buf $end
-$var wire 1 gY out_buf $end
-$var wire 1 hY pad_tristate $end
-$var wire 1 iY pwr_good_active_mode $end
-$var wire 1 jY pwr_good_active_mode_vdda $end
-$var wire 1 kY pwr_good_amux $end
-$var wire 1 lY pwr_good_analog_en_vdda $end
-$var wire 1 mY pwr_good_analog_en_vddio_q $end
-$var wire 1 nY pwr_good_analog_en_vswitch $end
-$var wire 1 oY pwr_good_hold_mode $end
-$var wire 1 pY pwr_good_hold_mode_vdda $end
-$var wire 1 qY pwr_good_hold_ovr_mode $end
-$var wire 1 rY pwr_good_inpbuff_hv $end
-$var wire 1 sY pwr_good_inpbuff_lv $end
-$var wire 1 tY pwr_good_output_driver $end
-$var wire 1 uY slow_buf $end
-$var wire 1 vY vtrip_sel_buf $end
-$var wire 1 wY x_on_analog_en_vdda $end
-$var wire 1 xY x_on_analog_en_vddio_q $end
-$var wire 1 yY x_on_analog_en_vswitch $end
-$var wire 1 zY x_on_in_hv $end
-$var wire 1 {Y x_on_in_lv $end
-$var wire 1 |Y x_on_pad $end
-$var wire 1 }Y zero_on_analog_en_vdda $end
-$var wire 1 ~Y zero_on_analog_en_vddio_q $end
-$var wire 1 !Z zero_on_analog_en_vswitch $end
-$var wire 1 "Z pwr_good_amux_vccd $end
-$var wire 1 #Z enable_pad_vssio_q $end
-$var wire 1 $Z enable_pad_vddio_q $end
-$var wire 1 %Z enable_pad_amuxbus_b $end
-$var wire 1 &Z enable_pad_amuxbus_a $end
-$var wire 1 'Z disable_inp_buff_lv $end
-$var wire 1 (Z disable_inp_buff $end
-$var wire 3 )Z amux_select [2:0] $end
-$var wire 1 @Y TIE_LO_ESD $end
-$var wire 1 AY TIE_HI_ESD $end
-$var wire 1 BY IN_H $end
-$var wire 1 CY IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 *Z analog_en_final $end
-$var reg 1 +Z analog_en_vdda $end
-$var reg 1 ,Z analog_en_vddio_q $end
-$var reg 1 -Z analog_en_vswitch $end
-$var reg 1 .Z dis_err_msgs $end
-$var reg 3 /Z dm_final [2:0] $end
-$var reg 1 0Z hld_ovr_final $end
-$var reg 1 1Z ib_mode_sel_final $end
-$var reg 1 2Z inp_dis_final $end
-$var reg 1 3Z notifier_dm $end
-$var reg 1 4Z notifier_enable_h $end
-$var reg 1 5Z notifier_hld_ovr $end
-$var reg 1 6Z notifier_ib_mode_sel $end
-$var reg 1 7Z notifier_inp_dis $end
-$var reg 1 8Z notifier_oe_n $end
-$var reg 1 9Z notifier_out $end
-$var reg 1 :Z notifier_slow $end
-$var reg 1 ;Z notifier_vtrip_sel $end
-$var reg 1 <Z oe_n_final $end
-$var reg 1 =Z out_final $end
-$var reg 1 >Z slow_final $end
-$var reg 1 ?Z vtrip_sel_final $end
-$var integer 32 @Z msg_count_pad [31:0] $end
-$var integer 32 AZ msg_count_pad1 [31:0] $end
-$var integer 32 BZ msg_count_pad10 [31:0] $end
-$var integer 32 CZ msg_count_pad11 [31:0] $end
-$var integer 32 DZ msg_count_pad12 [31:0] $end
-$var integer 32 EZ msg_count_pad2 [31:0] $end
-$var integer 32 FZ msg_count_pad3 [31:0] $end
-$var integer 32 GZ msg_count_pad4 [31:0] $end
-$var integer 32 HZ msg_count_pad5 [31:0] $end
-$var integer 32 IZ msg_count_pad6 [31:0] $end
-$var integer 32 JZ msg_count_pad7 [31:0] $end
-$var integer 32 KZ msg_count_pad8 [31:0] $end
-$var integer 32 LZ msg_count_pad9 [31:0] $end
-$var integer 32 MZ slow_0_delay [31:0] $end
-$var integer 32 NZ slow_1_delay [31:0] $end
-$var integer 32 OZ slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area1_io_pad[14] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 PZ ANALOG_EN $end
-$var wire 1 QZ ANALOG_POL $end
-$var wire 1 RZ ANALOG_SEL $end
-$var wire 3 SZ DM [2:0] $end
-$var wire 1 TZ ENABLE_H $end
-$var wire 1 UZ ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 VZ HLD_H_N $end
-$var wire 1 WZ HLD_OVR $end
-$var wire 1 XZ IB_MODE_SEL $end
-$var wire 1 YZ INP_DIS $end
-$var wire 1 ZZ OE_N $end
-$var wire 1 [Z OUT $end
-$var wire 1 \Z PAD $end
-$var wire 1 ]Z PAD_A_ESD_0_H $end
-$var wire 1 ^Z PAD_A_ESD_1_H $end
-$var wire 1 _Z PAD_A_NOESD_H $end
-$var wire 1 `Z SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 aZ VTRIP_SEL $end
-$var wire 1 bZ TIE_LO_ESD $end
-$var wire 1 cZ TIE_HI_ESD $end
-$var wire 1 dZ IN_H $end
-$var wire 1 eZ IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 fZ event_error_vswitch5 $end
-$var event 1 gZ event_error_vswitch4 $end
-$var event 1 hZ event_error_vswitch3 $end
-$var event 1 iZ event_error_vswitch2 $end
-$var event 1 jZ event_error_vswitch1 $end
-$var event 1 kZ event_error_vddio_q2 $end
-$var event 1 lZ event_error_vddio_q1 $end
-$var event 1 mZ event_error_vdda_vddioq_vswitch2 $end
-$var event 1 nZ event_error_vdda3 $end
-$var event 1 oZ event_error_vdda2 $end
-$var event 1 pZ event_error_vdda $end
-$var event 1 qZ event_error_supply_good $end
-$var event 1 rZ event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 PZ ANALOG_EN $end
-$var wire 1 QZ ANALOG_POL $end
-$var wire 1 RZ ANALOG_SEL $end
-$var wire 3 sZ DM [2:0] $end
-$var wire 1 TZ ENABLE_H $end
-$var wire 1 UZ ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 VZ HLD_H_N $end
-$var wire 1 WZ HLD_OVR $end
-$var wire 1 XZ IB_MODE_SEL $end
-$var wire 1 YZ INP_DIS $end
-$var wire 1 ZZ OE_N $end
-$var wire 1 [Z OUT $end
-$var wire 1 \Z PAD $end
-$var wire 1 ]Z PAD_A_ESD_0_H $end
-$var wire 1 ^Z PAD_A_ESD_1_H $end
-$var wire 1 _Z PAD_A_NOESD_H $end
-$var wire 1 `Z SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 aZ VTRIP_SEL $end
-$var wire 3 tZ dm_buf [2:0] $end
-$var wire 1 uZ error_enable_vddio $end
-$var wire 1 vZ error_supply_good $end
-$var wire 1 wZ error_vdda $end
-$var wire 1 xZ error_vdda2 $end
-$var wire 1 yZ error_vdda3 $end
-$var wire 1 zZ error_vdda_vddioq_vswitch2 $end
-$var wire 1 {Z error_vddio_q1 $end
-$var wire 1 |Z error_vddio_q2 $end
-$var wire 1 }Z error_vswitch1 $end
-$var wire 1 ~Z error_vswitch2 $end
-$var wire 1 ![ error_vswitch3 $end
-$var wire 1 "[ error_vswitch4 $end
-$var wire 1 #[ error_vswitch5 $end
-$var wire 1 $[ functional_mode_amux $end
-$var wire 1 %[ hld_h_n_buf $end
-$var wire 1 &[ hld_ovr_buf $end
-$var wire 1 '[ ib_mode_sel_buf $end
-$var wire 1 ([ inp_dis_buf $end
-$var wire 1 )[ invalid_controls_amux $end
-$var wire 1 *[ oe_n_buf $end
-$var wire 1 +[ out_buf $end
-$var wire 1 ,[ pad_tristate $end
-$var wire 1 -[ pwr_good_active_mode $end
-$var wire 1 .[ pwr_good_active_mode_vdda $end
-$var wire 1 /[ pwr_good_amux $end
-$var wire 1 0[ pwr_good_analog_en_vdda $end
-$var wire 1 1[ pwr_good_analog_en_vddio_q $end
-$var wire 1 2[ pwr_good_analog_en_vswitch $end
-$var wire 1 3[ pwr_good_hold_mode $end
-$var wire 1 4[ pwr_good_hold_mode_vdda $end
-$var wire 1 5[ pwr_good_hold_ovr_mode $end
-$var wire 1 6[ pwr_good_inpbuff_hv $end
-$var wire 1 7[ pwr_good_inpbuff_lv $end
-$var wire 1 8[ pwr_good_output_driver $end
-$var wire 1 9[ slow_buf $end
-$var wire 1 :[ vtrip_sel_buf $end
-$var wire 1 ;[ x_on_analog_en_vdda $end
-$var wire 1 <[ x_on_analog_en_vddio_q $end
-$var wire 1 =[ x_on_analog_en_vswitch $end
-$var wire 1 >[ x_on_in_hv $end
-$var wire 1 ?[ x_on_in_lv $end
-$var wire 1 @[ x_on_pad $end
-$var wire 1 A[ zero_on_analog_en_vdda $end
-$var wire 1 B[ zero_on_analog_en_vddio_q $end
-$var wire 1 C[ zero_on_analog_en_vswitch $end
-$var wire 1 D[ pwr_good_amux_vccd $end
-$var wire 1 E[ enable_pad_vssio_q $end
-$var wire 1 F[ enable_pad_vddio_q $end
-$var wire 1 G[ enable_pad_amuxbus_b $end
-$var wire 1 H[ enable_pad_amuxbus_a $end
-$var wire 1 I[ disable_inp_buff_lv $end
-$var wire 1 J[ disable_inp_buff $end
-$var wire 3 K[ amux_select [2:0] $end
-$var wire 1 bZ TIE_LO_ESD $end
-$var wire 1 cZ TIE_HI_ESD $end
-$var wire 1 dZ IN_H $end
-$var wire 1 eZ IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 L[ analog_en_final $end
-$var reg 1 M[ analog_en_vdda $end
-$var reg 1 N[ analog_en_vddio_q $end
-$var reg 1 O[ analog_en_vswitch $end
-$var reg 1 P[ dis_err_msgs $end
-$var reg 3 Q[ dm_final [2:0] $end
-$var reg 1 R[ hld_ovr_final $end
-$var reg 1 S[ ib_mode_sel_final $end
-$var reg 1 T[ inp_dis_final $end
-$var reg 1 U[ notifier_dm $end
-$var reg 1 V[ notifier_enable_h $end
-$var reg 1 W[ notifier_hld_ovr $end
-$var reg 1 X[ notifier_ib_mode_sel $end
-$var reg 1 Y[ notifier_inp_dis $end
-$var reg 1 Z[ notifier_oe_n $end
-$var reg 1 [[ notifier_out $end
-$var reg 1 \[ notifier_slow $end
-$var reg 1 ][ notifier_vtrip_sel $end
-$var reg 1 ^[ oe_n_final $end
-$var reg 1 _[ out_final $end
-$var reg 1 `[ slow_final $end
-$var reg 1 a[ vtrip_sel_final $end
-$var integer 32 b[ msg_count_pad [31:0] $end
-$var integer 32 c[ msg_count_pad1 [31:0] $end
-$var integer 32 d[ msg_count_pad10 [31:0] $end
-$var integer 32 e[ msg_count_pad11 [31:0] $end
-$var integer 32 f[ msg_count_pad12 [31:0] $end
-$var integer 32 g[ msg_count_pad2 [31:0] $end
-$var integer 32 h[ msg_count_pad3 [31:0] $end
-$var integer 32 i[ msg_count_pad4 [31:0] $end
-$var integer 32 j[ msg_count_pad5 [31:0] $end
-$var integer 32 k[ msg_count_pad6 [31:0] $end
-$var integer 32 l[ msg_count_pad7 [31:0] $end
-$var integer 32 m[ msg_count_pad8 [31:0] $end
-$var integer 32 n[ msg_count_pad9 [31:0] $end
-$var integer 32 o[ slow_0_delay [31:0] $end
-$var integer 32 p[ slow_1_delay [31:0] $end
-$var integer 32 q[ slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area1_io_pad[15] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 r[ ANALOG_EN $end
-$var wire 1 s[ ANALOG_POL $end
-$var wire 1 t[ ANALOG_SEL $end
-$var wire 3 u[ DM [2:0] $end
-$var wire 1 v[ ENABLE_H $end
-$var wire 1 w[ ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 x[ HLD_H_N $end
-$var wire 1 y[ HLD_OVR $end
-$var wire 1 z[ IB_MODE_SEL $end
-$var wire 1 {[ INP_DIS $end
-$var wire 1 |[ OE_N $end
-$var wire 1 }[ OUT $end
-$var wire 1 ~[ PAD $end
-$var wire 1 !\ PAD_A_ESD_0_H $end
-$var wire 1 "\ PAD_A_ESD_1_H $end
-$var wire 1 #\ PAD_A_NOESD_H $end
-$var wire 1 $\ SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 %\ VTRIP_SEL $end
-$var wire 1 &\ TIE_LO_ESD $end
-$var wire 1 '\ TIE_HI_ESD $end
-$var wire 1 (\ IN_H $end
-$var wire 1 )\ IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 *\ event_error_vswitch5 $end
-$var event 1 +\ event_error_vswitch4 $end
-$var event 1 ,\ event_error_vswitch3 $end
-$var event 1 -\ event_error_vswitch2 $end
-$var event 1 .\ event_error_vswitch1 $end
-$var event 1 /\ event_error_vddio_q2 $end
-$var event 1 0\ event_error_vddio_q1 $end
-$var event 1 1\ event_error_vdda_vddioq_vswitch2 $end
-$var event 1 2\ event_error_vdda3 $end
-$var event 1 3\ event_error_vdda2 $end
-$var event 1 4\ event_error_vdda $end
-$var event 1 5\ event_error_supply_good $end
-$var event 1 6\ event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 r[ ANALOG_EN $end
-$var wire 1 s[ ANALOG_POL $end
-$var wire 1 t[ ANALOG_SEL $end
-$var wire 3 7\ DM [2:0] $end
-$var wire 1 v[ ENABLE_H $end
-$var wire 1 w[ ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 x[ HLD_H_N $end
-$var wire 1 y[ HLD_OVR $end
-$var wire 1 z[ IB_MODE_SEL $end
-$var wire 1 {[ INP_DIS $end
-$var wire 1 |[ OE_N $end
-$var wire 1 }[ OUT $end
-$var wire 1 ~[ PAD $end
-$var wire 1 !\ PAD_A_ESD_0_H $end
-$var wire 1 "\ PAD_A_ESD_1_H $end
-$var wire 1 #\ PAD_A_NOESD_H $end
-$var wire 1 $\ SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 %\ VTRIP_SEL $end
-$var wire 3 8\ dm_buf [2:0] $end
-$var wire 1 9\ error_enable_vddio $end
-$var wire 1 :\ error_supply_good $end
-$var wire 1 ;\ error_vdda $end
-$var wire 1 <\ error_vdda2 $end
-$var wire 1 =\ error_vdda3 $end
-$var wire 1 >\ error_vdda_vddioq_vswitch2 $end
-$var wire 1 ?\ error_vddio_q1 $end
-$var wire 1 @\ error_vddio_q2 $end
-$var wire 1 A\ error_vswitch1 $end
-$var wire 1 B\ error_vswitch2 $end
-$var wire 1 C\ error_vswitch3 $end
-$var wire 1 D\ error_vswitch4 $end
-$var wire 1 E\ error_vswitch5 $end
-$var wire 1 F\ functional_mode_amux $end
-$var wire 1 G\ hld_h_n_buf $end
-$var wire 1 H\ hld_ovr_buf $end
-$var wire 1 I\ ib_mode_sel_buf $end
-$var wire 1 J\ inp_dis_buf $end
-$var wire 1 K\ invalid_controls_amux $end
-$var wire 1 L\ oe_n_buf $end
-$var wire 1 M\ out_buf $end
-$var wire 1 N\ pad_tristate $end
-$var wire 1 O\ pwr_good_active_mode $end
-$var wire 1 P\ pwr_good_active_mode_vdda $end
-$var wire 1 Q\ pwr_good_amux $end
-$var wire 1 R\ pwr_good_analog_en_vdda $end
-$var wire 1 S\ pwr_good_analog_en_vddio_q $end
-$var wire 1 T\ pwr_good_analog_en_vswitch $end
-$var wire 1 U\ pwr_good_hold_mode $end
-$var wire 1 V\ pwr_good_hold_mode_vdda $end
-$var wire 1 W\ pwr_good_hold_ovr_mode $end
-$var wire 1 X\ pwr_good_inpbuff_hv $end
-$var wire 1 Y\ pwr_good_inpbuff_lv $end
-$var wire 1 Z\ pwr_good_output_driver $end
-$var wire 1 [\ slow_buf $end
-$var wire 1 \\ vtrip_sel_buf $end
-$var wire 1 ]\ x_on_analog_en_vdda $end
-$var wire 1 ^\ x_on_analog_en_vddio_q $end
-$var wire 1 _\ x_on_analog_en_vswitch $end
-$var wire 1 `\ x_on_in_hv $end
-$var wire 1 a\ x_on_in_lv $end
-$var wire 1 b\ x_on_pad $end
-$var wire 1 c\ zero_on_analog_en_vdda $end
-$var wire 1 d\ zero_on_analog_en_vddio_q $end
-$var wire 1 e\ zero_on_analog_en_vswitch $end
-$var wire 1 f\ pwr_good_amux_vccd $end
-$var wire 1 g\ enable_pad_vssio_q $end
-$var wire 1 h\ enable_pad_vddio_q $end
-$var wire 1 i\ enable_pad_amuxbus_b $end
-$var wire 1 j\ enable_pad_amuxbus_a $end
-$var wire 1 k\ disable_inp_buff_lv $end
-$var wire 1 l\ disable_inp_buff $end
-$var wire 3 m\ amux_select [2:0] $end
-$var wire 1 &\ TIE_LO_ESD $end
-$var wire 1 '\ TIE_HI_ESD $end
-$var wire 1 (\ IN_H $end
-$var wire 1 )\ IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 n\ analog_en_final $end
-$var reg 1 o\ analog_en_vdda $end
-$var reg 1 p\ analog_en_vddio_q $end
-$var reg 1 q\ analog_en_vswitch $end
-$var reg 1 r\ dis_err_msgs $end
-$var reg 3 s\ dm_final [2:0] $end
-$var reg 1 t\ hld_ovr_final $end
-$var reg 1 u\ ib_mode_sel_final $end
-$var reg 1 v\ inp_dis_final $end
-$var reg 1 w\ notifier_dm $end
-$var reg 1 x\ notifier_enable_h $end
-$var reg 1 y\ notifier_hld_ovr $end
-$var reg 1 z\ notifier_ib_mode_sel $end
-$var reg 1 {\ notifier_inp_dis $end
-$var reg 1 |\ notifier_oe_n $end
-$var reg 1 }\ notifier_out $end
-$var reg 1 ~\ notifier_slow $end
-$var reg 1 !] notifier_vtrip_sel $end
-$var reg 1 "] oe_n_final $end
-$var reg 1 #] out_final $end
-$var reg 1 $] slow_final $end
-$var reg 1 %] vtrip_sel_final $end
-$var integer 32 &] msg_count_pad [31:0] $end
-$var integer 32 '] msg_count_pad1 [31:0] $end
-$var integer 32 (] msg_count_pad10 [31:0] $end
-$var integer 32 )] msg_count_pad11 [31:0] $end
-$var integer 32 *] msg_count_pad12 [31:0] $end
-$var integer 32 +] msg_count_pad2 [31:0] $end
-$var integer 32 ,] msg_count_pad3 [31:0] $end
-$var integer 32 -] msg_count_pad4 [31:0] $end
-$var integer 32 .] msg_count_pad5 [31:0] $end
-$var integer 32 /] msg_count_pad6 [31:0] $end
-$var integer 32 0] msg_count_pad7 [31:0] $end
-$var integer 32 1] msg_count_pad8 [31:0] $end
-$var integer 32 2] msg_count_pad9 [31:0] $end
-$var integer 32 3] slow_0_delay [31:0] $end
-$var integer 32 4] slow_1_delay [31:0] $end
-$var integer 32 5] slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area1_io_pad[16] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 6] ANALOG_EN $end
-$var wire 1 7] ANALOG_POL $end
-$var wire 1 8] ANALOG_SEL $end
-$var wire 3 9] DM [2:0] $end
-$var wire 1 :] ENABLE_H $end
-$var wire 1 ;] ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 <] HLD_H_N $end
-$var wire 1 =] HLD_OVR $end
-$var wire 1 >] IB_MODE_SEL $end
-$var wire 1 ?] INP_DIS $end
-$var wire 1 @] OE_N $end
-$var wire 1 A] OUT $end
-$var wire 1 B] PAD $end
-$var wire 1 C] PAD_A_ESD_0_H $end
-$var wire 1 D] PAD_A_ESD_1_H $end
-$var wire 1 E] PAD_A_NOESD_H $end
-$var wire 1 F] SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 G] VTRIP_SEL $end
-$var wire 1 H] TIE_LO_ESD $end
-$var wire 1 I] TIE_HI_ESD $end
-$var wire 1 J] IN_H $end
-$var wire 1 K] IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 L] event_error_vswitch5 $end
-$var event 1 M] event_error_vswitch4 $end
-$var event 1 N] event_error_vswitch3 $end
-$var event 1 O] event_error_vswitch2 $end
-$var event 1 P] event_error_vswitch1 $end
-$var event 1 Q] event_error_vddio_q2 $end
-$var event 1 R] event_error_vddio_q1 $end
-$var event 1 S] event_error_vdda_vddioq_vswitch2 $end
-$var event 1 T] event_error_vdda3 $end
-$var event 1 U] event_error_vdda2 $end
-$var event 1 V] event_error_vdda $end
-$var event 1 W] event_error_supply_good $end
-$var event 1 X] event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 6] ANALOG_EN $end
-$var wire 1 7] ANALOG_POL $end
-$var wire 1 8] ANALOG_SEL $end
-$var wire 3 Y] DM [2:0] $end
-$var wire 1 :] ENABLE_H $end
-$var wire 1 ;] ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 <] HLD_H_N $end
-$var wire 1 =] HLD_OVR $end
-$var wire 1 >] IB_MODE_SEL $end
-$var wire 1 ?] INP_DIS $end
-$var wire 1 @] OE_N $end
-$var wire 1 A] OUT $end
-$var wire 1 B] PAD $end
-$var wire 1 C] PAD_A_ESD_0_H $end
-$var wire 1 D] PAD_A_ESD_1_H $end
-$var wire 1 E] PAD_A_NOESD_H $end
-$var wire 1 F] SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 G] VTRIP_SEL $end
-$var wire 3 Z] dm_buf [2:0] $end
-$var wire 1 [] error_enable_vddio $end
-$var wire 1 \] error_supply_good $end
-$var wire 1 ]] error_vdda $end
-$var wire 1 ^] error_vdda2 $end
-$var wire 1 _] error_vdda3 $end
-$var wire 1 `] error_vdda_vddioq_vswitch2 $end
-$var wire 1 a] error_vddio_q1 $end
-$var wire 1 b] error_vddio_q2 $end
-$var wire 1 c] error_vswitch1 $end
-$var wire 1 d] error_vswitch2 $end
-$var wire 1 e] error_vswitch3 $end
-$var wire 1 f] error_vswitch4 $end
-$var wire 1 g] error_vswitch5 $end
-$var wire 1 h] functional_mode_amux $end
-$var wire 1 i] hld_h_n_buf $end
-$var wire 1 j] hld_ovr_buf $end
-$var wire 1 k] ib_mode_sel_buf $end
-$var wire 1 l] inp_dis_buf $end
-$var wire 1 m] invalid_controls_amux $end
-$var wire 1 n] oe_n_buf $end
-$var wire 1 o] out_buf $end
-$var wire 1 p] pad_tristate $end
-$var wire 1 q] pwr_good_active_mode $end
-$var wire 1 r] pwr_good_active_mode_vdda $end
-$var wire 1 s] pwr_good_amux $end
-$var wire 1 t] pwr_good_analog_en_vdda $end
-$var wire 1 u] pwr_good_analog_en_vddio_q $end
-$var wire 1 v] pwr_good_analog_en_vswitch $end
-$var wire 1 w] pwr_good_hold_mode $end
-$var wire 1 x] pwr_good_hold_mode_vdda $end
-$var wire 1 y] pwr_good_hold_ovr_mode $end
-$var wire 1 z] pwr_good_inpbuff_hv $end
-$var wire 1 {] pwr_good_inpbuff_lv $end
-$var wire 1 |] pwr_good_output_driver $end
-$var wire 1 }] slow_buf $end
-$var wire 1 ~] vtrip_sel_buf $end
-$var wire 1 !^ x_on_analog_en_vdda $end
-$var wire 1 "^ x_on_analog_en_vddio_q $end
-$var wire 1 #^ x_on_analog_en_vswitch $end
-$var wire 1 $^ x_on_in_hv $end
-$var wire 1 %^ x_on_in_lv $end
-$var wire 1 &^ x_on_pad $end
-$var wire 1 '^ zero_on_analog_en_vdda $end
-$var wire 1 (^ zero_on_analog_en_vddio_q $end
-$var wire 1 )^ zero_on_analog_en_vswitch $end
-$var wire 1 *^ pwr_good_amux_vccd $end
-$var wire 1 +^ enable_pad_vssio_q $end
-$var wire 1 ,^ enable_pad_vddio_q $end
-$var wire 1 -^ enable_pad_amuxbus_b $end
-$var wire 1 .^ enable_pad_amuxbus_a $end
-$var wire 1 /^ disable_inp_buff_lv $end
-$var wire 1 0^ disable_inp_buff $end
-$var wire 3 1^ amux_select [2:0] $end
-$var wire 1 H] TIE_LO_ESD $end
-$var wire 1 I] TIE_HI_ESD $end
-$var wire 1 J] IN_H $end
-$var wire 1 K] IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 2^ analog_en_final $end
-$var reg 1 3^ analog_en_vdda $end
-$var reg 1 4^ analog_en_vddio_q $end
-$var reg 1 5^ analog_en_vswitch $end
-$var reg 1 6^ dis_err_msgs $end
-$var reg 3 7^ dm_final [2:0] $end
-$var reg 1 8^ hld_ovr_final $end
-$var reg 1 9^ ib_mode_sel_final $end
-$var reg 1 :^ inp_dis_final $end
-$var reg 1 ;^ notifier_dm $end
-$var reg 1 <^ notifier_enable_h $end
-$var reg 1 =^ notifier_hld_ovr $end
-$var reg 1 >^ notifier_ib_mode_sel $end
-$var reg 1 ?^ notifier_inp_dis $end
-$var reg 1 @^ notifier_oe_n $end
-$var reg 1 A^ notifier_out $end
-$var reg 1 B^ notifier_slow $end
-$var reg 1 C^ notifier_vtrip_sel $end
-$var reg 1 D^ oe_n_final $end
-$var reg 1 E^ out_final $end
-$var reg 1 F^ slow_final $end
-$var reg 1 G^ vtrip_sel_final $end
-$var integer 32 H^ msg_count_pad [31:0] $end
-$var integer 32 I^ msg_count_pad1 [31:0] $end
-$var integer 32 J^ msg_count_pad10 [31:0] $end
-$var integer 32 K^ msg_count_pad11 [31:0] $end
-$var integer 32 L^ msg_count_pad12 [31:0] $end
-$var integer 32 M^ msg_count_pad2 [31:0] $end
-$var integer 32 N^ msg_count_pad3 [31:0] $end
-$var integer 32 O^ msg_count_pad4 [31:0] $end
-$var integer 32 P^ msg_count_pad5 [31:0] $end
-$var integer 32 Q^ msg_count_pad6 [31:0] $end
-$var integer 32 R^ msg_count_pad7 [31:0] $end
-$var integer 32 S^ msg_count_pad8 [31:0] $end
-$var integer 32 T^ msg_count_pad9 [31:0] $end
-$var integer 32 U^ slow_0_delay [31:0] $end
-$var integer 32 V^ slow_1_delay [31:0] $end
-$var integer 32 W^ slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area1_io_pad[17] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 X^ ANALOG_EN $end
-$var wire 1 Y^ ANALOG_POL $end
-$var wire 1 Z^ ANALOG_SEL $end
-$var wire 3 [^ DM [2:0] $end
-$var wire 1 \^ ENABLE_H $end
-$var wire 1 ]^ ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 ^^ HLD_H_N $end
-$var wire 1 _^ HLD_OVR $end
-$var wire 1 `^ IB_MODE_SEL $end
-$var wire 1 a^ INP_DIS $end
-$var wire 1 b^ OE_N $end
-$var wire 1 c^ OUT $end
-$var wire 1 d^ PAD $end
-$var wire 1 e^ PAD_A_ESD_0_H $end
-$var wire 1 f^ PAD_A_ESD_1_H $end
-$var wire 1 g^ PAD_A_NOESD_H $end
-$var wire 1 h^ SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 i^ VTRIP_SEL $end
-$var wire 1 j^ TIE_LO_ESD $end
-$var wire 1 k^ TIE_HI_ESD $end
-$var wire 1 l^ IN_H $end
-$var wire 1 m^ IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 n^ event_error_vswitch5 $end
-$var event 1 o^ event_error_vswitch4 $end
-$var event 1 p^ event_error_vswitch3 $end
-$var event 1 q^ event_error_vswitch2 $end
-$var event 1 r^ event_error_vswitch1 $end
-$var event 1 s^ event_error_vddio_q2 $end
-$var event 1 t^ event_error_vddio_q1 $end
-$var event 1 u^ event_error_vdda_vddioq_vswitch2 $end
-$var event 1 v^ event_error_vdda3 $end
-$var event 1 w^ event_error_vdda2 $end
-$var event 1 x^ event_error_vdda $end
-$var event 1 y^ event_error_supply_good $end
-$var event 1 z^ event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 X^ ANALOG_EN $end
-$var wire 1 Y^ ANALOG_POL $end
-$var wire 1 Z^ ANALOG_SEL $end
-$var wire 3 {^ DM [2:0] $end
-$var wire 1 \^ ENABLE_H $end
-$var wire 1 ]^ ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 ^^ HLD_H_N $end
-$var wire 1 _^ HLD_OVR $end
-$var wire 1 `^ IB_MODE_SEL $end
-$var wire 1 a^ INP_DIS $end
-$var wire 1 b^ OE_N $end
-$var wire 1 c^ OUT $end
-$var wire 1 d^ PAD $end
-$var wire 1 e^ PAD_A_ESD_0_H $end
-$var wire 1 f^ PAD_A_ESD_1_H $end
-$var wire 1 g^ PAD_A_NOESD_H $end
-$var wire 1 h^ SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 i^ VTRIP_SEL $end
-$var wire 3 |^ dm_buf [2:0] $end
-$var wire 1 }^ error_enable_vddio $end
-$var wire 1 ~^ error_supply_good $end
-$var wire 1 !_ error_vdda $end
-$var wire 1 "_ error_vdda2 $end
-$var wire 1 #_ error_vdda3 $end
-$var wire 1 $_ error_vdda_vddioq_vswitch2 $end
-$var wire 1 %_ error_vddio_q1 $end
-$var wire 1 &_ error_vddio_q2 $end
-$var wire 1 '_ error_vswitch1 $end
-$var wire 1 (_ error_vswitch2 $end
-$var wire 1 )_ error_vswitch3 $end
-$var wire 1 *_ error_vswitch4 $end
-$var wire 1 +_ error_vswitch5 $end
-$var wire 1 ,_ functional_mode_amux $end
-$var wire 1 -_ hld_h_n_buf $end
-$var wire 1 ._ hld_ovr_buf $end
-$var wire 1 /_ ib_mode_sel_buf $end
-$var wire 1 0_ inp_dis_buf $end
-$var wire 1 1_ invalid_controls_amux $end
-$var wire 1 2_ oe_n_buf $end
-$var wire 1 3_ out_buf $end
-$var wire 1 4_ pad_tristate $end
-$var wire 1 5_ pwr_good_active_mode $end
-$var wire 1 6_ pwr_good_active_mode_vdda $end
-$var wire 1 7_ pwr_good_amux $end
-$var wire 1 8_ pwr_good_analog_en_vdda $end
-$var wire 1 9_ pwr_good_analog_en_vddio_q $end
-$var wire 1 :_ pwr_good_analog_en_vswitch $end
-$var wire 1 ;_ pwr_good_hold_mode $end
-$var wire 1 <_ pwr_good_hold_mode_vdda $end
-$var wire 1 =_ pwr_good_hold_ovr_mode $end
-$var wire 1 >_ pwr_good_inpbuff_hv $end
-$var wire 1 ?_ pwr_good_inpbuff_lv $end
-$var wire 1 @_ pwr_good_output_driver $end
-$var wire 1 A_ slow_buf $end
-$var wire 1 B_ vtrip_sel_buf $end
-$var wire 1 C_ x_on_analog_en_vdda $end
-$var wire 1 D_ x_on_analog_en_vddio_q $end
-$var wire 1 E_ x_on_analog_en_vswitch $end
-$var wire 1 F_ x_on_in_hv $end
-$var wire 1 G_ x_on_in_lv $end
-$var wire 1 H_ x_on_pad $end
-$var wire 1 I_ zero_on_analog_en_vdda $end
-$var wire 1 J_ zero_on_analog_en_vddio_q $end
-$var wire 1 K_ zero_on_analog_en_vswitch $end
-$var wire 1 L_ pwr_good_amux_vccd $end
-$var wire 1 M_ enable_pad_vssio_q $end
-$var wire 1 N_ enable_pad_vddio_q $end
-$var wire 1 O_ enable_pad_amuxbus_b $end
-$var wire 1 P_ enable_pad_amuxbus_a $end
-$var wire 1 Q_ disable_inp_buff_lv $end
-$var wire 1 R_ disable_inp_buff $end
-$var wire 3 S_ amux_select [2:0] $end
-$var wire 1 j^ TIE_LO_ESD $end
-$var wire 1 k^ TIE_HI_ESD $end
-$var wire 1 l^ IN_H $end
-$var wire 1 m^ IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 T_ analog_en_final $end
-$var reg 1 U_ analog_en_vdda $end
-$var reg 1 V_ analog_en_vddio_q $end
-$var reg 1 W_ analog_en_vswitch $end
-$var reg 1 X_ dis_err_msgs $end
-$var reg 3 Y_ dm_final [2:0] $end
-$var reg 1 Z_ hld_ovr_final $end
-$var reg 1 [_ ib_mode_sel_final $end
-$var reg 1 \_ inp_dis_final $end
-$var reg 1 ]_ notifier_dm $end
-$var reg 1 ^_ notifier_enable_h $end
-$var reg 1 __ notifier_hld_ovr $end
-$var reg 1 `_ notifier_ib_mode_sel $end
-$var reg 1 a_ notifier_inp_dis $end
-$var reg 1 b_ notifier_oe_n $end
-$var reg 1 c_ notifier_out $end
-$var reg 1 d_ notifier_slow $end
-$var reg 1 e_ notifier_vtrip_sel $end
-$var reg 1 f_ oe_n_final $end
-$var reg 1 g_ out_final $end
-$var reg 1 h_ slow_final $end
-$var reg 1 i_ vtrip_sel_final $end
-$var integer 32 j_ msg_count_pad [31:0] $end
-$var integer 32 k_ msg_count_pad1 [31:0] $end
-$var integer 32 l_ msg_count_pad10 [31:0] $end
-$var integer 32 m_ msg_count_pad11 [31:0] $end
-$var integer 32 n_ msg_count_pad12 [31:0] $end
-$var integer 32 o_ msg_count_pad2 [31:0] $end
-$var integer 32 p_ msg_count_pad3 [31:0] $end
-$var integer 32 q_ msg_count_pad4 [31:0] $end
-$var integer 32 r_ msg_count_pad5 [31:0] $end
-$var integer 32 s_ msg_count_pad6 [31:0] $end
-$var integer 32 t_ msg_count_pad7 [31:0] $end
-$var integer 32 u_ msg_count_pad8 [31:0] $end
-$var integer 32 v_ msg_count_pad9 [31:0] $end
-$var integer 32 w_ slow_0_delay [31:0] $end
-$var integer 32 x_ slow_1_delay [31:0] $end
-$var integer 32 y_ slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area2_io_pad[0] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 z_ ANALOG_EN $end
-$var wire 1 {_ ANALOG_POL $end
-$var wire 1 |_ ANALOG_SEL $end
-$var wire 3 }_ DM [2:0] $end
-$var wire 1 ~_ ENABLE_H $end
-$var wire 1 !` ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 "` HLD_H_N $end
-$var wire 1 #` HLD_OVR $end
-$var wire 1 $` IB_MODE_SEL $end
-$var wire 1 %` INP_DIS $end
-$var wire 1 &` OE_N $end
-$var wire 1 '` OUT $end
-$var wire 1 (` PAD $end
-$var wire 1 )` PAD_A_ESD_0_H $end
-$var wire 1 *` PAD_A_ESD_1_H $end
-$var wire 1 +` PAD_A_NOESD_H $end
-$var wire 1 ,` SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 -` VTRIP_SEL $end
-$var wire 1 .` TIE_LO_ESD $end
-$var wire 1 /` TIE_HI_ESD $end
-$var wire 1 0` IN_H $end
-$var wire 1 1` IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 2` event_error_vswitch5 $end
-$var event 1 3` event_error_vswitch4 $end
-$var event 1 4` event_error_vswitch3 $end
-$var event 1 5` event_error_vswitch2 $end
-$var event 1 6` event_error_vswitch1 $end
-$var event 1 7` event_error_vddio_q2 $end
-$var event 1 8` event_error_vddio_q1 $end
-$var event 1 9` event_error_vdda_vddioq_vswitch2 $end
-$var event 1 :` event_error_vdda3 $end
-$var event 1 ;` event_error_vdda2 $end
-$var event 1 <` event_error_vdda $end
-$var event 1 =` event_error_supply_good $end
-$var event 1 >` event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 z_ ANALOG_EN $end
-$var wire 1 {_ ANALOG_POL $end
-$var wire 1 |_ ANALOG_SEL $end
-$var wire 3 ?` DM [2:0] $end
-$var wire 1 ~_ ENABLE_H $end
-$var wire 1 !` ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 "` HLD_H_N $end
-$var wire 1 #` HLD_OVR $end
-$var wire 1 $` IB_MODE_SEL $end
-$var wire 1 %` INP_DIS $end
-$var wire 1 &` OE_N $end
-$var wire 1 '` OUT $end
-$var wire 1 (` PAD $end
-$var wire 1 )` PAD_A_ESD_0_H $end
-$var wire 1 *` PAD_A_ESD_1_H $end
-$var wire 1 +` PAD_A_NOESD_H $end
-$var wire 1 ,` SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 -` VTRIP_SEL $end
-$var wire 3 @` dm_buf [2:0] $end
-$var wire 1 A` error_enable_vddio $end
-$var wire 1 B` error_supply_good $end
-$var wire 1 C` error_vdda $end
-$var wire 1 D` error_vdda2 $end
-$var wire 1 E` error_vdda3 $end
-$var wire 1 F` error_vdda_vddioq_vswitch2 $end
-$var wire 1 G` error_vddio_q1 $end
-$var wire 1 H` error_vddio_q2 $end
-$var wire 1 I` error_vswitch1 $end
-$var wire 1 J` error_vswitch2 $end
-$var wire 1 K` error_vswitch3 $end
-$var wire 1 L` error_vswitch4 $end
-$var wire 1 M` error_vswitch5 $end
-$var wire 1 N` functional_mode_amux $end
-$var wire 1 O` hld_h_n_buf $end
-$var wire 1 P` hld_ovr_buf $end
-$var wire 1 Q` ib_mode_sel_buf $end
-$var wire 1 R` inp_dis_buf $end
-$var wire 1 S` invalid_controls_amux $end
-$var wire 1 T` oe_n_buf $end
-$var wire 1 U` out_buf $end
-$var wire 1 V` pad_tristate $end
-$var wire 1 W` pwr_good_active_mode $end
-$var wire 1 X` pwr_good_active_mode_vdda $end
-$var wire 1 Y` pwr_good_amux $end
-$var wire 1 Z` pwr_good_analog_en_vdda $end
-$var wire 1 [` pwr_good_analog_en_vddio_q $end
-$var wire 1 \` pwr_good_analog_en_vswitch $end
-$var wire 1 ]` pwr_good_hold_mode $end
-$var wire 1 ^` pwr_good_hold_mode_vdda $end
-$var wire 1 _` pwr_good_hold_ovr_mode $end
-$var wire 1 `` pwr_good_inpbuff_hv $end
-$var wire 1 a` pwr_good_inpbuff_lv $end
-$var wire 1 b` pwr_good_output_driver $end
-$var wire 1 c` slow_buf $end
-$var wire 1 d` vtrip_sel_buf $end
-$var wire 1 e` x_on_analog_en_vdda $end
-$var wire 1 f` x_on_analog_en_vddio_q $end
-$var wire 1 g` x_on_analog_en_vswitch $end
-$var wire 1 h` x_on_in_hv $end
-$var wire 1 i` x_on_in_lv $end
-$var wire 1 j` x_on_pad $end
-$var wire 1 k` zero_on_analog_en_vdda $end
-$var wire 1 l` zero_on_analog_en_vddio_q $end
-$var wire 1 m` zero_on_analog_en_vswitch $end
-$var wire 1 n` pwr_good_amux_vccd $end
-$var wire 1 o` enable_pad_vssio_q $end
-$var wire 1 p` enable_pad_vddio_q $end
-$var wire 1 q` enable_pad_amuxbus_b $end
-$var wire 1 r` enable_pad_amuxbus_a $end
-$var wire 1 s` disable_inp_buff_lv $end
-$var wire 1 t` disable_inp_buff $end
-$var wire 3 u` amux_select [2:0] $end
-$var wire 1 .` TIE_LO_ESD $end
-$var wire 1 /` TIE_HI_ESD $end
-$var wire 1 0` IN_H $end
-$var wire 1 1` IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 v` analog_en_final $end
-$var reg 1 w` analog_en_vdda $end
-$var reg 1 x` analog_en_vddio_q $end
-$var reg 1 y` analog_en_vswitch $end
-$var reg 1 z` dis_err_msgs $end
-$var reg 3 {` dm_final [2:0] $end
-$var reg 1 |` hld_ovr_final $end
-$var reg 1 }` ib_mode_sel_final $end
-$var reg 1 ~` inp_dis_final $end
-$var reg 1 !a notifier_dm $end
-$var reg 1 "a notifier_enable_h $end
-$var reg 1 #a notifier_hld_ovr $end
-$var reg 1 $a notifier_ib_mode_sel $end
-$var reg 1 %a notifier_inp_dis $end
-$var reg 1 &a notifier_oe_n $end
-$var reg 1 'a notifier_out $end
-$var reg 1 (a notifier_slow $end
-$var reg 1 )a notifier_vtrip_sel $end
-$var reg 1 *a oe_n_final $end
-$var reg 1 +a out_final $end
-$var reg 1 ,a slow_final $end
-$var reg 1 -a vtrip_sel_final $end
-$var integer 32 .a msg_count_pad [31:0] $end
-$var integer 32 /a msg_count_pad1 [31:0] $end
-$var integer 32 0a msg_count_pad10 [31:0] $end
-$var integer 32 1a msg_count_pad11 [31:0] $end
-$var integer 32 2a msg_count_pad12 [31:0] $end
-$var integer 32 3a msg_count_pad2 [31:0] $end
-$var integer 32 4a msg_count_pad3 [31:0] $end
-$var integer 32 5a msg_count_pad4 [31:0] $end
-$var integer 32 6a msg_count_pad5 [31:0] $end
-$var integer 32 7a msg_count_pad6 [31:0] $end
-$var integer 32 8a msg_count_pad7 [31:0] $end
-$var integer 32 9a msg_count_pad8 [31:0] $end
-$var integer 32 :a msg_count_pad9 [31:0] $end
-$var integer 32 ;a slow_0_delay [31:0] $end
-$var integer 32 <a slow_1_delay [31:0] $end
-$var integer 32 =a slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area2_io_pad[1] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 >a ANALOG_EN $end
-$var wire 1 ?a ANALOG_POL $end
-$var wire 1 @a ANALOG_SEL $end
-$var wire 3 Aa DM [2:0] $end
-$var wire 1 Ba ENABLE_H $end
-$var wire 1 Ca ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 Da HLD_H_N $end
-$var wire 1 Ea HLD_OVR $end
-$var wire 1 Fa IB_MODE_SEL $end
-$var wire 1 Ga INP_DIS $end
-$var wire 1 Ha OE_N $end
-$var wire 1 Ia OUT $end
-$var wire 1 Ja PAD $end
-$var wire 1 Ka PAD_A_ESD_0_H $end
-$var wire 1 La PAD_A_ESD_1_H $end
-$var wire 1 Ma PAD_A_NOESD_H $end
-$var wire 1 Na SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 Oa VTRIP_SEL $end
-$var wire 1 Pa TIE_LO_ESD $end
-$var wire 1 Qa TIE_HI_ESD $end
-$var wire 1 Ra IN_H $end
-$var wire 1 Sa IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 Ta event_error_vswitch5 $end
-$var event 1 Ua event_error_vswitch4 $end
-$var event 1 Va event_error_vswitch3 $end
-$var event 1 Wa event_error_vswitch2 $end
-$var event 1 Xa event_error_vswitch1 $end
-$var event 1 Ya event_error_vddio_q2 $end
-$var event 1 Za event_error_vddio_q1 $end
-$var event 1 [a event_error_vdda_vddioq_vswitch2 $end
-$var event 1 \a event_error_vdda3 $end
-$var event 1 ]a event_error_vdda2 $end
-$var event 1 ^a event_error_vdda $end
-$var event 1 _a event_error_supply_good $end
-$var event 1 `a event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 >a ANALOG_EN $end
-$var wire 1 ?a ANALOG_POL $end
-$var wire 1 @a ANALOG_SEL $end
-$var wire 3 aa DM [2:0] $end
-$var wire 1 Ba ENABLE_H $end
-$var wire 1 Ca ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 Da HLD_H_N $end
-$var wire 1 Ea HLD_OVR $end
-$var wire 1 Fa IB_MODE_SEL $end
-$var wire 1 Ga INP_DIS $end
-$var wire 1 Ha OE_N $end
-$var wire 1 Ia OUT $end
-$var wire 1 Ja PAD $end
-$var wire 1 Ka PAD_A_ESD_0_H $end
-$var wire 1 La PAD_A_ESD_1_H $end
-$var wire 1 Ma PAD_A_NOESD_H $end
-$var wire 1 Na SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 Oa VTRIP_SEL $end
-$var wire 3 ba dm_buf [2:0] $end
-$var wire 1 ca error_enable_vddio $end
-$var wire 1 da error_supply_good $end
-$var wire 1 ea error_vdda $end
-$var wire 1 fa error_vdda2 $end
-$var wire 1 ga error_vdda3 $end
-$var wire 1 ha error_vdda_vddioq_vswitch2 $end
-$var wire 1 ia error_vddio_q1 $end
-$var wire 1 ja error_vddio_q2 $end
-$var wire 1 ka error_vswitch1 $end
-$var wire 1 la error_vswitch2 $end
-$var wire 1 ma error_vswitch3 $end
-$var wire 1 na error_vswitch4 $end
-$var wire 1 oa error_vswitch5 $end
-$var wire 1 pa functional_mode_amux $end
-$var wire 1 qa hld_h_n_buf $end
-$var wire 1 ra hld_ovr_buf $end
-$var wire 1 sa ib_mode_sel_buf $end
-$var wire 1 ta inp_dis_buf $end
-$var wire 1 ua invalid_controls_amux $end
-$var wire 1 va oe_n_buf $end
-$var wire 1 wa out_buf $end
-$var wire 1 xa pad_tristate $end
-$var wire 1 ya pwr_good_active_mode $end
-$var wire 1 za pwr_good_active_mode_vdda $end
-$var wire 1 {a pwr_good_amux $end
-$var wire 1 |a pwr_good_analog_en_vdda $end
-$var wire 1 }a pwr_good_analog_en_vddio_q $end
-$var wire 1 ~a pwr_good_analog_en_vswitch $end
-$var wire 1 !b pwr_good_hold_mode $end
-$var wire 1 "b pwr_good_hold_mode_vdda $end
-$var wire 1 #b pwr_good_hold_ovr_mode $end
-$var wire 1 $b pwr_good_inpbuff_hv $end
-$var wire 1 %b pwr_good_inpbuff_lv $end
-$var wire 1 &b pwr_good_output_driver $end
-$var wire 1 'b slow_buf $end
-$var wire 1 (b vtrip_sel_buf $end
-$var wire 1 )b x_on_analog_en_vdda $end
-$var wire 1 *b x_on_analog_en_vddio_q $end
-$var wire 1 +b x_on_analog_en_vswitch $end
-$var wire 1 ,b x_on_in_hv $end
-$var wire 1 -b x_on_in_lv $end
-$var wire 1 .b x_on_pad $end
-$var wire 1 /b zero_on_analog_en_vdda $end
-$var wire 1 0b zero_on_analog_en_vddio_q $end
-$var wire 1 1b zero_on_analog_en_vswitch $end
-$var wire 1 2b pwr_good_amux_vccd $end
-$var wire 1 3b enable_pad_vssio_q $end
-$var wire 1 4b enable_pad_vddio_q $end
-$var wire 1 5b enable_pad_amuxbus_b $end
-$var wire 1 6b enable_pad_amuxbus_a $end
-$var wire 1 7b disable_inp_buff_lv $end
-$var wire 1 8b disable_inp_buff $end
-$var wire 3 9b amux_select [2:0] $end
-$var wire 1 Pa TIE_LO_ESD $end
-$var wire 1 Qa TIE_HI_ESD $end
-$var wire 1 Ra IN_H $end
-$var wire 1 Sa IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 :b analog_en_final $end
-$var reg 1 ;b analog_en_vdda $end
-$var reg 1 <b analog_en_vddio_q $end
-$var reg 1 =b analog_en_vswitch $end
-$var reg 1 >b dis_err_msgs $end
-$var reg 3 ?b dm_final [2:0] $end
-$var reg 1 @b hld_ovr_final $end
-$var reg 1 Ab ib_mode_sel_final $end
-$var reg 1 Bb inp_dis_final $end
-$var reg 1 Cb notifier_dm $end
-$var reg 1 Db notifier_enable_h $end
-$var reg 1 Eb notifier_hld_ovr $end
-$var reg 1 Fb notifier_ib_mode_sel $end
-$var reg 1 Gb notifier_inp_dis $end
-$var reg 1 Hb notifier_oe_n $end
-$var reg 1 Ib notifier_out $end
-$var reg 1 Jb notifier_slow $end
-$var reg 1 Kb notifier_vtrip_sel $end
-$var reg 1 Lb oe_n_final $end
-$var reg 1 Mb out_final $end
-$var reg 1 Nb slow_final $end
-$var reg 1 Ob vtrip_sel_final $end
-$var integer 32 Pb msg_count_pad [31:0] $end
-$var integer 32 Qb msg_count_pad1 [31:0] $end
-$var integer 32 Rb msg_count_pad10 [31:0] $end
-$var integer 32 Sb msg_count_pad11 [31:0] $end
-$var integer 32 Tb msg_count_pad12 [31:0] $end
-$var integer 32 Ub msg_count_pad2 [31:0] $end
-$var integer 32 Vb msg_count_pad3 [31:0] $end
-$var integer 32 Wb msg_count_pad4 [31:0] $end
-$var integer 32 Xb msg_count_pad5 [31:0] $end
-$var integer 32 Yb msg_count_pad6 [31:0] $end
-$var integer 32 Zb msg_count_pad7 [31:0] $end
-$var integer 32 [b msg_count_pad8 [31:0] $end
-$var integer 32 \b msg_count_pad9 [31:0] $end
-$var integer 32 ]b slow_0_delay [31:0] $end
-$var integer 32 ^b slow_1_delay [31:0] $end
-$var integer 32 _b slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area2_io_pad[2] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 `b ANALOG_EN $end
-$var wire 1 ab ANALOG_POL $end
-$var wire 1 bb ANALOG_SEL $end
-$var wire 3 cb DM [2:0] $end
-$var wire 1 db ENABLE_H $end
-$var wire 1 eb ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 fb HLD_H_N $end
-$var wire 1 gb HLD_OVR $end
-$var wire 1 hb IB_MODE_SEL $end
-$var wire 1 ib INP_DIS $end
-$var wire 1 jb OE_N $end
-$var wire 1 kb OUT $end
-$var wire 1 lb PAD $end
-$var wire 1 mb PAD_A_ESD_0_H $end
-$var wire 1 nb PAD_A_ESD_1_H $end
-$var wire 1 ob PAD_A_NOESD_H $end
-$var wire 1 pb SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 qb VTRIP_SEL $end
-$var wire 1 rb TIE_LO_ESD $end
-$var wire 1 sb TIE_HI_ESD $end
-$var wire 1 tb IN_H $end
-$var wire 1 ub IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 vb event_error_vswitch5 $end
-$var event 1 wb event_error_vswitch4 $end
-$var event 1 xb event_error_vswitch3 $end
-$var event 1 yb event_error_vswitch2 $end
-$var event 1 zb event_error_vswitch1 $end
-$var event 1 {b event_error_vddio_q2 $end
-$var event 1 |b event_error_vddio_q1 $end
-$var event 1 }b event_error_vdda_vddioq_vswitch2 $end
-$var event 1 ~b event_error_vdda3 $end
-$var event 1 !c event_error_vdda2 $end
-$var event 1 "c event_error_vdda $end
-$var event 1 #c event_error_supply_good $end
-$var event 1 $c event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 `b ANALOG_EN $end
-$var wire 1 ab ANALOG_POL $end
-$var wire 1 bb ANALOG_SEL $end
-$var wire 3 %c DM [2:0] $end
-$var wire 1 db ENABLE_H $end
-$var wire 1 eb ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 fb HLD_H_N $end
-$var wire 1 gb HLD_OVR $end
-$var wire 1 hb IB_MODE_SEL $end
-$var wire 1 ib INP_DIS $end
-$var wire 1 jb OE_N $end
-$var wire 1 kb OUT $end
-$var wire 1 lb PAD $end
-$var wire 1 mb PAD_A_ESD_0_H $end
-$var wire 1 nb PAD_A_ESD_1_H $end
-$var wire 1 ob PAD_A_NOESD_H $end
-$var wire 1 pb SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 qb VTRIP_SEL $end
-$var wire 3 &c dm_buf [2:0] $end
-$var wire 1 'c error_enable_vddio $end
-$var wire 1 (c error_supply_good $end
-$var wire 1 )c error_vdda $end
-$var wire 1 *c error_vdda2 $end
-$var wire 1 +c error_vdda3 $end
-$var wire 1 ,c error_vdda_vddioq_vswitch2 $end
-$var wire 1 -c error_vddio_q1 $end
-$var wire 1 .c error_vddio_q2 $end
-$var wire 1 /c error_vswitch1 $end
-$var wire 1 0c error_vswitch2 $end
-$var wire 1 1c error_vswitch3 $end
-$var wire 1 2c error_vswitch4 $end
-$var wire 1 3c error_vswitch5 $end
-$var wire 1 4c functional_mode_amux $end
-$var wire 1 5c hld_h_n_buf $end
-$var wire 1 6c hld_ovr_buf $end
-$var wire 1 7c ib_mode_sel_buf $end
-$var wire 1 8c inp_dis_buf $end
-$var wire 1 9c invalid_controls_amux $end
-$var wire 1 :c oe_n_buf $end
-$var wire 1 ;c out_buf $end
-$var wire 1 <c pad_tristate $end
-$var wire 1 =c pwr_good_active_mode $end
-$var wire 1 >c pwr_good_active_mode_vdda $end
-$var wire 1 ?c pwr_good_amux $end
-$var wire 1 @c pwr_good_analog_en_vdda $end
-$var wire 1 Ac pwr_good_analog_en_vddio_q $end
-$var wire 1 Bc pwr_good_analog_en_vswitch $end
-$var wire 1 Cc pwr_good_hold_mode $end
-$var wire 1 Dc pwr_good_hold_mode_vdda $end
-$var wire 1 Ec pwr_good_hold_ovr_mode $end
-$var wire 1 Fc pwr_good_inpbuff_hv $end
-$var wire 1 Gc pwr_good_inpbuff_lv $end
-$var wire 1 Hc pwr_good_output_driver $end
-$var wire 1 Ic slow_buf $end
-$var wire 1 Jc vtrip_sel_buf $end
-$var wire 1 Kc x_on_analog_en_vdda $end
-$var wire 1 Lc x_on_analog_en_vddio_q $end
-$var wire 1 Mc x_on_analog_en_vswitch $end
-$var wire 1 Nc x_on_in_hv $end
-$var wire 1 Oc x_on_in_lv $end
-$var wire 1 Pc x_on_pad $end
-$var wire 1 Qc zero_on_analog_en_vdda $end
-$var wire 1 Rc zero_on_analog_en_vddio_q $end
-$var wire 1 Sc zero_on_analog_en_vswitch $end
-$var wire 1 Tc pwr_good_amux_vccd $end
-$var wire 1 Uc enable_pad_vssio_q $end
-$var wire 1 Vc enable_pad_vddio_q $end
-$var wire 1 Wc enable_pad_amuxbus_b $end
-$var wire 1 Xc enable_pad_amuxbus_a $end
-$var wire 1 Yc disable_inp_buff_lv $end
-$var wire 1 Zc disable_inp_buff $end
-$var wire 3 [c amux_select [2:0] $end
-$var wire 1 rb TIE_LO_ESD $end
-$var wire 1 sb TIE_HI_ESD $end
-$var wire 1 tb IN_H $end
-$var wire 1 ub IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 \c analog_en_final $end
-$var reg 1 ]c analog_en_vdda $end
-$var reg 1 ^c analog_en_vddio_q $end
-$var reg 1 _c analog_en_vswitch $end
-$var reg 1 `c dis_err_msgs $end
-$var reg 3 ac dm_final [2:0] $end
-$var reg 1 bc hld_ovr_final $end
-$var reg 1 cc ib_mode_sel_final $end
-$var reg 1 dc inp_dis_final $end
-$var reg 1 ec notifier_dm $end
-$var reg 1 fc notifier_enable_h $end
-$var reg 1 gc notifier_hld_ovr $end
-$var reg 1 hc notifier_ib_mode_sel $end
-$var reg 1 ic notifier_inp_dis $end
-$var reg 1 jc notifier_oe_n $end
-$var reg 1 kc notifier_out $end
-$var reg 1 lc notifier_slow $end
-$var reg 1 mc notifier_vtrip_sel $end
-$var reg 1 nc oe_n_final $end
-$var reg 1 oc out_final $end
-$var reg 1 pc slow_final $end
-$var reg 1 qc vtrip_sel_final $end
-$var integer 32 rc msg_count_pad [31:0] $end
-$var integer 32 sc msg_count_pad1 [31:0] $end
-$var integer 32 tc msg_count_pad10 [31:0] $end
-$var integer 32 uc msg_count_pad11 [31:0] $end
-$var integer 32 vc msg_count_pad12 [31:0] $end
-$var integer 32 wc msg_count_pad2 [31:0] $end
-$var integer 32 xc msg_count_pad3 [31:0] $end
-$var integer 32 yc msg_count_pad4 [31:0] $end
-$var integer 32 zc msg_count_pad5 [31:0] $end
-$var integer 32 {c msg_count_pad6 [31:0] $end
-$var integer 32 |c msg_count_pad7 [31:0] $end
-$var integer 32 }c msg_count_pad8 [31:0] $end
-$var integer 32 ~c msg_count_pad9 [31:0] $end
-$var integer 32 !d slow_0_delay [31:0] $end
-$var integer 32 "d slow_1_delay [31:0] $end
-$var integer 32 #d slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area2_io_pad[3] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 $d ANALOG_EN $end
-$var wire 1 %d ANALOG_POL $end
-$var wire 1 &d ANALOG_SEL $end
-$var wire 3 'd DM [2:0] $end
-$var wire 1 (d ENABLE_H $end
-$var wire 1 )d ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 *d HLD_H_N $end
-$var wire 1 +d HLD_OVR $end
-$var wire 1 ,d IB_MODE_SEL $end
-$var wire 1 -d INP_DIS $end
-$var wire 1 .d OE_N $end
-$var wire 1 /d OUT $end
-$var wire 1 0d PAD $end
-$var wire 1 1d PAD_A_ESD_0_H $end
-$var wire 1 2d PAD_A_ESD_1_H $end
-$var wire 1 3d PAD_A_NOESD_H $end
-$var wire 1 4d SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 5d VTRIP_SEL $end
-$var wire 1 6d TIE_LO_ESD $end
-$var wire 1 7d TIE_HI_ESD $end
-$var wire 1 8d IN_H $end
-$var wire 1 9d IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 :d event_error_vswitch5 $end
-$var event 1 ;d event_error_vswitch4 $end
-$var event 1 <d event_error_vswitch3 $end
-$var event 1 =d event_error_vswitch2 $end
-$var event 1 >d event_error_vswitch1 $end
-$var event 1 ?d event_error_vddio_q2 $end
-$var event 1 @d event_error_vddio_q1 $end
-$var event 1 Ad event_error_vdda_vddioq_vswitch2 $end
-$var event 1 Bd event_error_vdda3 $end
-$var event 1 Cd event_error_vdda2 $end
-$var event 1 Dd event_error_vdda $end
-$var event 1 Ed event_error_supply_good $end
-$var event 1 Fd event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 $d ANALOG_EN $end
-$var wire 1 %d ANALOG_POL $end
-$var wire 1 &d ANALOG_SEL $end
-$var wire 3 Gd DM [2:0] $end
-$var wire 1 (d ENABLE_H $end
-$var wire 1 )d ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 *d HLD_H_N $end
-$var wire 1 +d HLD_OVR $end
-$var wire 1 ,d IB_MODE_SEL $end
-$var wire 1 -d INP_DIS $end
-$var wire 1 .d OE_N $end
-$var wire 1 /d OUT $end
-$var wire 1 0d PAD $end
-$var wire 1 1d PAD_A_ESD_0_H $end
-$var wire 1 2d PAD_A_ESD_1_H $end
-$var wire 1 3d PAD_A_NOESD_H $end
-$var wire 1 4d SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 5d VTRIP_SEL $end
-$var wire 3 Hd dm_buf [2:0] $end
-$var wire 1 Id error_enable_vddio $end
-$var wire 1 Jd error_supply_good $end
-$var wire 1 Kd error_vdda $end
-$var wire 1 Ld error_vdda2 $end
-$var wire 1 Md error_vdda3 $end
-$var wire 1 Nd error_vdda_vddioq_vswitch2 $end
-$var wire 1 Od error_vddio_q1 $end
-$var wire 1 Pd error_vddio_q2 $end
-$var wire 1 Qd error_vswitch1 $end
-$var wire 1 Rd error_vswitch2 $end
-$var wire 1 Sd error_vswitch3 $end
-$var wire 1 Td error_vswitch4 $end
-$var wire 1 Ud error_vswitch5 $end
-$var wire 1 Vd functional_mode_amux $end
-$var wire 1 Wd hld_h_n_buf $end
-$var wire 1 Xd hld_ovr_buf $end
-$var wire 1 Yd ib_mode_sel_buf $end
-$var wire 1 Zd inp_dis_buf $end
-$var wire 1 [d invalid_controls_amux $end
-$var wire 1 \d oe_n_buf $end
-$var wire 1 ]d out_buf $end
-$var wire 1 ^d pad_tristate $end
-$var wire 1 _d pwr_good_active_mode $end
-$var wire 1 `d pwr_good_active_mode_vdda $end
-$var wire 1 ad pwr_good_amux $end
-$var wire 1 bd pwr_good_analog_en_vdda $end
-$var wire 1 cd pwr_good_analog_en_vddio_q $end
-$var wire 1 dd pwr_good_analog_en_vswitch $end
-$var wire 1 ed pwr_good_hold_mode $end
-$var wire 1 fd pwr_good_hold_mode_vdda $end
-$var wire 1 gd pwr_good_hold_ovr_mode $end
-$var wire 1 hd pwr_good_inpbuff_hv $end
-$var wire 1 id pwr_good_inpbuff_lv $end
-$var wire 1 jd pwr_good_output_driver $end
-$var wire 1 kd slow_buf $end
-$var wire 1 ld vtrip_sel_buf $end
-$var wire 1 md x_on_analog_en_vdda $end
-$var wire 1 nd x_on_analog_en_vddio_q $end
-$var wire 1 od x_on_analog_en_vswitch $end
-$var wire 1 pd x_on_in_hv $end
-$var wire 1 qd x_on_in_lv $end
-$var wire 1 rd x_on_pad $end
-$var wire 1 sd zero_on_analog_en_vdda $end
-$var wire 1 td zero_on_analog_en_vddio_q $end
-$var wire 1 ud zero_on_analog_en_vswitch $end
-$var wire 1 vd pwr_good_amux_vccd $end
-$var wire 1 wd enable_pad_vssio_q $end
-$var wire 1 xd enable_pad_vddio_q $end
-$var wire 1 yd enable_pad_amuxbus_b $end
-$var wire 1 zd enable_pad_amuxbus_a $end
-$var wire 1 {d disable_inp_buff_lv $end
-$var wire 1 |d disable_inp_buff $end
-$var wire 3 }d amux_select [2:0] $end
-$var wire 1 6d TIE_LO_ESD $end
-$var wire 1 7d TIE_HI_ESD $end
-$var wire 1 8d IN_H $end
-$var wire 1 9d IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 ~d analog_en_final $end
-$var reg 1 !e analog_en_vdda $end
-$var reg 1 "e analog_en_vddio_q $end
-$var reg 1 #e analog_en_vswitch $end
-$var reg 1 $e dis_err_msgs $end
-$var reg 3 %e dm_final [2:0] $end
-$var reg 1 &e hld_ovr_final $end
-$var reg 1 'e ib_mode_sel_final $end
-$var reg 1 (e inp_dis_final $end
-$var reg 1 )e notifier_dm $end
-$var reg 1 *e notifier_enable_h $end
-$var reg 1 +e notifier_hld_ovr $end
-$var reg 1 ,e notifier_ib_mode_sel $end
-$var reg 1 -e notifier_inp_dis $end
-$var reg 1 .e notifier_oe_n $end
-$var reg 1 /e notifier_out $end
-$var reg 1 0e notifier_slow $end
-$var reg 1 1e notifier_vtrip_sel $end
-$var reg 1 2e oe_n_final $end
-$var reg 1 3e out_final $end
-$var reg 1 4e slow_final $end
-$var reg 1 5e vtrip_sel_final $end
-$var integer 32 6e msg_count_pad [31:0] $end
-$var integer 32 7e msg_count_pad1 [31:0] $end
-$var integer 32 8e msg_count_pad10 [31:0] $end
-$var integer 32 9e msg_count_pad11 [31:0] $end
-$var integer 32 :e msg_count_pad12 [31:0] $end
-$var integer 32 ;e msg_count_pad2 [31:0] $end
-$var integer 32 <e msg_count_pad3 [31:0] $end
-$var integer 32 =e msg_count_pad4 [31:0] $end
-$var integer 32 >e msg_count_pad5 [31:0] $end
-$var integer 32 ?e msg_count_pad6 [31:0] $end
-$var integer 32 @e msg_count_pad7 [31:0] $end
-$var integer 32 Ae msg_count_pad8 [31:0] $end
-$var integer 32 Be msg_count_pad9 [31:0] $end
-$var integer 32 Ce slow_0_delay [31:0] $end
-$var integer 32 De slow_1_delay [31:0] $end
-$var integer 32 Ee slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area2_io_pad[4] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 Fe ANALOG_EN $end
-$var wire 1 Ge ANALOG_POL $end
-$var wire 1 He ANALOG_SEL $end
-$var wire 3 Ie DM [2:0] $end
-$var wire 1 Je ENABLE_H $end
-$var wire 1 Ke ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 Le HLD_H_N $end
-$var wire 1 Me HLD_OVR $end
-$var wire 1 Ne IB_MODE_SEL $end
-$var wire 1 Oe INP_DIS $end
-$var wire 1 Pe OE_N $end
-$var wire 1 Qe OUT $end
-$var wire 1 Re PAD $end
-$var wire 1 Se PAD_A_ESD_0_H $end
-$var wire 1 Te PAD_A_ESD_1_H $end
-$var wire 1 Ue PAD_A_NOESD_H $end
-$var wire 1 Ve SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 We VTRIP_SEL $end
-$var wire 1 Xe TIE_LO_ESD $end
-$var wire 1 Ye TIE_HI_ESD $end
-$var wire 1 Ze IN_H $end
-$var wire 1 [e IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 \e event_error_vswitch5 $end
-$var event 1 ]e event_error_vswitch4 $end
-$var event 1 ^e event_error_vswitch3 $end
-$var event 1 _e event_error_vswitch2 $end
-$var event 1 `e event_error_vswitch1 $end
-$var event 1 ae event_error_vddio_q2 $end
-$var event 1 be event_error_vddio_q1 $end
-$var event 1 ce event_error_vdda_vddioq_vswitch2 $end
-$var event 1 de event_error_vdda3 $end
-$var event 1 ee event_error_vdda2 $end
-$var event 1 fe event_error_vdda $end
-$var event 1 ge event_error_supply_good $end
-$var event 1 he event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 Fe ANALOG_EN $end
-$var wire 1 Ge ANALOG_POL $end
-$var wire 1 He ANALOG_SEL $end
-$var wire 3 ie DM [2:0] $end
-$var wire 1 Je ENABLE_H $end
-$var wire 1 Ke ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 Le HLD_H_N $end
-$var wire 1 Me HLD_OVR $end
-$var wire 1 Ne IB_MODE_SEL $end
-$var wire 1 Oe INP_DIS $end
-$var wire 1 Pe OE_N $end
-$var wire 1 Qe OUT $end
-$var wire 1 Re PAD $end
-$var wire 1 Se PAD_A_ESD_0_H $end
-$var wire 1 Te PAD_A_ESD_1_H $end
-$var wire 1 Ue PAD_A_NOESD_H $end
-$var wire 1 Ve SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 We VTRIP_SEL $end
-$var wire 3 je dm_buf [2:0] $end
-$var wire 1 ke error_enable_vddio $end
-$var wire 1 le error_supply_good $end
-$var wire 1 me error_vdda $end
-$var wire 1 ne error_vdda2 $end
-$var wire 1 oe error_vdda3 $end
-$var wire 1 pe error_vdda_vddioq_vswitch2 $end
-$var wire 1 qe error_vddio_q1 $end
-$var wire 1 re error_vddio_q2 $end
-$var wire 1 se error_vswitch1 $end
-$var wire 1 te error_vswitch2 $end
-$var wire 1 ue error_vswitch3 $end
-$var wire 1 ve error_vswitch4 $end
-$var wire 1 we error_vswitch5 $end
-$var wire 1 xe functional_mode_amux $end
-$var wire 1 ye hld_h_n_buf $end
-$var wire 1 ze hld_ovr_buf $end
-$var wire 1 {e ib_mode_sel_buf $end
-$var wire 1 |e inp_dis_buf $end
-$var wire 1 }e invalid_controls_amux $end
-$var wire 1 ~e oe_n_buf $end
-$var wire 1 !f out_buf $end
-$var wire 1 "f pad_tristate $end
-$var wire 1 #f pwr_good_active_mode $end
-$var wire 1 $f pwr_good_active_mode_vdda $end
-$var wire 1 %f pwr_good_amux $end
-$var wire 1 &f pwr_good_analog_en_vdda $end
-$var wire 1 'f pwr_good_analog_en_vddio_q $end
-$var wire 1 (f pwr_good_analog_en_vswitch $end
-$var wire 1 )f pwr_good_hold_mode $end
-$var wire 1 *f pwr_good_hold_mode_vdda $end
-$var wire 1 +f pwr_good_hold_ovr_mode $end
-$var wire 1 ,f pwr_good_inpbuff_hv $end
-$var wire 1 -f pwr_good_inpbuff_lv $end
-$var wire 1 .f pwr_good_output_driver $end
-$var wire 1 /f slow_buf $end
-$var wire 1 0f vtrip_sel_buf $end
-$var wire 1 1f x_on_analog_en_vdda $end
-$var wire 1 2f x_on_analog_en_vddio_q $end
-$var wire 1 3f x_on_analog_en_vswitch $end
-$var wire 1 4f x_on_in_hv $end
-$var wire 1 5f x_on_in_lv $end
-$var wire 1 6f x_on_pad $end
-$var wire 1 7f zero_on_analog_en_vdda $end
-$var wire 1 8f zero_on_analog_en_vddio_q $end
-$var wire 1 9f zero_on_analog_en_vswitch $end
-$var wire 1 :f pwr_good_amux_vccd $end
-$var wire 1 ;f enable_pad_vssio_q $end
-$var wire 1 <f enable_pad_vddio_q $end
-$var wire 1 =f enable_pad_amuxbus_b $end
-$var wire 1 >f enable_pad_amuxbus_a $end
-$var wire 1 ?f disable_inp_buff_lv $end
-$var wire 1 @f disable_inp_buff $end
-$var wire 3 Af amux_select [2:0] $end
-$var wire 1 Xe TIE_LO_ESD $end
-$var wire 1 Ye TIE_HI_ESD $end
-$var wire 1 Ze IN_H $end
-$var wire 1 [e IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 Bf analog_en_final $end
-$var reg 1 Cf analog_en_vdda $end
-$var reg 1 Df analog_en_vddio_q $end
-$var reg 1 Ef analog_en_vswitch $end
-$var reg 1 Ff dis_err_msgs $end
-$var reg 3 Gf dm_final [2:0] $end
-$var reg 1 Hf hld_ovr_final $end
-$var reg 1 If ib_mode_sel_final $end
-$var reg 1 Jf inp_dis_final $end
-$var reg 1 Kf notifier_dm $end
-$var reg 1 Lf notifier_enable_h $end
-$var reg 1 Mf notifier_hld_ovr $end
-$var reg 1 Nf notifier_ib_mode_sel $end
-$var reg 1 Of notifier_inp_dis $end
-$var reg 1 Pf notifier_oe_n $end
-$var reg 1 Qf notifier_out $end
-$var reg 1 Rf notifier_slow $end
-$var reg 1 Sf notifier_vtrip_sel $end
-$var reg 1 Tf oe_n_final $end
-$var reg 1 Uf out_final $end
-$var reg 1 Vf slow_final $end
-$var reg 1 Wf vtrip_sel_final $end
-$var integer 32 Xf msg_count_pad [31:0] $end
-$var integer 32 Yf msg_count_pad1 [31:0] $end
-$var integer 32 Zf msg_count_pad10 [31:0] $end
-$var integer 32 [f msg_count_pad11 [31:0] $end
-$var integer 32 \f msg_count_pad12 [31:0] $end
-$var integer 32 ]f msg_count_pad2 [31:0] $end
-$var integer 32 ^f msg_count_pad3 [31:0] $end
-$var integer 32 _f msg_count_pad4 [31:0] $end
-$var integer 32 `f msg_count_pad5 [31:0] $end
-$var integer 32 af msg_count_pad6 [31:0] $end
-$var integer 32 bf msg_count_pad7 [31:0] $end
-$var integer 32 cf msg_count_pad8 [31:0] $end
-$var integer 32 df msg_count_pad9 [31:0] $end
-$var integer 32 ef slow_0_delay [31:0] $end
-$var integer 32 ff slow_1_delay [31:0] $end
-$var integer 32 gf slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area2_io_pad[5] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 hf ANALOG_EN $end
-$var wire 1 if ANALOG_POL $end
-$var wire 1 jf ANALOG_SEL $end
-$var wire 3 kf DM [2:0] $end
-$var wire 1 lf ENABLE_H $end
-$var wire 1 mf ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 nf HLD_H_N $end
-$var wire 1 of HLD_OVR $end
-$var wire 1 pf IB_MODE_SEL $end
-$var wire 1 qf INP_DIS $end
-$var wire 1 rf OE_N $end
-$var wire 1 sf OUT $end
-$var wire 1 tf PAD $end
-$var wire 1 uf PAD_A_ESD_0_H $end
-$var wire 1 vf PAD_A_ESD_1_H $end
-$var wire 1 wf PAD_A_NOESD_H $end
-$var wire 1 xf SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 yf VTRIP_SEL $end
-$var wire 1 zf TIE_LO_ESD $end
-$var wire 1 {f TIE_HI_ESD $end
-$var wire 1 |f IN_H $end
-$var wire 1 }f IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 ~f event_error_vswitch5 $end
-$var event 1 !g event_error_vswitch4 $end
-$var event 1 "g event_error_vswitch3 $end
-$var event 1 #g event_error_vswitch2 $end
-$var event 1 $g event_error_vswitch1 $end
-$var event 1 %g event_error_vddio_q2 $end
-$var event 1 &g event_error_vddio_q1 $end
-$var event 1 'g event_error_vdda_vddioq_vswitch2 $end
-$var event 1 (g event_error_vdda3 $end
-$var event 1 )g event_error_vdda2 $end
-$var event 1 *g event_error_vdda $end
-$var event 1 +g event_error_supply_good $end
-$var event 1 ,g event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 hf ANALOG_EN $end
-$var wire 1 if ANALOG_POL $end
-$var wire 1 jf ANALOG_SEL $end
-$var wire 3 -g DM [2:0] $end
-$var wire 1 lf ENABLE_H $end
-$var wire 1 mf ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 nf HLD_H_N $end
-$var wire 1 of HLD_OVR $end
-$var wire 1 pf IB_MODE_SEL $end
-$var wire 1 qf INP_DIS $end
-$var wire 1 rf OE_N $end
-$var wire 1 sf OUT $end
-$var wire 1 tf PAD $end
-$var wire 1 uf PAD_A_ESD_0_H $end
-$var wire 1 vf PAD_A_ESD_1_H $end
-$var wire 1 wf PAD_A_NOESD_H $end
-$var wire 1 xf SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 yf VTRIP_SEL $end
-$var wire 3 .g dm_buf [2:0] $end
-$var wire 1 /g error_enable_vddio $end
-$var wire 1 0g error_supply_good $end
-$var wire 1 1g error_vdda $end
-$var wire 1 2g error_vdda2 $end
-$var wire 1 3g error_vdda3 $end
-$var wire 1 4g error_vdda_vddioq_vswitch2 $end
-$var wire 1 5g error_vddio_q1 $end
-$var wire 1 6g error_vddio_q2 $end
-$var wire 1 7g error_vswitch1 $end
-$var wire 1 8g error_vswitch2 $end
-$var wire 1 9g error_vswitch3 $end
-$var wire 1 :g error_vswitch4 $end
-$var wire 1 ;g error_vswitch5 $end
-$var wire 1 <g functional_mode_amux $end
-$var wire 1 =g hld_h_n_buf $end
-$var wire 1 >g hld_ovr_buf $end
-$var wire 1 ?g ib_mode_sel_buf $end
-$var wire 1 @g inp_dis_buf $end
-$var wire 1 Ag invalid_controls_amux $end
-$var wire 1 Bg oe_n_buf $end
-$var wire 1 Cg out_buf $end
-$var wire 1 Dg pad_tristate $end
-$var wire 1 Eg pwr_good_active_mode $end
-$var wire 1 Fg pwr_good_active_mode_vdda $end
-$var wire 1 Gg pwr_good_amux $end
-$var wire 1 Hg pwr_good_analog_en_vdda $end
-$var wire 1 Ig pwr_good_analog_en_vddio_q $end
-$var wire 1 Jg pwr_good_analog_en_vswitch $end
-$var wire 1 Kg pwr_good_hold_mode $end
-$var wire 1 Lg pwr_good_hold_mode_vdda $end
-$var wire 1 Mg pwr_good_hold_ovr_mode $end
-$var wire 1 Ng pwr_good_inpbuff_hv $end
-$var wire 1 Og pwr_good_inpbuff_lv $end
-$var wire 1 Pg pwr_good_output_driver $end
-$var wire 1 Qg slow_buf $end
-$var wire 1 Rg vtrip_sel_buf $end
-$var wire 1 Sg x_on_analog_en_vdda $end
-$var wire 1 Tg x_on_analog_en_vddio_q $end
-$var wire 1 Ug x_on_analog_en_vswitch $end
-$var wire 1 Vg x_on_in_hv $end
-$var wire 1 Wg x_on_in_lv $end
-$var wire 1 Xg x_on_pad $end
-$var wire 1 Yg zero_on_analog_en_vdda $end
-$var wire 1 Zg zero_on_analog_en_vddio_q $end
-$var wire 1 [g zero_on_analog_en_vswitch $end
-$var wire 1 \g pwr_good_amux_vccd $end
-$var wire 1 ]g enable_pad_vssio_q $end
-$var wire 1 ^g enable_pad_vddio_q $end
-$var wire 1 _g enable_pad_amuxbus_b $end
-$var wire 1 `g enable_pad_amuxbus_a $end
-$var wire 1 ag disable_inp_buff_lv $end
-$var wire 1 bg disable_inp_buff $end
-$var wire 3 cg amux_select [2:0] $end
-$var wire 1 zf TIE_LO_ESD $end
-$var wire 1 {f TIE_HI_ESD $end
-$var wire 1 |f IN_H $end
-$var wire 1 }f IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 dg analog_en_final $end
-$var reg 1 eg analog_en_vdda $end
-$var reg 1 fg analog_en_vddio_q $end
-$var reg 1 gg analog_en_vswitch $end
-$var reg 1 hg dis_err_msgs $end
-$var reg 3 ig dm_final [2:0] $end
-$var reg 1 jg hld_ovr_final $end
-$var reg 1 kg ib_mode_sel_final $end
-$var reg 1 lg inp_dis_final $end
-$var reg 1 mg notifier_dm $end
-$var reg 1 ng notifier_enable_h $end
-$var reg 1 og notifier_hld_ovr $end
-$var reg 1 pg notifier_ib_mode_sel $end
-$var reg 1 qg notifier_inp_dis $end
-$var reg 1 rg notifier_oe_n $end
-$var reg 1 sg notifier_out $end
-$var reg 1 tg notifier_slow $end
-$var reg 1 ug notifier_vtrip_sel $end
-$var reg 1 vg oe_n_final $end
-$var reg 1 wg out_final $end
-$var reg 1 xg slow_final $end
-$var reg 1 yg vtrip_sel_final $end
-$var integer 32 zg msg_count_pad [31:0] $end
-$var integer 32 {g msg_count_pad1 [31:0] $end
-$var integer 32 |g msg_count_pad10 [31:0] $end
-$var integer 32 }g msg_count_pad11 [31:0] $end
-$var integer 32 ~g msg_count_pad12 [31:0] $end
-$var integer 32 !h msg_count_pad2 [31:0] $end
-$var integer 32 "h msg_count_pad3 [31:0] $end
-$var integer 32 #h msg_count_pad4 [31:0] $end
-$var integer 32 $h msg_count_pad5 [31:0] $end
-$var integer 32 %h msg_count_pad6 [31:0] $end
-$var integer 32 &h msg_count_pad7 [31:0] $end
-$var integer 32 'h msg_count_pad8 [31:0] $end
-$var integer 32 (h msg_count_pad9 [31:0] $end
-$var integer 32 )h slow_0_delay [31:0] $end
-$var integer 32 *h slow_1_delay [31:0] $end
-$var integer 32 +h slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area2_io_pad[6] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ,h ANALOG_EN $end
-$var wire 1 -h ANALOG_POL $end
-$var wire 1 .h ANALOG_SEL $end
-$var wire 3 /h DM [2:0] $end
-$var wire 1 0h ENABLE_H $end
-$var wire 1 1h ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 2h HLD_H_N $end
-$var wire 1 3h HLD_OVR $end
-$var wire 1 4h IB_MODE_SEL $end
-$var wire 1 5h INP_DIS $end
-$var wire 1 6h OE_N $end
-$var wire 1 7h OUT $end
-$var wire 1 8h PAD $end
-$var wire 1 9h PAD_A_ESD_0_H $end
-$var wire 1 :h PAD_A_ESD_1_H $end
-$var wire 1 ;h PAD_A_NOESD_H $end
-$var wire 1 <h SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 =h VTRIP_SEL $end
-$var wire 1 >h TIE_LO_ESD $end
-$var wire 1 ?h TIE_HI_ESD $end
-$var wire 1 @h IN_H $end
-$var wire 1 Ah IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 Bh event_error_vswitch5 $end
-$var event 1 Ch event_error_vswitch4 $end
-$var event 1 Dh event_error_vswitch3 $end
-$var event 1 Eh event_error_vswitch2 $end
-$var event 1 Fh event_error_vswitch1 $end
-$var event 1 Gh event_error_vddio_q2 $end
-$var event 1 Hh event_error_vddio_q1 $end
-$var event 1 Ih event_error_vdda_vddioq_vswitch2 $end
-$var event 1 Jh event_error_vdda3 $end
-$var event 1 Kh event_error_vdda2 $end
-$var event 1 Lh event_error_vdda $end
-$var event 1 Mh event_error_supply_good $end
-$var event 1 Nh event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 ,h ANALOG_EN $end
-$var wire 1 -h ANALOG_POL $end
-$var wire 1 .h ANALOG_SEL $end
-$var wire 3 Oh DM [2:0] $end
-$var wire 1 0h ENABLE_H $end
-$var wire 1 1h ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 2h HLD_H_N $end
-$var wire 1 3h HLD_OVR $end
-$var wire 1 4h IB_MODE_SEL $end
-$var wire 1 5h INP_DIS $end
-$var wire 1 6h OE_N $end
-$var wire 1 7h OUT $end
-$var wire 1 8h PAD $end
-$var wire 1 9h PAD_A_ESD_0_H $end
-$var wire 1 :h PAD_A_ESD_1_H $end
-$var wire 1 ;h PAD_A_NOESD_H $end
-$var wire 1 <h SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 =h VTRIP_SEL $end
-$var wire 3 Ph dm_buf [2:0] $end
-$var wire 1 Qh error_enable_vddio $end
-$var wire 1 Rh error_supply_good $end
-$var wire 1 Sh error_vdda $end
-$var wire 1 Th error_vdda2 $end
-$var wire 1 Uh error_vdda3 $end
-$var wire 1 Vh error_vdda_vddioq_vswitch2 $end
-$var wire 1 Wh error_vddio_q1 $end
-$var wire 1 Xh error_vddio_q2 $end
-$var wire 1 Yh error_vswitch1 $end
-$var wire 1 Zh error_vswitch2 $end
-$var wire 1 [h error_vswitch3 $end
-$var wire 1 \h error_vswitch4 $end
-$var wire 1 ]h error_vswitch5 $end
-$var wire 1 ^h functional_mode_amux $end
-$var wire 1 _h hld_h_n_buf $end
-$var wire 1 `h hld_ovr_buf $end
-$var wire 1 ah ib_mode_sel_buf $end
-$var wire 1 bh inp_dis_buf $end
-$var wire 1 ch invalid_controls_amux $end
-$var wire 1 dh oe_n_buf $end
-$var wire 1 eh out_buf $end
-$var wire 1 fh pad_tristate $end
-$var wire 1 gh pwr_good_active_mode $end
-$var wire 1 hh pwr_good_active_mode_vdda $end
-$var wire 1 ih pwr_good_amux $end
-$var wire 1 jh pwr_good_analog_en_vdda $end
-$var wire 1 kh pwr_good_analog_en_vddio_q $end
-$var wire 1 lh pwr_good_analog_en_vswitch $end
-$var wire 1 mh pwr_good_hold_mode $end
-$var wire 1 nh pwr_good_hold_mode_vdda $end
-$var wire 1 oh pwr_good_hold_ovr_mode $end
-$var wire 1 ph pwr_good_inpbuff_hv $end
-$var wire 1 qh pwr_good_inpbuff_lv $end
-$var wire 1 rh pwr_good_output_driver $end
-$var wire 1 sh slow_buf $end
-$var wire 1 th vtrip_sel_buf $end
-$var wire 1 uh x_on_analog_en_vdda $end
-$var wire 1 vh x_on_analog_en_vddio_q $end
-$var wire 1 wh x_on_analog_en_vswitch $end
-$var wire 1 xh x_on_in_hv $end
-$var wire 1 yh x_on_in_lv $end
-$var wire 1 zh x_on_pad $end
-$var wire 1 {h zero_on_analog_en_vdda $end
-$var wire 1 |h zero_on_analog_en_vddio_q $end
-$var wire 1 }h zero_on_analog_en_vswitch $end
-$var wire 1 ~h pwr_good_amux_vccd $end
-$var wire 1 !i enable_pad_vssio_q $end
-$var wire 1 "i enable_pad_vddio_q $end
-$var wire 1 #i enable_pad_amuxbus_b $end
-$var wire 1 $i enable_pad_amuxbus_a $end
-$var wire 1 %i disable_inp_buff_lv $end
-$var wire 1 &i disable_inp_buff $end
-$var wire 3 'i amux_select [2:0] $end
-$var wire 1 >h TIE_LO_ESD $end
-$var wire 1 ?h TIE_HI_ESD $end
-$var wire 1 @h IN_H $end
-$var wire 1 Ah IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 (i analog_en_final $end
-$var reg 1 )i analog_en_vdda $end
-$var reg 1 *i analog_en_vddio_q $end
-$var reg 1 +i analog_en_vswitch $end
-$var reg 1 ,i dis_err_msgs $end
-$var reg 3 -i dm_final [2:0] $end
-$var reg 1 .i hld_ovr_final $end
-$var reg 1 /i ib_mode_sel_final $end
-$var reg 1 0i inp_dis_final $end
-$var reg 1 1i notifier_dm $end
-$var reg 1 2i notifier_enable_h $end
-$var reg 1 3i notifier_hld_ovr $end
-$var reg 1 4i notifier_ib_mode_sel $end
-$var reg 1 5i notifier_inp_dis $end
-$var reg 1 6i notifier_oe_n $end
-$var reg 1 7i notifier_out $end
-$var reg 1 8i notifier_slow $end
-$var reg 1 9i notifier_vtrip_sel $end
-$var reg 1 :i oe_n_final $end
-$var reg 1 ;i out_final $end
-$var reg 1 <i slow_final $end
-$var reg 1 =i vtrip_sel_final $end
-$var integer 32 >i msg_count_pad [31:0] $end
-$var integer 32 ?i msg_count_pad1 [31:0] $end
-$var integer 32 @i msg_count_pad10 [31:0] $end
-$var integer 32 Ai msg_count_pad11 [31:0] $end
-$var integer 32 Bi msg_count_pad12 [31:0] $end
-$var integer 32 Ci msg_count_pad2 [31:0] $end
-$var integer 32 Di msg_count_pad3 [31:0] $end
-$var integer 32 Ei msg_count_pad4 [31:0] $end
-$var integer 32 Fi msg_count_pad5 [31:0] $end
-$var integer 32 Gi msg_count_pad6 [31:0] $end
-$var integer 32 Hi msg_count_pad7 [31:0] $end
-$var integer 32 Ii msg_count_pad8 [31:0] $end
-$var integer 32 Ji msg_count_pad9 [31:0] $end
-$var integer 32 Ki slow_0_delay [31:0] $end
-$var integer 32 Li slow_1_delay [31:0] $end
-$var integer 32 Mi slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area2_io_pad[7] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 Ni ANALOG_EN $end
-$var wire 1 Oi ANALOG_POL $end
-$var wire 1 Pi ANALOG_SEL $end
-$var wire 3 Qi DM [2:0] $end
-$var wire 1 Ri ENABLE_H $end
-$var wire 1 Si ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 Ti HLD_H_N $end
-$var wire 1 Ui HLD_OVR $end
-$var wire 1 Vi IB_MODE_SEL $end
-$var wire 1 Wi INP_DIS $end
-$var wire 1 Xi OE_N $end
-$var wire 1 Yi OUT $end
-$var wire 1 Zi PAD $end
-$var wire 1 [i PAD_A_ESD_0_H $end
-$var wire 1 \i PAD_A_ESD_1_H $end
-$var wire 1 ]i PAD_A_NOESD_H $end
-$var wire 1 ^i SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 _i VTRIP_SEL $end
-$var wire 1 `i TIE_LO_ESD $end
-$var wire 1 ai TIE_HI_ESD $end
-$var wire 1 bi IN_H $end
-$var wire 1 ci IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 di event_error_vswitch5 $end
-$var event 1 ei event_error_vswitch4 $end
-$var event 1 fi event_error_vswitch3 $end
-$var event 1 gi event_error_vswitch2 $end
-$var event 1 hi event_error_vswitch1 $end
-$var event 1 ii event_error_vddio_q2 $end
-$var event 1 ji event_error_vddio_q1 $end
-$var event 1 ki event_error_vdda_vddioq_vswitch2 $end
-$var event 1 li event_error_vdda3 $end
-$var event 1 mi event_error_vdda2 $end
-$var event 1 ni event_error_vdda $end
-$var event 1 oi event_error_supply_good $end
-$var event 1 pi event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 Ni ANALOG_EN $end
-$var wire 1 Oi ANALOG_POL $end
-$var wire 1 Pi ANALOG_SEL $end
-$var wire 3 qi DM [2:0] $end
-$var wire 1 Ri ENABLE_H $end
-$var wire 1 Si ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 Ti HLD_H_N $end
-$var wire 1 Ui HLD_OVR $end
-$var wire 1 Vi IB_MODE_SEL $end
-$var wire 1 Wi INP_DIS $end
-$var wire 1 Xi OE_N $end
-$var wire 1 Yi OUT $end
-$var wire 1 Zi PAD $end
-$var wire 1 [i PAD_A_ESD_0_H $end
-$var wire 1 \i PAD_A_ESD_1_H $end
-$var wire 1 ]i PAD_A_NOESD_H $end
-$var wire 1 ^i SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 _i VTRIP_SEL $end
-$var wire 3 ri dm_buf [2:0] $end
-$var wire 1 si error_enable_vddio $end
-$var wire 1 ti error_supply_good $end
-$var wire 1 ui error_vdda $end
-$var wire 1 vi error_vdda2 $end
-$var wire 1 wi error_vdda3 $end
-$var wire 1 xi error_vdda_vddioq_vswitch2 $end
-$var wire 1 yi error_vddio_q1 $end
-$var wire 1 zi error_vddio_q2 $end
-$var wire 1 {i error_vswitch1 $end
-$var wire 1 |i error_vswitch2 $end
-$var wire 1 }i error_vswitch3 $end
-$var wire 1 ~i error_vswitch4 $end
-$var wire 1 !j error_vswitch5 $end
-$var wire 1 "j functional_mode_amux $end
-$var wire 1 #j hld_h_n_buf $end
-$var wire 1 $j hld_ovr_buf $end
-$var wire 1 %j ib_mode_sel_buf $end
-$var wire 1 &j inp_dis_buf $end
-$var wire 1 'j invalid_controls_amux $end
-$var wire 1 (j oe_n_buf $end
-$var wire 1 )j out_buf $end
-$var wire 1 *j pad_tristate $end
-$var wire 1 +j pwr_good_active_mode $end
-$var wire 1 ,j pwr_good_active_mode_vdda $end
-$var wire 1 -j pwr_good_amux $end
-$var wire 1 .j pwr_good_analog_en_vdda $end
-$var wire 1 /j pwr_good_analog_en_vddio_q $end
-$var wire 1 0j pwr_good_analog_en_vswitch $end
-$var wire 1 1j pwr_good_hold_mode $end
-$var wire 1 2j pwr_good_hold_mode_vdda $end
-$var wire 1 3j pwr_good_hold_ovr_mode $end
-$var wire 1 4j pwr_good_inpbuff_hv $end
-$var wire 1 5j pwr_good_inpbuff_lv $end
-$var wire 1 6j pwr_good_output_driver $end
-$var wire 1 7j slow_buf $end
-$var wire 1 8j vtrip_sel_buf $end
-$var wire 1 9j x_on_analog_en_vdda $end
-$var wire 1 :j x_on_analog_en_vddio_q $end
-$var wire 1 ;j x_on_analog_en_vswitch $end
-$var wire 1 <j x_on_in_hv $end
-$var wire 1 =j x_on_in_lv $end
-$var wire 1 >j x_on_pad $end
-$var wire 1 ?j zero_on_analog_en_vdda $end
-$var wire 1 @j zero_on_analog_en_vddio_q $end
-$var wire 1 Aj zero_on_analog_en_vswitch $end
-$var wire 1 Bj pwr_good_amux_vccd $end
-$var wire 1 Cj enable_pad_vssio_q $end
-$var wire 1 Dj enable_pad_vddio_q $end
-$var wire 1 Ej enable_pad_amuxbus_b $end
-$var wire 1 Fj enable_pad_amuxbus_a $end
-$var wire 1 Gj disable_inp_buff_lv $end
-$var wire 1 Hj disable_inp_buff $end
-$var wire 3 Ij amux_select [2:0] $end
-$var wire 1 `i TIE_LO_ESD $end
-$var wire 1 ai TIE_HI_ESD $end
-$var wire 1 bi IN_H $end
-$var wire 1 ci IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 Jj analog_en_final $end
-$var reg 1 Kj analog_en_vdda $end
-$var reg 1 Lj analog_en_vddio_q $end
-$var reg 1 Mj analog_en_vswitch $end
-$var reg 1 Nj dis_err_msgs $end
-$var reg 3 Oj dm_final [2:0] $end
-$var reg 1 Pj hld_ovr_final $end
-$var reg 1 Qj ib_mode_sel_final $end
-$var reg 1 Rj inp_dis_final $end
-$var reg 1 Sj notifier_dm $end
-$var reg 1 Tj notifier_enable_h $end
-$var reg 1 Uj notifier_hld_ovr $end
-$var reg 1 Vj notifier_ib_mode_sel $end
-$var reg 1 Wj notifier_inp_dis $end
-$var reg 1 Xj notifier_oe_n $end
-$var reg 1 Yj notifier_out $end
-$var reg 1 Zj notifier_slow $end
-$var reg 1 [j notifier_vtrip_sel $end
-$var reg 1 \j oe_n_final $end
-$var reg 1 ]j out_final $end
-$var reg 1 ^j slow_final $end
-$var reg 1 _j vtrip_sel_final $end
-$var integer 32 `j msg_count_pad [31:0] $end
-$var integer 32 aj msg_count_pad1 [31:0] $end
-$var integer 32 bj msg_count_pad10 [31:0] $end
-$var integer 32 cj msg_count_pad11 [31:0] $end
-$var integer 32 dj msg_count_pad12 [31:0] $end
-$var integer 32 ej msg_count_pad2 [31:0] $end
-$var integer 32 fj msg_count_pad3 [31:0] $end
-$var integer 32 gj msg_count_pad4 [31:0] $end
-$var integer 32 hj msg_count_pad5 [31:0] $end
-$var integer 32 ij msg_count_pad6 [31:0] $end
-$var integer 32 jj msg_count_pad7 [31:0] $end
-$var integer 32 kj msg_count_pad8 [31:0] $end
-$var integer 32 lj msg_count_pad9 [31:0] $end
-$var integer 32 mj slow_0_delay [31:0] $end
-$var integer 32 nj slow_1_delay [31:0] $end
-$var integer 32 oj slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area2_io_pad[8] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 pj ANALOG_EN $end
-$var wire 1 qj ANALOG_POL $end
-$var wire 1 rj ANALOG_SEL $end
-$var wire 3 sj DM [2:0] $end
-$var wire 1 tj ENABLE_H $end
-$var wire 1 uj ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 vj HLD_H_N $end
-$var wire 1 wj HLD_OVR $end
-$var wire 1 xj IB_MODE_SEL $end
-$var wire 1 yj INP_DIS $end
-$var wire 1 zj OE_N $end
-$var wire 1 {j OUT $end
-$var wire 1 |j PAD $end
-$var wire 1 }j PAD_A_ESD_0_H $end
-$var wire 1 ~j PAD_A_ESD_1_H $end
-$var wire 1 !k PAD_A_NOESD_H $end
-$var wire 1 "k SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 #k VTRIP_SEL $end
-$var wire 1 $k TIE_LO_ESD $end
-$var wire 1 %k TIE_HI_ESD $end
-$var wire 1 &k IN_H $end
-$var wire 1 'k IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 (k event_error_vswitch5 $end
-$var event 1 )k event_error_vswitch4 $end
-$var event 1 *k event_error_vswitch3 $end
-$var event 1 +k event_error_vswitch2 $end
-$var event 1 ,k event_error_vswitch1 $end
-$var event 1 -k event_error_vddio_q2 $end
-$var event 1 .k event_error_vddio_q1 $end
-$var event 1 /k event_error_vdda_vddioq_vswitch2 $end
-$var event 1 0k event_error_vdda3 $end
-$var event 1 1k event_error_vdda2 $end
-$var event 1 2k event_error_vdda $end
-$var event 1 3k event_error_supply_good $end
-$var event 1 4k event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 pj ANALOG_EN $end
-$var wire 1 qj ANALOG_POL $end
-$var wire 1 rj ANALOG_SEL $end
-$var wire 3 5k DM [2:0] $end
-$var wire 1 tj ENABLE_H $end
-$var wire 1 uj ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 vj HLD_H_N $end
-$var wire 1 wj HLD_OVR $end
-$var wire 1 xj IB_MODE_SEL $end
-$var wire 1 yj INP_DIS $end
-$var wire 1 zj OE_N $end
-$var wire 1 {j OUT $end
-$var wire 1 |j PAD $end
-$var wire 1 }j PAD_A_ESD_0_H $end
-$var wire 1 ~j PAD_A_ESD_1_H $end
-$var wire 1 !k PAD_A_NOESD_H $end
-$var wire 1 "k SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 #k VTRIP_SEL $end
-$var wire 3 6k dm_buf [2:0] $end
-$var wire 1 7k error_enable_vddio $end
-$var wire 1 8k error_supply_good $end
-$var wire 1 9k error_vdda $end
-$var wire 1 :k error_vdda2 $end
-$var wire 1 ;k error_vdda3 $end
-$var wire 1 <k error_vdda_vddioq_vswitch2 $end
-$var wire 1 =k error_vddio_q1 $end
-$var wire 1 >k error_vddio_q2 $end
-$var wire 1 ?k error_vswitch1 $end
-$var wire 1 @k error_vswitch2 $end
-$var wire 1 Ak error_vswitch3 $end
-$var wire 1 Bk error_vswitch4 $end
-$var wire 1 Ck error_vswitch5 $end
-$var wire 1 Dk functional_mode_amux $end
-$var wire 1 Ek hld_h_n_buf $end
-$var wire 1 Fk hld_ovr_buf $end
-$var wire 1 Gk ib_mode_sel_buf $end
-$var wire 1 Hk inp_dis_buf $end
-$var wire 1 Ik invalid_controls_amux $end
-$var wire 1 Jk oe_n_buf $end
-$var wire 1 Kk out_buf $end
-$var wire 1 Lk pad_tristate $end
-$var wire 1 Mk pwr_good_active_mode $end
-$var wire 1 Nk pwr_good_active_mode_vdda $end
-$var wire 1 Ok pwr_good_amux $end
-$var wire 1 Pk pwr_good_analog_en_vdda $end
-$var wire 1 Qk pwr_good_analog_en_vddio_q $end
-$var wire 1 Rk pwr_good_analog_en_vswitch $end
-$var wire 1 Sk pwr_good_hold_mode $end
-$var wire 1 Tk pwr_good_hold_mode_vdda $end
-$var wire 1 Uk pwr_good_hold_ovr_mode $end
-$var wire 1 Vk pwr_good_inpbuff_hv $end
-$var wire 1 Wk pwr_good_inpbuff_lv $end
-$var wire 1 Xk pwr_good_output_driver $end
-$var wire 1 Yk slow_buf $end
-$var wire 1 Zk vtrip_sel_buf $end
-$var wire 1 [k x_on_analog_en_vdda $end
-$var wire 1 \k x_on_analog_en_vddio_q $end
-$var wire 1 ]k x_on_analog_en_vswitch $end
-$var wire 1 ^k x_on_in_hv $end
-$var wire 1 _k x_on_in_lv $end
-$var wire 1 `k x_on_pad $end
-$var wire 1 ak zero_on_analog_en_vdda $end
-$var wire 1 bk zero_on_analog_en_vddio_q $end
-$var wire 1 ck zero_on_analog_en_vswitch $end
-$var wire 1 dk pwr_good_amux_vccd $end
-$var wire 1 ek enable_pad_vssio_q $end
-$var wire 1 fk enable_pad_vddio_q $end
-$var wire 1 gk enable_pad_amuxbus_b $end
-$var wire 1 hk enable_pad_amuxbus_a $end
-$var wire 1 ik disable_inp_buff_lv $end
-$var wire 1 jk disable_inp_buff $end
-$var wire 3 kk amux_select [2:0] $end
-$var wire 1 $k TIE_LO_ESD $end
-$var wire 1 %k TIE_HI_ESD $end
-$var wire 1 &k IN_H $end
-$var wire 1 'k IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 lk analog_en_final $end
-$var reg 1 mk analog_en_vdda $end
-$var reg 1 nk analog_en_vddio_q $end
-$var reg 1 ok analog_en_vswitch $end
-$var reg 1 pk dis_err_msgs $end
-$var reg 3 qk dm_final [2:0] $end
-$var reg 1 rk hld_ovr_final $end
-$var reg 1 sk ib_mode_sel_final $end
-$var reg 1 tk inp_dis_final $end
-$var reg 1 uk notifier_dm $end
-$var reg 1 vk notifier_enable_h $end
-$var reg 1 wk notifier_hld_ovr $end
-$var reg 1 xk notifier_ib_mode_sel $end
-$var reg 1 yk notifier_inp_dis $end
-$var reg 1 zk notifier_oe_n $end
-$var reg 1 {k notifier_out $end
-$var reg 1 |k notifier_slow $end
-$var reg 1 }k notifier_vtrip_sel $end
-$var reg 1 ~k oe_n_final $end
-$var reg 1 !l out_final $end
-$var reg 1 "l slow_final $end
-$var reg 1 #l vtrip_sel_final $end
-$var integer 32 $l msg_count_pad [31:0] $end
-$var integer 32 %l msg_count_pad1 [31:0] $end
-$var integer 32 &l msg_count_pad10 [31:0] $end
-$var integer 32 'l msg_count_pad11 [31:0] $end
-$var integer 32 (l msg_count_pad12 [31:0] $end
-$var integer 32 )l msg_count_pad2 [31:0] $end
-$var integer 32 *l msg_count_pad3 [31:0] $end
-$var integer 32 +l msg_count_pad4 [31:0] $end
-$var integer 32 ,l msg_count_pad5 [31:0] $end
-$var integer 32 -l msg_count_pad6 [31:0] $end
-$var integer 32 .l msg_count_pad7 [31:0] $end
-$var integer 32 /l msg_count_pad8 [31:0] $end
-$var integer 32 0l msg_count_pad9 [31:0] $end
-$var integer 32 1l slow_0_delay [31:0] $end
-$var integer 32 2l slow_1_delay [31:0] $end
-$var integer 32 3l slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area2_io_pad[9] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 4l ANALOG_EN $end
-$var wire 1 5l ANALOG_POL $end
-$var wire 1 6l ANALOG_SEL $end
-$var wire 3 7l DM [2:0] $end
-$var wire 1 8l ENABLE_H $end
-$var wire 1 9l ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 :l HLD_H_N $end
-$var wire 1 ;l HLD_OVR $end
-$var wire 1 <l IB_MODE_SEL $end
-$var wire 1 =l INP_DIS $end
-$var wire 1 >l OE_N $end
-$var wire 1 ?l OUT $end
-$var wire 1 @l PAD $end
-$var wire 1 Al PAD_A_ESD_0_H $end
-$var wire 1 Bl PAD_A_ESD_1_H $end
-$var wire 1 Cl PAD_A_NOESD_H $end
-$var wire 1 Dl SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 El VTRIP_SEL $end
-$var wire 1 Fl TIE_LO_ESD $end
-$var wire 1 Gl TIE_HI_ESD $end
-$var wire 1 Hl IN_H $end
-$var wire 1 Il IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 Jl event_error_vswitch5 $end
-$var event 1 Kl event_error_vswitch4 $end
-$var event 1 Ll event_error_vswitch3 $end
-$var event 1 Ml event_error_vswitch2 $end
-$var event 1 Nl event_error_vswitch1 $end
-$var event 1 Ol event_error_vddio_q2 $end
-$var event 1 Pl event_error_vddio_q1 $end
-$var event 1 Ql event_error_vdda_vddioq_vswitch2 $end
-$var event 1 Rl event_error_vdda3 $end
-$var event 1 Sl event_error_vdda2 $end
-$var event 1 Tl event_error_vdda $end
-$var event 1 Ul event_error_supply_good $end
-$var event 1 Vl event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 4l ANALOG_EN $end
-$var wire 1 5l ANALOG_POL $end
-$var wire 1 6l ANALOG_SEL $end
-$var wire 3 Wl DM [2:0] $end
-$var wire 1 8l ENABLE_H $end
-$var wire 1 9l ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 :l HLD_H_N $end
-$var wire 1 ;l HLD_OVR $end
-$var wire 1 <l IB_MODE_SEL $end
-$var wire 1 =l INP_DIS $end
-$var wire 1 >l OE_N $end
-$var wire 1 ?l OUT $end
-$var wire 1 @l PAD $end
-$var wire 1 Al PAD_A_ESD_0_H $end
-$var wire 1 Bl PAD_A_ESD_1_H $end
-$var wire 1 Cl PAD_A_NOESD_H $end
-$var wire 1 Dl SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 El VTRIP_SEL $end
-$var wire 3 Xl dm_buf [2:0] $end
-$var wire 1 Yl error_enable_vddio $end
-$var wire 1 Zl error_supply_good $end
-$var wire 1 [l error_vdda $end
-$var wire 1 \l error_vdda2 $end
-$var wire 1 ]l error_vdda3 $end
-$var wire 1 ^l error_vdda_vddioq_vswitch2 $end
-$var wire 1 _l error_vddio_q1 $end
-$var wire 1 `l error_vddio_q2 $end
-$var wire 1 al error_vswitch1 $end
-$var wire 1 bl error_vswitch2 $end
-$var wire 1 cl error_vswitch3 $end
-$var wire 1 dl error_vswitch4 $end
-$var wire 1 el error_vswitch5 $end
-$var wire 1 fl functional_mode_amux $end
-$var wire 1 gl hld_h_n_buf $end
-$var wire 1 hl hld_ovr_buf $end
-$var wire 1 il ib_mode_sel_buf $end
-$var wire 1 jl inp_dis_buf $end
-$var wire 1 kl invalid_controls_amux $end
-$var wire 1 ll oe_n_buf $end
-$var wire 1 ml out_buf $end
-$var wire 1 nl pad_tristate $end
-$var wire 1 ol pwr_good_active_mode $end
-$var wire 1 pl pwr_good_active_mode_vdda $end
-$var wire 1 ql pwr_good_amux $end
-$var wire 1 rl pwr_good_analog_en_vdda $end
-$var wire 1 sl pwr_good_analog_en_vddio_q $end
-$var wire 1 tl pwr_good_analog_en_vswitch $end
-$var wire 1 ul pwr_good_hold_mode $end
-$var wire 1 vl pwr_good_hold_mode_vdda $end
-$var wire 1 wl pwr_good_hold_ovr_mode $end
-$var wire 1 xl pwr_good_inpbuff_hv $end
-$var wire 1 yl pwr_good_inpbuff_lv $end
-$var wire 1 zl pwr_good_output_driver $end
-$var wire 1 {l slow_buf $end
-$var wire 1 |l vtrip_sel_buf $end
-$var wire 1 }l x_on_analog_en_vdda $end
-$var wire 1 ~l x_on_analog_en_vddio_q $end
-$var wire 1 !m x_on_analog_en_vswitch $end
-$var wire 1 "m x_on_in_hv $end
-$var wire 1 #m x_on_in_lv $end
-$var wire 1 $m x_on_pad $end
-$var wire 1 %m zero_on_analog_en_vdda $end
-$var wire 1 &m zero_on_analog_en_vddio_q $end
-$var wire 1 'm zero_on_analog_en_vswitch $end
-$var wire 1 (m pwr_good_amux_vccd $end
-$var wire 1 )m enable_pad_vssio_q $end
-$var wire 1 *m enable_pad_vddio_q $end
-$var wire 1 +m enable_pad_amuxbus_b $end
-$var wire 1 ,m enable_pad_amuxbus_a $end
-$var wire 1 -m disable_inp_buff_lv $end
-$var wire 1 .m disable_inp_buff $end
-$var wire 3 /m amux_select [2:0] $end
-$var wire 1 Fl TIE_LO_ESD $end
-$var wire 1 Gl TIE_HI_ESD $end
-$var wire 1 Hl IN_H $end
-$var wire 1 Il IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 0m analog_en_final $end
-$var reg 1 1m analog_en_vdda $end
-$var reg 1 2m analog_en_vddio_q $end
-$var reg 1 3m analog_en_vswitch $end
-$var reg 1 4m dis_err_msgs $end
-$var reg 3 5m dm_final [2:0] $end
-$var reg 1 6m hld_ovr_final $end
-$var reg 1 7m ib_mode_sel_final $end
-$var reg 1 8m inp_dis_final $end
-$var reg 1 9m notifier_dm $end
-$var reg 1 :m notifier_enable_h $end
-$var reg 1 ;m notifier_hld_ovr $end
-$var reg 1 <m notifier_ib_mode_sel $end
-$var reg 1 =m notifier_inp_dis $end
-$var reg 1 >m notifier_oe_n $end
-$var reg 1 ?m notifier_out $end
-$var reg 1 @m notifier_slow $end
-$var reg 1 Am notifier_vtrip_sel $end
-$var reg 1 Bm oe_n_final $end
-$var reg 1 Cm out_final $end
-$var reg 1 Dm slow_final $end
-$var reg 1 Em vtrip_sel_final $end
-$var integer 32 Fm msg_count_pad [31:0] $end
-$var integer 32 Gm msg_count_pad1 [31:0] $end
-$var integer 32 Hm msg_count_pad10 [31:0] $end
-$var integer 32 Im msg_count_pad11 [31:0] $end
-$var integer 32 Jm msg_count_pad12 [31:0] $end
-$var integer 32 Km msg_count_pad2 [31:0] $end
-$var integer 32 Lm msg_count_pad3 [31:0] $end
-$var integer 32 Mm msg_count_pad4 [31:0] $end
-$var integer 32 Nm msg_count_pad5 [31:0] $end
-$var integer 32 Om msg_count_pad6 [31:0] $end
-$var integer 32 Pm msg_count_pad7 [31:0] $end
-$var integer 32 Qm msg_count_pad8 [31:0] $end
-$var integer 32 Rm msg_count_pad9 [31:0] $end
-$var integer 32 Sm slow_0_delay [31:0] $end
-$var integer 32 Tm slow_1_delay [31:0] $end
-$var integer 32 Um slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area2_io_pad[10] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 Vm ANALOG_EN $end
-$var wire 1 Wm ANALOG_POL $end
-$var wire 1 Xm ANALOG_SEL $end
-$var wire 3 Ym DM [2:0] $end
-$var wire 1 Zm ENABLE_H $end
-$var wire 1 [m ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 \m HLD_H_N $end
-$var wire 1 ]m HLD_OVR $end
-$var wire 1 ^m IB_MODE_SEL $end
-$var wire 1 _m INP_DIS $end
-$var wire 1 `m OE_N $end
-$var wire 1 am OUT $end
-$var wire 1 bm PAD $end
-$var wire 1 cm PAD_A_ESD_0_H $end
-$var wire 1 dm PAD_A_ESD_1_H $end
-$var wire 1 em PAD_A_NOESD_H $end
-$var wire 1 fm SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 gm VTRIP_SEL $end
-$var wire 1 hm TIE_LO_ESD $end
-$var wire 1 im TIE_HI_ESD $end
-$var wire 1 jm IN_H $end
-$var wire 1 km IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 lm event_error_vswitch5 $end
-$var event 1 mm event_error_vswitch4 $end
-$var event 1 nm event_error_vswitch3 $end
-$var event 1 om event_error_vswitch2 $end
-$var event 1 pm event_error_vswitch1 $end
-$var event 1 qm event_error_vddio_q2 $end
-$var event 1 rm event_error_vddio_q1 $end
-$var event 1 sm event_error_vdda_vddioq_vswitch2 $end
-$var event 1 tm event_error_vdda3 $end
-$var event 1 um event_error_vdda2 $end
-$var event 1 vm event_error_vdda $end
-$var event 1 wm event_error_supply_good $end
-$var event 1 xm event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 Vm ANALOG_EN $end
-$var wire 1 Wm ANALOG_POL $end
-$var wire 1 Xm ANALOG_SEL $end
-$var wire 3 ym DM [2:0] $end
-$var wire 1 Zm ENABLE_H $end
-$var wire 1 [m ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 \m HLD_H_N $end
-$var wire 1 ]m HLD_OVR $end
-$var wire 1 ^m IB_MODE_SEL $end
-$var wire 1 _m INP_DIS $end
-$var wire 1 `m OE_N $end
-$var wire 1 am OUT $end
-$var wire 1 bm PAD $end
-$var wire 1 cm PAD_A_ESD_0_H $end
-$var wire 1 dm PAD_A_ESD_1_H $end
-$var wire 1 em PAD_A_NOESD_H $end
-$var wire 1 fm SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 gm VTRIP_SEL $end
-$var wire 3 zm dm_buf [2:0] $end
-$var wire 1 {m error_enable_vddio $end
-$var wire 1 |m error_supply_good $end
-$var wire 1 }m error_vdda $end
-$var wire 1 ~m error_vdda2 $end
-$var wire 1 !n error_vdda3 $end
-$var wire 1 "n error_vdda_vddioq_vswitch2 $end
-$var wire 1 #n error_vddio_q1 $end
-$var wire 1 $n error_vddio_q2 $end
-$var wire 1 %n error_vswitch1 $end
-$var wire 1 &n error_vswitch2 $end
-$var wire 1 'n error_vswitch3 $end
-$var wire 1 (n error_vswitch4 $end
-$var wire 1 )n error_vswitch5 $end
-$var wire 1 *n functional_mode_amux $end
-$var wire 1 +n hld_h_n_buf $end
-$var wire 1 ,n hld_ovr_buf $end
-$var wire 1 -n ib_mode_sel_buf $end
-$var wire 1 .n inp_dis_buf $end
-$var wire 1 /n invalid_controls_amux $end
-$var wire 1 0n oe_n_buf $end
-$var wire 1 1n out_buf $end
-$var wire 1 2n pad_tristate $end
-$var wire 1 3n pwr_good_active_mode $end
-$var wire 1 4n pwr_good_active_mode_vdda $end
-$var wire 1 5n pwr_good_amux $end
-$var wire 1 6n pwr_good_analog_en_vdda $end
-$var wire 1 7n pwr_good_analog_en_vddio_q $end
-$var wire 1 8n pwr_good_analog_en_vswitch $end
-$var wire 1 9n pwr_good_hold_mode $end
-$var wire 1 :n pwr_good_hold_mode_vdda $end
-$var wire 1 ;n pwr_good_hold_ovr_mode $end
-$var wire 1 <n pwr_good_inpbuff_hv $end
-$var wire 1 =n pwr_good_inpbuff_lv $end
-$var wire 1 >n pwr_good_output_driver $end
-$var wire 1 ?n slow_buf $end
-$var wire 1 @n vtrip_sel_buf $end
-$var wire 1 An x_on_analog_en_vdda $end
-$var wire 1 Bn x_on_analog_en_vddio_q $end
-$var wire 1 Cn x_on_analog_en_vswitch $end
-$var wire 1 Dn x_on_in_hv $end
-$var wire 1 En x_on_in_lv $end
-$var wire 1 Fn x_on_pad $end
-$var wire 1 Gn zero_on_analog_en_vdda $end
-$var wire 1 Hn zero_on_analog_en_vddio_q $end
-$var wire 1 In zero_on_analog_en_vswitch $end
-$var wire 1 Jn pwr_good_amux_vccd $end
-$var wire 1 Kn enable_pad_vssio_q $end
-$var wire 1 Ln enable_pad_vddio_q $end
-$var wire 1 Mn enable_pad_amuxbus_b $end
-$var wire 1 Nn enable_pad_amuxbus_a $end
-$var wire 1 On disable_inp_buff_lv $end
-$var wire 1 Pn disable_inp_buff $end
-$var wire 3 Qn amux_select [2:0] $end
-$var wire 1 hm TIE_LO_ESD $end
-$var wire 1 im TIE_HI_ESD $end
-$var wire 1 jm IN_H $end
-$var wire 1 km IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 Rn analog_en_final $end
-$var reg 1 Sn analog_en_vdda $end
-$var reg 1 Tn analog_en_vddio_q $end
-$var reg 1 Un analog_en_vswitch $end
-$var reg 1 Vn dis_err_msgs $end
-$var reg 3 Wn dm_final [2:0] $end
-$var reg 1 Xn hld_ovr_final $end
-$var reg 1 Yn ib_mode_sel_final $end
-$var reg 1 Zn inp_dis_final $end
-$var reg 1 [n notifier_dm $end
-$var reg 1 \n notifier_enable_h $end
-$var reg 1 ]n notifier_hld_ovr $end
-$var reg 1 ^n notifier_ib_mode_sel $end
-$var reg 1 _n notifier_inp_dis $end
-$var reg 1 `n notifier_oe_n $end
-$var reg 1 an notifier_out $end
-$var reg 1 bn notifier_slow $end
-$var reg 1 cn notifier_vtrip_sel $end
-$var reg 1 dn oe_n_final $end
-$var reg 1 en out_final $end
-$var reg 1 fn slow_final $end
-$var reg 1 gn vtrip_sel_final $end
-$var integer 32 hn msg_count_pad [31:0] $end
-$var integer 32 in msg_count_pad1 [31:0] $end
-$var integer 32 jn msg_count_pad10 [31:0] $end
-$var integer 32 kn msg_count_pad11 [31:0] $end
-$var integer 32 ln msg_count_pad12 [31:0] $end
-$var integer 32 mn msg_count_pad2 [31:0] $end
-$var integer 32 nn msg_count_pad3 [31:0] $end
-$var integer 32 on msg_count_pad4 [31:0] $end
-$var integer 32 pn msg_count_pad5 [31:0] $end
-$var integer 32 qn msg_count_pad6 [31:0] $end
-$var integer 32 rn msg_count_pad7 [31:0] $end
-$var integer 32 sn msg_count_pad8 [31:0] $end
-$var integer 32 tn msg_count_pad9 [31:0] $end
-$var integer 32 un slow_0_delay [31:0] $end
-$var integer 32 vn slow_1_delay [31:0] $end
-$var integer 32 wn slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area2_io_pad[11] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 xn ANALOG_EN $end
-$var wire 1 yn ANALOG_POL $end
-$var wire 1 zn ANALOG_SEL $end
-$var wire 3 {n DM [2:0] $end
-$var wire 1 |n ENABLE_H $end
-$var wire 1 }n ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 ~n HLD_H_N $end
-$var wire 1 !o HLD_OVR $end
-$var wire 1 "o IB_MODE_SEL $end
-$var wire 1 #o INP_DIS $end
-$var wire 1 $o OE_N $end
-$var wire 1 %o OUT $end
-$var wire 1 &o PAD $end
-$var wire 1 'o PAD_A_ESD_0_H $end
-$var wire 1 (o PAD_A_ESD_1_H $end
-$var wire 1 )o PAD_A_NOESD_H $end
-$var wire 1 *o SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 +o VTRIP_SEL $end
-$var wire 1 ,o TIE_LO_ESD $end
-$var wire 1 -o TIE_HI_ESD $end
-$var wire 1 .o IN_H $end
-$var wire 1 /o IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$scope module gpiov2_base $end
-$var event 1 0o event_error_vswitch5 $end
-$var event 1 1o event_error_vswitch4 $end
-$var event 1 2o event_error_vswitch3 $end
-$var event 1 3o event_error_vswitch2 $end
-$var event 1 4o event_error_vswitch1 $end
-$var event 1 5o event_error_vddio_q2 $end
-$var event 1 6o event_error_vddio_q1 $end
-$var event 1 7o event_error_vdda_vddioq_vswitch2 $end
-$var event 1 8o event_error_vdda3 $end
-$var event 1 9o event_error_vdda2 $end
-$var event 1 :o event_error_vdda $end
-$var event 1 ;o event_error_supply_good $end
-$var event 1 <o event_error_enable_vddio $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 xn ANALOG_EN $end
-$var wire 1 yn ANALOG_POL $end
-$var wire 1 zn ANALOG_SEL $end
-$var wire 3 =o DM [2:0] $end
-$var wire 1 |n ENABLE_H $end
-$var wire 1 }n ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 ~n HLD_H_N $end
-$var wire 1 !o HLD_OVR $end
-$var wire 1 "o IB_MODE_SEL $end
-$var wire 1 #o INP_DIS $end
-$var wire 1 $o OE_N $end
-$var wire 1 %o OUT $end
-$var wire 1 &o PAD $end
-$var wire 1 'o PAD_A_ESD_0_H $end
-$var wire 1 (o PAD_A_ESD_1_H $end
-$var wire 1 )o PAD_A_NOESD_H $end
-$var wire 1 *o SLOW $end
-$var wire 1 + VCCD $end
-$var wire 1 + VCCHIB $end
-$var wire 1 * VDDA $end
-$var wire 1 * VDDIO $end
-$var wire 1 i? VDDIO_Q $end
-$var wire 1 ! VSSA $end
-$var wire 1 ! VSSD $end
-$var wire 1 ! VSSIO $end
-$var wire 1 j? VSSIO_Q $end
-$var wire 1 * VSWITCH $end
-$var wire 1 +o VTRIP_SEL $end
-$var wire 3 >o dm_buf [2:0] $end
-$var wire 1 ?o error_enable_vddio $end
-$var wire 1 @o error_supply_good $end
-$var wire 1 Ao error_vdda $end
-$var wire 1 Bo error_vdda2 $end
-$var wire 1 Co error_vdda3 $end
-$var wire 1 Do error_vdda_vddioq_vswitch2 $end
-$var wire 1 Eo error_vddio_q1 $end
-$var wire 1 Fo error_vddio_q2 $end
-$var wire 1 Go error_vswitch1 $end
-$var wire 1 Ho error_vswitch2 $end
-$var wire 1 Io error_vswitch3 $end
-$var wire 1 Jo error_vswitch4 $end
-$var wire 1 Ko error_vswitch5 $end
-$var wire 1 Lo functional_mode_amux $end
-$var wire 1 Mo hld_h_n_buf $end
-$var wire 1 No hld_ovr_buf $end
-$var wire 1 Oo ib_mode_sel_buf $end
-$var wire 1 Po inp_dis_buf $end
-$var wire 1 Qo invalid_controls_amux $end
-$var wire 1 Ro oe_n_buf $end
-$var wire 1 So out_buf $end
-$var wire 1 To pad_tristate $end
-$var wire 1 Uo pwr_good_active_mode $end
-$var wire 1 Vo pwr_good_active_mode_vdda $end
-$var wire 1 Wo pwr_good_amux $end
-$var wire 1 Xo pwr_good_analog_en_vdda $end
-$var wire 1 Yo pwr_good_analog_en_vddio_q $end
-$var wire 1 Zo pwr_good_analog_en_vswitch $end
-$var wire 1 [o pwr_good_hold_mode $end
-$var wire 1 \o pwr_good_hold_mode_vdda $end
-$var wire 1 ]o pwr_good_hold_ovr_mode $end
-$var wire 1 ^o pwr_good_inpbuff_hv $end
-$var wire 1 _o pwr_good_inpbuff_lv $end
-$var wire 1 `o pwr_good_output_driver $end
-$var wire 1 ao slow_buf $end
-$var wire 1 bo vtrip_sel_buf $end
-$var wire 1 co x_on_analog_en_vdda $end
-$var wire 1 do x_on_analog_en_vddio_q $end
-$var wire 1 eo x_on_analog_en_vswitch $end
-$var wire 1 fo x_on_in_hv $end
-$var wire 1 go x_on_in_lv $end
-$var wire 1 ho x_on_pad $end
-$var wire 1 io zero_on_analog_en_vdda $end
-$var wire 1 jo zero_on_analog_en_vddio_q $end
-$var wire 1 ko zero_on_analog_en_vswitch $end
-$var wire 1 lo pwr_good_amux_vccd $end
-$var wire 1 mo enable_pad_vssio_q $end
-$var wire 1 no enable_pad_vddio_q $end
-$var wire 1 oo enable_pad_amuxbus_b $end
-$var wire 1 po enable_pad_amuxbus_a $end
-$var wire 1 qo disable_inp_buff_lv $end
-$var wire 1 ro disable_inp_buff $end
-$var wire 3 so amux_select [2:0] $end
-$var wire 1 ,o TIE_LO_ESD $end
-$var wire 1 -o TIE_HI_ESD $end
-$var wire 1 .o IN_H $end
-$var wire 1 /o IN $end
-$var wire 1 h ENABLE_VDDA_H $end
-$var reg 1 to analog_en_final $end
-$var reg 1 uo analog_en_vdda $end
-$var reg 1 vo analog_en_vddio_q $end
-$var reg 1 wo analog_en_vswitch $end
-$var reg 1 xo dis_err_msgs $end
-$var reg 3 yo dm_final [2:0] $end
-$var reg 1 zo hld_ovr_final $end
-$var reg 1 {o ib_mode_sel_final $end
-$var reg 1 |o inp_dis_final $end
-$var reg 1 }o notifier_dm $end
-$var reg 1 ~o notifier_enable_h $end
-$var reg 1 !p notifier_hld_ovr $end
-$var reg 1 "p notifier_ib_mode_sel $end
-$var reg 1 #p notifier_inp_dis $end
-$var reg 1 $p notifier_oe_n $end
-$var reg 1 %p notifier_out $end
-$var reg 1 &p notifier_slow $end
-$var reg 1 'p notifier_vtrip_sel $end
-$var reg 1 (p oe_n_final $end
-$var reg 1 )p out_final $end
-$var reg 1 *p slow_final $end
-$var reg 1 +p vtrip_sel_final $end
-$var integer 32 ,p msg_count_pad [31:0] $end
-$var integer 32 -p msg_count_pad1 [31:0] $end
-$var integer 32 .p msg_count_pad10 [31:0] $end
-$var integer 32 /p msg_count_pad11 [31:0] $end
-$var integer 32 0p msg_count_pad12 [31:0] $end
-$var integer 32 1p msg_count_pad2 [31:0] $end
-$var integer 32 2p msg_count_pad3 [31:0] $end
-$var integer 32 3p msg_count_pad4 [31:0] $end
-$var integer 32 4p msg_count_pad5 [31:0] $end
-$var integer 32 5p msg_count_pad6 [31:0] $end
-$var integer 32 6p msg_count_pad7 [31:0] $end
-$var integer 32 7p msg_count_pad8 [31:0] $end
-$var integer 32 8p msg_count_pad9 [31:0] $end
-$var integer 32 9p slow_0_delay [31:0] $end
-$var integer 32 :p slow_1_delay [31:0] $end
-$var integer 32 ;p slow_delay [31:0] $end
-$scope begin LATCH_dm $end
-$upscope $end
-$scope begin LATCH_hld_ovr $end
-$upscope $end
-$scope begin LATCH_ib_mode_sel $end
-$upscope $end
-$scope begin LATCH_inp_dis $end
-$upscope $end
-$scope begin LATCH_oe_n $end
-$upscope $end
-$scope begin LATCH_out $end
-$upscope $end
-$scope begin LATCH_slow $end
-$upscope $end
-$scope begin LATCH_vtrip_sel $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module area2_io_pad[12] $end
-$var wire 1 X? AMUXBUS_A $end
-$var wire 1 Y? AMUXBUS_B $end
-$var wire 1 <p ANALOG_EN $end
-$var wire 1 =p ANALOG_POL $end
-$var wire 1 >p ANALOG_SEL $end
-$var wire 3 ?p DM [2:0] $end
-$var wire 1 @p ENABLE_H $end
-$var wire 1 Ap ENABLE_INP_H $end
-$var wire 1 + ENABLE_VDDIO $end
-$var wire 1 ! ENABLE_VSWITCH_H $end
-$var wire 1 Bp HLD_H_N $end