SoC-osu: Single-cycle RISC-V processor developed by OSU.

Clone this repo:
  1. 97cb8ba final gds & drc results by Jeff DiCorpo · 10 months ago main mpw-one-final
  2. a048dca final gds & drc results by Jeff DiCorpo · 10 months ago
  3. 52f6cf8 Add checks folder from DRC-fixed precheck by Alex Underwood · 10 months ago
  4. 8731083 Fix user_project_wrapper DRC and update caravel GDS by Alex Underwood · 10 months ago
  5. 915504b Add the checks folder from the prechecker script by Alex Underwood · 10 months ago

OSU RISC-V Caravel

This is an implementation of a single-cycle RISC-V processor inside of the Caravel test system for use in the SkyWater 130nm PDK.