[LocalRun04] Bugfix on carrychain
diff --git a/OpenFPGA_task/arch/vpr_arch.xml b/OpenFPGA_task/arch/vpr_arch.xml
index 07c6ba8..44db1ed 100644
--- a/OpenFPGA_task/arch/vpr_arch.xml
+++ b/OpenFPGA_task/arch/vpr_arch.xml
@@ -1,9 +1,9 @@
-<!-- 
+<!--
   Low-cost homogeneous FPGA Architecture.
 
   - Skywater 130 nm technology
-  - General purpose logic block: 
-    K = 4, N = 8, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared) 
+  - General purpose logic block:
+    K = 4, N = 8, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared)
     with optionally registered outputs
   - Routing architecture:
       - 10% L = 1, fc_in = 0.15, Fc_out = 0.10
@@ -14,13 +14,13 @@
   Authors: Xifan Tang
 -->
 <architecture>
-  <!-- 
-       ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+  <!--
+       ODIN II specific config begins
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to
        ".model [type_of_block]") that this architecture supports.
 
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
+       already special structures in blif (.names, .input, .output, and .latch)
        that describe them.
   -->
   <models>
@@ -204,19 +204,19 @@
     </fixed_layout>
   </layout>
   <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
 			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
 			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
 			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
+			     lined up with Stratix IV.
 			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
 			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
 			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
 	                     by 2.5x when looking up in Jeff's tables.
 			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
+			     proposed FPGA, and which is also 40 nm
 			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
 			     4x minimum drive strength buffer. -->
     <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
@@ -234,14 +234,14 @@
   <switchlist>
     <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
 	       book area formula. This means the mux transistors are about 5x minimum drive strength.
-	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
 	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
 	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
 	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
 	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
 	       2.5x when looking up in Jeff's tables.
 	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
 	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
@@ -252,7 +252,7 @@
     <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
   </switchlist>
   <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
 			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
 			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
     <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
@@ -286,8 +286,8 @@
            If you need to register the I/O, define clocks in the circuit models
            These clocks can be handled in back-end
        -->
-      <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
+      <!-- A mode denotes the physical implementation of an I/O
+           This mode will be not packable but is mainly used for fabric verilog generation
         -->
       <mode name="physical" disabled_in_pack="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
@@ -306,7 +306,7 @@
 
       <!-- IOs can operate as either inputs or outputs.
 	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     the delays to and from registers in the I/O (and generally I/Os are registered
 	     today and that is when you timing analyze them.
 	     -->
       <mode name="inpad">
@@ -333,8 +333,8 @@
     </pb_type>
     <!-- Define I/O pads ends -->
     <!-- Define general purpose logic block (CLB) begin -->
-    <!-- -Due to the absence of local routing, 
-         the 4 inputs of fracturable LUT4 are no longer equivalent, 
+    <!-- -Due to the absence of local routing,
+         the 4 inputs of fracturable LUT4 are no longer equivalent,
          because the 4th input can not be switched when the dual-LUT3 modes are used.
          So pin equivalence should be applied to the first 3 inputs only
 	  -->
@@ -364,8 +364,8 @@
       <output name="sc_out" num_pins="1"/>
       <output name="cout" num_pins="1"/>
       <clock name="clk" num_pins="1"/>
-      <!-- Describe fracturable logic element.  
-             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+      <!-- Describe fracturable logic element.
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
              The outputs of the fracturable logic element can be optionally registered
         -->
       <pb_type name="fle" num_pb="8">
@@ -434,13 +434,15 @@
               <T_setup value="66e-12" port="ff.DI" clock="clk"/>
               <T_setup value="66e-12" port="ff.reset" clock="clk"/>
               <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>         
+            </pb_type>
             <interconnect>
               <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="fabric.sc_in" output="ff[0].DI"/>
-              <direct name="direct3" input="ff[0].Q" output="ff[1].DI"/>
-              <direct name="direct4" input="ff[1].Q" output="fabric.sc_out"/>
-              <direct name="direct5" input="ff[1].Q" output="fabric.reg_out"/>
+              <direct name="direct2" input="fabric.cin" output="frac_logic.cin"/>
+              <direct name="direct3" input="fabric.sc_in" output="ff[0].DI"/>
+              <direct name="direct4" input="ff[0].Q" output="ff[1].DI"/>
+              <direct name="direct5" input="ff[1].Q" output="fabric.sc_out"/>
+              <direct name="direct6" input="ff[1].Q" output="fabric.reg_out"/>
+              <direct name="direct7" input="frac_logic.cout" output="fabric.cout"/>
               <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
               <complete name="complete2" input="fabric.reset" output="ff[1:0].reset"/>
               <mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
@@ -629,7 +631,7 @@
             <direct name="direct4" input="fle.clk" output="shift_reg.clk"/>
           </interconnect>
         </mode>
-        <!-- Define shift register end --> 
+        <!-- Define shift register end -->
       </pb_type>
       <interconnect>
         <!-- We use direct connections to reduce the area to the most
@@ -691,8 +693,8 @@
         </complete>
         <complete name="resets" input="clb.reset" output="fle[7:0].reset">
         </complete>
-        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
                then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
                naive specification).
           -->
diff --git a/checks/KlayoutMerge.log b/checks/KlayoutMerge.log
index 513a90d..7c2ebc2 100644
--- a/checks/KlayoutMerge.log
+++ b/checks/KlayoutMerge.log
@@ -1,2 +1 @@
 Placing module at (326.540000,1393.580000)
-removing cell user_proj_example
diff --git a/checks/caravel.magic.drc.mag b/checks/caravel.magic.drc.mag
index 14d8bc1..75e5924 100644
--- a/checks/caravel.magic.drc.mag
+++ b/checks/caravel.magic.drc.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1608507776
+timestamp 1609087257
 << checkpaint >>
 rect -3932 -3932 721532 1041532
 << metal1 >>
@@ -80930,7 +80930,7 @@
 transform 1 0 0 0 1 0
 box 0 0 717600 1037600
 use user_project_wrapper  mprj
-timestamp 1608507776
+timestamp 1609087257
 transform 1 0 65308 0 1 278716
 box -8576 -7506 592500 711442
 << properties >>
diff --git a/checks/compare_caravel.txt b/checks/compare_caravel.txt
index 2ccd2d5..debb591 100644
--- a/checks/compare_caravel.txt
+++ b/checks/compare_caravel.txt
@@ -3,7 +3,7 @@
  .travisCI/travisBuild.sh                           |     28 -
  OpenFPGA_task/arch/fabric_key.xml                  |    678 +
  OpenFPGA_task/arch/openfpga_arch.xml               |    330 +
- OpenFPGA_task/arch/vpr_arch.xml                    |    737 +
+ OpenFPGA_task/arch/vpr_arch.xml                    |    739 +
  OpenFPGA_task/config/task.conf                     |     39 +
  OpenFPGA_task/config/task_generation.conf          |     39 +
  OpenFPGA_task/config/task_simulation.conf          |     33 +
@@ -26,42 +26,42 @@
  OpenFPGA_task/user_project_wrapper_empty.def       |   1219 +
  OpenFPGA_task/user_project_wrapper_template.def    |   3768 +
  README.md                                          |    158 +-
- checks/KlayoutMerge.log                            |      2 +
+ checks/KlayoutMerge.log                            |      1 +
  checks/caravel.magic.drc                           |    104 +
- checks/caravel.magic.drc.mag                       |  80938 ++++++++++
+ checks/caravel.magic.drc.mag                       |  80938 ++++++++
  checks/caravel.magic.namelist                      |      1 +
  checks/caravel.magic.rdb                           |     63 +
  checks/caravel.magic.typelist                      |      1 +
  checks/compare_caravel.txt                         |      0
- checks/full_log.log                                |     57 +
+ checks/full_log.log                                |     56 +
  checks/magic_drc.log                               |   5095 +
- checks/magic_extract.log                           |  20268 +++
+ checks/magic_extract.log                           |  10873 ++
  checks/magic_merge_user_project_wrapper.log        |   5250 +
  checks/manifest_check.mag.log                      |      2 +
  checks/manifest_check.maglef.log                   |     13 +
  checks/manifest_check.rtl.log                      |     37 +
  checks/mprj.magic.namelist                         |      1 +
  checks/mprj.magic.typelist                         |      1 +
- checks/spdx_compliance_report.log                  |    125 +
- gds/caravel.gds.gz                                 |    Bin 52991493 -> 59641419 bytes
+ checks/spdx_compliance_report.log                  |    123 +
+ gds/caravel.gds.gz                                 |    Bin 52991493 -> 57163768 bytes
  gds/user_proj_example.gds.gz                       |    Bin 742584 -> 0 bytes
- gds/user_project_wrapper.gds.gz                    |    Bin 6394035 -> 3561254 bytes
+ gds/user_project_wrapper.gds.gz                    |    Bin 6394035 -> 3559736 bytes
  gds/user_project_wrapper_empty.gds.gz              |    Bin 73084 -> 0 bytes
  info.yaml                                          |      6 +-
  mag/.magicrc                                       |     16 -
  qflow/digital_pll_controller/tech                  |      1 -
  qflow/ring_osc2x13/tech                            |      1 -
- source_commit_hash.txt                             |     14 +
+ source_commit_hash.txt                             |     17 +
  verilog/OpenFPGA_Verilog/InstancesMap.txt          |      1 +
  verilog/OpenFPGA_Verilog/define_simulation.v       |     18 +
  verilog/OpenFPGA_Verilog/fabric_netlists.v         |     72 +
- verilog/OpenFPGA_Verilog/fpga_core.v               |  49530 ++++++
+ verilog/OpenFPGA_Verilog/fpga_core.v               |  49530 +++++
  verilog/OpenFPGA_Verilog/fpga_defines.v            |     10 +
  verilog/OpenFPGA_Verilog/fpga_top.v                |  41442 +++++
  verilog/OpenFPGA_Verilog/lb/grid_clb.v             |    272 +
  .../lb/logical_tile_clb_mode_clb_.v                |    758 +
  .../lb/logical_tile_clb_mode_default__fle.v        |    173 +
- ...e_clb_mode_default__fle_mode_physical__fabric.v |    242 +
+ ...e_clb_mode_default__fle_mode_physical__fabric.v |    250 +
  ...t__fle_mode_physical__fabric_mode_default__ff.v |     61 +
  ...ode_physical__fabric_mode_default__frac_logic.v |    151 +
  ...ault__frac_logic_mode_default__carry_follower.v |     52 +
@@ -100,5 +100,6 @@
  .../sub_module/sky130_fd_sc_hd_wrapper.v           |     20 +
  verilog/OpenFPGA_Verilog/sub_module/wires.v        |     34 +
  verilog/OpenFPGA_Verilog/top_include_netlists.v    |     31 +
- verilog/gl/caravel_sofa_chd_top.v                  | 147104 ++++++++++++++++++
- 103 files changed, 377967 insertions(+), 268 deletions(-)
+ verilog/gl/caravel_sofa_chd_top.v                  | 173465 ++++++++++++++++++
+ verilog/gl/user_project_wrapper.v                  |    160 +-
+ 104 files changed, 395052 insertions(+), 318 deletions(-)
diff --git a/checks/full_log.log b/checks/full_log.log
index 157ab24..8ac0c83 100644
--- a/checks/full_log.log
+++ b/checks/full_log.log
@@ -5,8 +5,8 @@
 {{LICENSE COMPLIANCE PASSED}} Apache-2.0 LICENSE file was found in project root
  No third party libraries found.
 Step 1 done without fatal errors.
-{{SPDX COMPLIANCE WARNING}} Found 123 non-compliant files with the SPDX Standard. Check full log for more information
-SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/usr/local/workspace/Caravel-SOFA-CHD/README.md', '/usr/local/workspace/Caravel-SOFA-CHD/source_commit_hash.txt', '/usr/local/workspace/Caravel-SOFA-CHD/doc/caravel_datasheet.ps', '/usr/local/workspace/Caravel-SOFA-CHD/mag/clamp_list.txt', '/usr/local/workspace/Caravel-SOFA-CHD/mag/.magicrc', '/usr/local/workspace/Caravel-SOFA-CHD/maglef/.magicrc', '/usr/local/workspace/Caravel-SOFA-CHD/openlane/chip_dimensions.txt', '/usr/local/workspace/Caravel-SOFA-CHD/openlane/mgmt_protect/pdn.tcl', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/DFFRAM.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/chip_io.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/digital_pll.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/gpio_control_block.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/simple_por.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/storage.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/user_id_programming.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mgmt_core.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mgmt_protect.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mgmt_protect_hv.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mprj2_logic_high.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mprj_logic_high.spice']
+{{SPDX COMPLIANCE WARNING}} Found 121 non-compliant files with the SPDX Standard. Check full log for more information
+SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/usr/local/workspace/Caravel-SOFA-CHD/README.md', '/usr/local/workspace/Caravel-SOFA-CHD/source_commit_hash.txt', '/usr/local/workspace/Caravel-SOFA-CHD/doc/caravel_datasheet.ps', '/usr/local/workspace/Caravel-SOFA-CHD/mag/clamp_list.txt', '/usr/local/workspace/Caravel-SOFA-CHD/openlane/chip_dimensions.txt', '/usr/local/workspace/Caravel-SOFA-CHD/openlane/mgmt_protect/pdn.tcl', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/DFFRAM.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/chip_io.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/digital_pll.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/gpio_control_block.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/simple_por.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/storage.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/user_id_programming.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mgmt_core.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mgmt_protect.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mgmt_protect_hv.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mprj2_logic_high.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mprj_logic_high.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/user_proj_example.spice']
  Executing Step 2 of 4: Checking YAML description.
  YAML file valid!
 Step 2 done without fatal errors.
@@ -23,8 +23,7 @@
 b'Removing manifest'
 b'Fetching manifest'
 b'Running sha1sum checks'
- Manifest Checks Failed. Please rebase your Repository to the latest Caravel master.
-.magicrc: FAILED
+ Nothing Happened
  Documentation Checks Passed.
  Makefile Checks Passed.
 instance caravel found
@@ -35,9 +34,9 @@
  Basic Hierarchy Checks Passed.
  Running Magic Extractions From GDS...
 user wrapper cell names differences: 
-['mprj']
+['fpga_top_uut']
 user wrapper cell type differences: 
-['user_proj_example']
+['fpga_top']
 toplevel cell names differences: 
 ['user_project_wrapper_0', 'mprj']
 toplevel cell type differences: 
diff --git a/checks/magic_drc.log b/checks/magic_drc.log
index f6d353d..14e02e0 100644
--- a/checks/magic_drc.log
+++ b/checks/magic_drc.log
@@ -31,24 +31,24 @@
 Reading "$$M2M3_PR".
 Reading "$$M1M2_PR".
 Reading "$$M4M5_PR_16000_16000_2_1".
-Reading "sky130_fd_sc_hd__fill_2".
-Reading "sky130_fd_sc_hd__fill_8".
 Reading "sky130_fd_sc_hd__fill_4".
+Reading "sky130_fd_sc_hd__fill_8".
 Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__fill_2".
 Reading "sky130_fd_sc_hd__buf_1".
 Error while reading cell "sky130_fd_sc_hd__buf_1" (byte position 8706): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__clkbuf_1".
 Error while reading cell "sky130_fd_sc_hd__clkbuf_1" (byte position 12678): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__buf_6".
-Error while reading cell "sky130_fd_sc_hd__buf_6" (byte position 16488): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__bufbuf_16".
-Error while reading cell "sky130_fd_sc_hd__bufbuf_16" (byte position 23530): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__buf_4".
-Error while reading cell "sky130_fd_sc_hd__buf_4" (byte position 41792): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__buf_8".
-Error while reading cell "sky130_fd_sc_hd__buf_8" (byte position 47200): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__buf_2".
-Error while reading cell "sky130_fd_sc_hd__buf_2" (byte position 56092): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__buf_2" (byte position 16488): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__buf_6".
+Error while reading cell "sky130_fd_sc_hd__buf_6" (byte position 20984): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__bufbuf_16".
+Error while reading cell "sky130_fd_sc_hd__bufbuf_16" (byte position 28026): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__buf_4".
+Error while reading cell "sky130_fd_sc_hd__buf_4" (byte position 46288): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__buf_8".
+Error while reading cell "sky130_fd_sc_hd__buf_8" (byte position 51696): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__dfrtp_1".
 Error while reading cell "sky130_fd_sc_hd__dfrtp_1" (byte position 60590): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_uuopenfpga_cc_hd_invmux3_1".
@@ -64,12 +64,12 @@
 Error while reading cell "sky130_fd_sc_hd__sdfrtp_1" (byte position 105652): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__mux2_1".
 Error while reading cell "sky130_fd_sc_hd__mux2_1" (byte position 124542): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__or2_0".
-Error while reading cell "sky130_fd_sc_hd__or2_0" (byte position 131430): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__inv_8".
-Error while reading cell "sky130_fd_sc_hd__inv_8" (byte position 135384): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__inv_2".
-Error while reading cell "sky130_fd_sc_hd__inv_2" (byte position 142944): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__inv_2" (byte position 131430): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__or2_0".
+Error while reading cell "sky130_fd_sc_hd__or2_0" (byte position 135238): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__inv_8".
+Error while reading cell "sky130_fd_sc_hd__inv_8" (byte position 139192): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__dlygate4sd1_1".
 Error while reading cell "sky130_fd_sc_hd__dlygate4sd1_1" (byte position 146760): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__dlygate4sd3_1".
@@ -179,7 +179,7 @@
     9700 uses
     9800 uses
 Reading "sky130_fd_sc_hd__mux2_2".
-Error while reading cell "sky130_fd_sc_hd__mux2_2" (byte position 923982): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__mux2_2" (byte position 910382): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sb_0__0_".
     100 uses
     200 uses
@@ -227,7 +227,7 @@
     4400 uses
     4500 uses
 Reading "sky130_fd_sc_hd__dlygate4sd2_1".
-Error while reading cell "sky130_fd_sc_hd__dlygate4sd2_1" (byte position 1285714): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__dlygate4sd2_1" (byte position 1272114): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_uuopenfpga_cc_hd_invmux2_1".
 Reading "sb_0__1_".
     100 uses
@@ -325,7 +325,7 @@
     9300 uses
     9400 uses
 Reading "sky130_fd_sc_hd__inv_6".
-Error while reading cell "sky130_fd_sc_hd__inv_6" (byte position 2078114): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__inv_6" (byte position 2064514): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sb_0__2_".
     100 uses
     200 uses
@@ -644,7 +644,7 @@
     15700 uses
     15800 uses
 Reading "sky130_fd_sc_hd__bufbuf_8".
-Error while reading cell "sky130_fd_sc_hd__bufbuf_8" (byte position 4743568): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__bufbuf_8" (byte position 4729968): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sb_1__2_".
     100 uses
     200 uses
@@ -990,13 +990,13 @@
     6300 uses
     6400 uses
 Reading "sky130_fd_sc_hd__inv_4".
-Error while reading cell "sky130_fd_sc_hd__inv_4" (byte position 7506942): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__inv_4" (byte position 7493342): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__ebufn_4".
-Error while reading cell "sky130_fd_sc_hd__ebufn_4" (byte position 7511994): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__ebufn_4" (byte position 7498394): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__nand2b_1".
-Error while reading cell "sky130_fd_sc_hd__nand2b_1" (byte position 7521504): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__nand2b_1" (byte position 7507904): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__or2b_4".
-Error while reading cell "sky130_fd_sc_hd__or2b_4" (byte position 7526096): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__or2b_4" (byte position 7512496): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "cbx_1__0_".
     100 uses
     200 uses
diff --git a/checks/magic_extract.log b/checks/magic_extract.log
index 116c085..d349222 100644
--- a/checks/magic_extract.log
+++ b/checks/magic_extract.log
@@ -323,8 +323,8 @@
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808360".
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808361".
 Reading "sky130_fd_io__nfet_con_diff_wo_abt_270v2".
-Error while reading cell "sky130_fd_io__nfet_con_diff_wo_abt_270v2" (byte position 1223032): Unknown layer/datatype in boundary, layer=81 type=6
-Error while reading cell "sky130_fd_io__nfet_con_diff_wo_abt_270v2" (byte position 1224824): Unknown layer/datatype in boundary, layer=81 type=8
+Error while reading cell "sky130_fd_io__nfet_con_diff_wo_abt_270v2" (byte position 1223190): Unknown layer/datatype in boundary, layer=81 type=6
+Error while reading cell "sky130_fd_io__nfet_con_diff_wo_abt_270v2" (byte position 1224982): Unknown layer/datatype in boundary, layer=81 type=8
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808656".
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808654".
 Reading "sky130_fd_io__pfet_con_diff_wo_abt_270v2".
@@ -461,10 +461,10 @@
 Reading "sky130_fd_io__com_pudrvr_weakv2".
 Error while reading cell "sky130_fd_io__com_pudrvr_weakv2" (byte position 2581436): Unknown layer/datatype in boundary, layer=81 type=6
 Reading "sky130_fd_io__gpio_pddrvr_weakv2".
-Error while reading cell "sky130_fd_io__gpio_pddrvr_weakv2" (byte position 2643044): Unknown layer/datatype in boundary, layer=81 type=6
+Error while reading cell "sky130_fd_io__gpio_pddrvr_weakv2" (byte position 2643108): Unknown layer/datatype in boundary, layer=81 type=6
 Reading "sky130_fd_io__gpio_pudrvr_strongv2".
 Reading "sky130_fd_io__gpio_pddrvr_strong_slowv2".
-Error while reading cell "sky130_fd_io__gpio_pddrvr_strong_slowv2" (byte position 2989798): Unknown layer/datatype in boundary, layer=81 type=6
+Error while reading cell "sky130_fd_io__gpio_pddrvr_strong_slowv2" (byte position 2989862): Unknown layer/datatype in boundary, layer=81 type=6
 Reading "sky130_fd_io__tk_em1s_cdns_5595914180852".
 Reading "sky130_fd_pr__res_generic_po__example_5595914180853".
 Error while reading cell "sky130_fd_pr__res_generic_po__example_5595914180853" (byte position 2991204): Unknown layer/datatype in boundary, layer=66 type=14
@@ -554,7 +554,7 @@
 Reading "sky130_fd_io__hvsbt_inv_x4".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808555".
 Reading "sky130_fd_io__signal_5_sym_hv_local_5term".
-Error while reading cell "sky130_fd_io__signal_5_sym_hv_local_5term" (byte position 5033274): Unknown layer/datatype in boundary, layer=81 type=19
+Error while reading cell "sky130_fd_io__signal_5_sym_hv_local_5term" (byte position 5033376): Unknown layer/datatype in boundary, layer=81 type=19
 Error while reading cell "sky130_fd_io__signal_5_sym_hv_local_5term" (byte position 5033664): Unknown layer/datatype in boundary, layer=66 type=9
 Reading "sky130_fd_pr__padplhp__example_559591418080".
 Error while reading cell "sky130_fd_pr__padplhp__example_559591418080" (byte position 5034608): Unknown layer/datatype in boundary, layer=81 type=20
@@ -627,7 +627,7 @@
 Reading "sky130_fd_pr__tpl1__example_55959141808685".
 Reading "sky130_fd_pr__tpl1__example_55959141808686".
 Reading "sky130_fd_io__amux_switch_1v2b".
-Error while reading cell "sky130_fd_io__amux_switch_1v2b" (byte position 5458186): Unknown layer/datatype in boundary, layer=81 type=6
+Error while reading cell "sky130_fd_io__amux_switch_1v2b" (byte position 5458918): Unknown layer/datatype in boundary, layer=81 type=6
 Reading "sky130_fd_io__gpiov2_amux_ctl_logic".
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808591".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808592".
@@ -635,7 +635,7 @@
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808594".
 Reading "sky130_fd_io__gpiov2_ibuf_se".
 Reading "sky130_fd_io__gpiov2_buf_localesd".
-Error while reading cell "sky130_fd_io__gpiov2_buf_localesd" (byte position 5598650): Unknown layer/datatype in boundary, layer=81 type=6
+Error while reading cell "sky130_fd_io__gpiov2_buf_localesd" (byte position 5598986): Unknown layer/datatype in boundary, layer=81 type=6
 Reading "sky130_fd_io__gpiov2_ictl_logic".
 CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
 Reading "sky130_fd_io__com_ctl_hldv2".
@@ -643,8 +643,8 @@
 Reading "sky130_fd_io__gpiov2_octl_dat".
 Reading "sky130_fd_io__gpio_odrvrv2".
 Reading "sky130_fd_io__res75only_small".
-Error while reading cell "sky130_fd_io__res75only_small" (byte position 5927464): Unknown layer/datatype in boundary, layer=66 type=14
-Error while reading cell "sky130_fd_io__res75only_small" (byte position 5927528): Unknown layer/datatype in boundary, layer=81 type=19
+Error while reading cell "sky130_fd_io__res75only_small" (byte position 5927592): Unknown layer/datatype in boundary, layer=66 type=14
+Error while reading cell "sky130_fd_io__res75only_small" (byte position 5927656): Unknown layer/datatype in boundary, layer=81 type=19
 Reading "sky130_fd_io__com_bus_slice_m4".
 Reading "sky130_fd_io__top_gpio_pad".
 Reading "sky130_fd_io__pad_esd".
@@ -907,44 +907,44 @@
 Reading "pnand2_1".
 Reading "contact_32".
 Reading "contact_33".
-Reading "sky130_fd_sc_hd__bufbuf_8".
-Error while reading cell "sky130_fd_sc_hd__bufbuf_8" (byte position 11986942): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__or2b_4".
-Error while reading cell "sky130_fd_sc_hd__or2b_4" (byte position 12007372): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__inv_6".
-Error while reading cell "sky130_fd_sc_hd__inv_6" (byte position 12025322): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__or2b_4" (byte position 11958072): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__nand2b_1".
-Error while reading cell "sky130_fd_sc_hd__nand2b_1" (byte position 12039016): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__nand2b_1" (byte position 11964222): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__bufbuf_8".
+Error while reading cell "sky130_fd_sc_hd__bufbuf_8" (byte position 11970412): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__inv_6".
+Error while reading cell "sky130_fd_sc_hd__inv_6" (byte position 11979514): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_uuopenfpga_cc_hd_invmux2_1".
 Reading "sky130_fd_sc_hd__dlygate4sd2_1".
-Error while reading cell "sky130_fd_sc_hd__dlygate4sd2_1" (byte position 12083624): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__dlygate4sd2_1" (byte position 11995052): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__mux2_2".
-Error while reading cell "sky130_fd_sc_hd__mux2_2" (byte position 12105296): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__mux2_2" (byte position 12001234): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__dlygate4sd3_1".
-Error while reading cell "sky130_fd_sc_hd__dlygate4sd3_1" (byte position 12123164): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__dlygate4sd3_1" (byte position 12008000): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__dlygate4sd1_1".
-Error while reading cell "sky130_fd_sc_hd__dlygate4sd1_1" (byte position 12139478): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__dlygate4sd1_1" (byte position 12014176): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__or2_0".
-Error while reading cell "sky130_fd_sc_hd__or2_0" (byte position 12151260): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__or2_0" (byte position 12019034): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__mux2_1".
-Error while reading cell "sky130_fd_sc_hd__mux2_1" (byte position 12171846): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__mux2_1" (byte position 12024026): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__sdfrtp_1".
-Error while reading cell "sky130_fd_sc_hd__sdfrtp_1" (byte position 12228434): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__sdfrtp_1" (byte position 12036692): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__nand2_1".
-Error while reading cell "sky130_fd_sc_hd__nand2_1" (byte position 12240212): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__nand2_1" (byte position 12048554): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__nor2_1".
-Error while reading cell "sky130_fd_sc_hd__nor2_1" (byte position 12251132): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__nor2_1" (byte position 12052550): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_uuopenfpga_cc_hd_invmux3_1".
 Reading "sky130_fd_sc_hd__dfrtp_1".
-Error while reading cell "sky130_fd_sc_hd__dfrtp_1" (byte position 12341046): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__dfrtp_1" (byte position 12076012): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__bufbuf_16".
-Error while reading cell "sky130_fd_sc_hd__bufbuf_16" (byte position 12395756): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__bufbuf_16" (byte position 12089814): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__buf_6".
-Error while reading cell "sky130_fd_sc_hd__buf_6" (byte position 12416790): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__buf_6" (byte position 12105316): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__buf_1".
-Error while reading cell "sky130_fd_sc_hd__buf_1" (byte position 12428614): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__fill_4".
+Error while reading cell "sky130_fd_sc_hd__buf_1" (byte position 12111726): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__fill_8".
+Reading "sky130_fd_sc_hd__fill_4".
 Reading "$$M4M5_PR_16000_16000_2_1".
 Reading "$$M1M2_PR".
 Reading "$$M2M3_PR".
@@ -956,15 +956,15 @@
 Reading "sky130_fd_io__hvc_clampv2".
     100 uses
 Reading "sky130_fd_pr__res_bent_po__example_55959141808692".
-Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808692" (byte position 17412968): Unknown layer/datatype in boundary, layer=66 type=14
+Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808692" (byte position 17087516): Unknown layer/datatype in boundary, layer=66 type=14
 Reading "sky130_fd_pr__res_bent_po__example_55959141808689".
-Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808689" (byte position 17416202): Unknown layer/datatype in boundary, layer=66 type=14
+Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808689" (byte position 17090750): Unknown layer/datatype in boundary, layer=66 type=14
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808701".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808703".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808704".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808695".
 Reading "sky130_fd_pr__res_bent_po__example_55959141808688".
-Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808688" (byte position 17472632): Unknown layer/datatype in boundary, layer=66 type=14
+Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808688" (byte position 17147180): Unknown layer/datatype in boundary, layer=66 type=14
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808699".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808696".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808698".
@@ -974,18 +974,18 @@
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808705".
 Reading "sky130_fd_pr__dfl1__example_55959141808682".
 Reading "sky130_fd_pr__res_bent_po__example_55959141808690".
-Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808690" (byte position 17525444): Unknown layer/datatype in boundary, layer=66 type=14
+Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808690" (byte position 17199992): Unknown layer/datatype in boundary, layer=66 type=14
 Reading "sky130_fd_pr__res_bent_po__example_55959141808691".
-Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808691" (byte position 17529190): Unknown layer/datatype in boundary, layer=66 type=14
+Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808691" (byte position 17203738): Unknown layer/datatype in boundary, layer=66 type=14
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808687".
 Reading "sky130_fd_io__gnd2gnd_120x2_lv_isosub".
-Error while reading cell "sky130_fd_io__gnd2gnd_120x2_lv_isosub" (byte position 17536512): Unknown layer/datatype in boundary, layer=81 type=19
+Error while reading cell "sky130_fd_io__gnd2gnd_120x2_lv_isosub" (byte position 17211846): Unknown layer/datatype in boundary, layer=81 type=19
 Reading "sky130_fd_io__top_gpiov2".
 Reading "sky130_fd_io__overlay_gpiov2".
 Reading "sky130_fd_pr__res_bent_po__example_55959141808768".
-Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808768" (byte position 19485704): Unknown layer/datatype in boundary, layer=66 type=14
+Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808768" (byte position 19160252): Unknown layer/datatype in boundary, layer=66 type=14
 Reading "sky130_fd_pr__res_bent_nd__example_55959141808769".
-Error while reading cell "sky130_fd_pr__res_bent_nd__example_55959141808769" (byte position 19488482): Unknown layer/datatype in boundary, layer=65 type=14
+Error while reading cell "sky130_fd_pr__res_bent_nd__example_55959141808769" (byte position 19163030): Unknown layer/datatype in boundary, layer=65 type=14
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808770".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808771".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808772".
@@ -1004,13 +1004,13 @@
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808786".
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808787".
 Reading "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2".
-Error while reading cell "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2" (byte position 20312960): Unknown layer/datatype in boundary, layer=81 type=6
-Error while reading cell "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2" (byte position 20314752): Unknown layer/datatype in boundary, layer=81 type=8
+Error while reading cell "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2" (byte position 19987572): Unknown layer/datatype in boundary, layer=81 type=6
+Error while reading cell "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2" (byte position 19989364): Unknown layer/datatype in boundary, layer=81 type=8
 Reading "sky130_fd_io__xres_p_em1c_cdns_55959141808753".
 Reading "sky130_fd_pr__res_generic_nd__example_55959141808754".
-Error while reading cell "sky130_fd_pr__res_generic_nd__example_55959141808754" (byte position 20317884): Unknown layer/datatype in boundary, layer=65 type=14
+Error while reading cell "sky130_fd_pr__res_generic_nd__example_55959141808754" (byte position 19992432): Unknown layer/datatype in boundary, layer=65 type=14
 Reading "sky130_fd_pr__res_generic_nd__example_55959141808755".
-Error while reading cell "sky130_fd_pr__res_generic_nd__example_55959141808755" (byte position 20318506): Unknown layer/datatype in boundary, layer=65 type=14
+Error while reading cell "sky130_fd_pr__res_generic_nd__example_55959141808755" (byte position 19993054): Unknown layer/datatype in boundary, layer=65 type=14
 Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756".
 Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757".
 Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758".
@@ -1044,8 +1044,8 @@
 Reading "sky130_fd_pr__via_l1m1__example_55959141808751".
 Reading "sky130_fd_pr__via_l1m1__example_55959141808752".
 Reading "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2".
-Error while reading cell "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2" (byte position 21203842): Unknown layer/datatype in boundary, layer=81 type=6
-Error while reading cell "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2" (byte position 21205634): Unknown layer/datatype in boundary, layer=81 type=8
+Error while reading cell "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2" (byte position 20878390): Unknown layer/datatype in boundary, layer=81 type=6
+Error while reading cell "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2" (byte position 20880182): Unknown layer/datatype in boundary, layer=81 type=8
 Reading "sky130_fd_pr__via_m1m2__example_55959141808551".
 Reading "sky130_fd_pr__via_m1m2__example_55959141808552".
 Reading "sky130_fd_pr__via_m1m2__example_55959141808724".
@@ -1057,7 +1057,7 @@
 Reading "sky130_fd_pr__via_m1m2__example_55959141808727".
 Reading "sky130_fd_pr__via_m1m2__example_55959141808728".
 Reading "sky130_fd_pr__res_bent_po__example_55959141808715".
-Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808715" (byte position 21219160): Unknown layer/datatype in boundary, layer=66 type=14
+Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808715" (byte position 20893708): Unknown layer/datatype in boundary, layer=66 type=14
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808716".
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808718".
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808720".
@@ -1065,21 +1065,21 @@
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808722".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808723".
 Reading "sky130_fd_sc_hd__inv_8".
-Error while reading cell "sky130_fd_sc_hd__inv_8" (byte position 21255516): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__inv_8" (byte position 20904484): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__ebufn_4".
-Error while reading cell "sky130_fd_sc_hd__ebufn_4" (byte position 21293362): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__ebufn_4" (byte position 20920978): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__inv_1".
-Error while reading cell "sky130_fd_sc_hd__inv_1" (byte position 21307446): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__inv_1" (byte position 20937010): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__clkbuf_8".
-Error while reading cell "sky130_fd_sc_hd__clkbuf_8" (byte position 21338574): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__clkbuf_8" (byte position 20946350): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__inv_4".
-Error while reading cell "sky130_fd_sc_hd__inv_4" (byte position 21358642): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__inv_4" (byte position 20960118): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__clkinv_1".
-Error while reading cell "sky130_fd_sc_hd__clkinv_1" (byte position 21373850): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__clkinv_1" (byte position 20969546): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__buf_4".
-Error while reading cell "sky130_fd_sc_hd__buf_4" (byte position 21395350): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__buf_4" (byte position 20978258): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__buf_8".
-Error while reading cell "sky130_fd_sc_hd__buf_8" (byte position 21430786): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__buf_8" (byte position 20990506): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "bank".
     100 uses
     200 uses
@@ -1095,11 +1095,11 @@
     300 uses
     400 uses
 Reading "control_logic_r".
-Error while reading cell "control_logic_r" (byte position 22629414): Warning:  Cell control_logic_r boundary was redefined.
-Error while reading cell "control_logic_r" (byte position 22629414): Warning:  Cell control_logic_r boundary was redefined.
-Error while reading cell "control_logic_r" (byte position 22629414): Warning:  Cell control_logic_r boundary was redefined.
-Error while reading cell "control_logic_r" (byte position 22629414): Warning:  Cell control_logic_r boundary was redefined.
-Error while reading cell "control_logic_r" (byte position 22629414): Warning:  Cell control_logic_r boundary was redefined.
+Error while reading cell "control_logic_r" (byte position 22201486): Warning:  Cell control_logic_r boundary was redefined.
+Error while reading cell "control_logic_r" (byte position 22201486): Warning:  Cell control_logic_r boundary was redefined.
+Error while reading cell "control_logic_r" (byte position 22201486): Warning:  Cell control_logic_r boundary was redefined.
+Error while reading cell "control_logic_r" (byte position 22201486): Warning:  Cell control_logic_r boundary was redefined.
+Error while reading cell "control_logic_r" (byte position 22201486): Warning:  Cell control_logic_r boundary was redefined.
 Reading "cr_3".
 Reading "control_logic_rw".
     100 uses
@@ -1108,13 +1108,13 @@
 Reading "row_addr_dff".
 Reading "contact_34".
 Reading "sky130_fd_sc_hd__clkbuf_1".
-Error while reading cell "sky130_fd_sc_hd__clkbuf_1" (byte position 22675682): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__clkbuf_1" (byte position 22236042): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__inv_2".
-Error while reading cell "sky130_fd_sc_hd__inv_2" (byte position 22690782): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__inv_2" (byte position 22243122): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__buf_2".
-Error while reading cell "sky130_fd_sc_hd__buf_2" (byte position 22708634): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__buf_2" (byte position 22251306): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__conb_1".
-Error while reading cell "sky130_fd_sc_hd__conb_1" (byte position 22721448): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__conb_1" (byte position 22260036): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__fill_1".
 Reading "sky130_fd_sc_hd__fill_2".
 Reading "$$M1M2_PR_3200_3200_1_9".
@@ -1125,7 +1125,176 @@
 Reading "$$M4M5_PR_16000_16000_1_7".
 Reading "$$M4M5_PR_16000_16000_2_7".
 Reading "$$M2M3_PR_C".
-Reading "sb_2__2_".
+Reading "cby_2__1_".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+    4700 uses
+    4800 uses
+    4900 uses
+    5000 uses
+    5100 uses
+    5200 uses
+    5300 uses
+    5400 uses
+    5500 uses
+    5600 uses
+    5700 uses
+    5800 uses
+    5900 uses
+    6000 uses
+    6100 uses
+    6200 uses
+    6300 uses
+    6400 uses
+    6500 uses
+    6600 uses
+    6700 uses
+    6800 uses
+    6900 uses
+    7000 uses
+    7100 uses
+    7200 uses
+    7300 uses
+    7400 uses
+Reading "cby_1__1_".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+    4700 uses
+    4800 uses
+    4900 uses
+    5000 uses
+    5100 uses
+    5200 uses
+    5300 uses
+    5400 uses
+    5500 uses
+    5600 uses
+    5700 uses
+    5800 uses
+    5900 uses
+    6000 uses
+    6100 uses
+    6200 uses
+    6300 uses
+    6400 uses
+    6500 uses
+    6600 uses
+    6700 uses
+    6800 uses
+    6900 uses
+    7000 uses
+Reading "cby_0__1_".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+Reading "cbx_1__2_".
     100 uses
     200 uses
     300 uses
@@ -1201,124 +1370,201 @@
     7300 uses
     7400 uses
     7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
+Reading "cbx_1__1_".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+    4700 uses
+    4800 uses
+    4900 uses
+    5000 uses
+    5100 uses
+    5200 uses
+    5300 uses
+    5400 uses
+    5500 uses
+    5600 uses
+    5700 uses
+    5800 uses
+    5900 uses
+    6000 uses
+    6100 uses
+    6200 uses
+    6300 uses
+    6400 uses
+    6500 uses
+    6600 uses
+    6700 uses
+    6800 uses
+    6900 uses
+    7000 uses
+    7100 uses
+    7200 uses
+Reading "cbx_1__0_".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+    4700 uses
+    4800 uses
+    4900 uses
+    5000 uses
+    5100 uses
+    5200 uses
+    5300 uses
+    5400 uses
+    5500 uses
+    5600 uses
+Reading "sb_2__2_".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+    4700 uses
+    4800 uses
+    4900 uses
+    5000 uses
+    5100 uses
+    5200 uses
+    5300 uses
+    5400 uses
+    5500 uses
+    5600 uses
+    5700 uses
+    5800 uses
+    5900 uses
+    6000 uses
+    6100 uses
+    6200 uses
+    6300 uses
+    6400 uses
 Reading "sb_2__1_".
     100 uses
     200 uses
@@ -1421,210 +1667,6 @@
     9900 uses
     10000 uses
     10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-    21200 uses
-    21300 uses
-    21400 uses
-    21500 uses
-    21600 uses
-    21700 uses
-    21800 uses
-    21900 uses
-    22000 uses
-    22100 uses
-    22200 uses
-    22300 uses
-    22400 uses
-    22500 uses
-    22600 uses
-    22700 uses
-    22800 uses
-    22900 uses
-    23000 uses
-    23100 uses
-    23200 uses
-    23300 uses
-    23400 uses
-    23500 uses
-    23600 uses
-    23700 uses
-    23800 uses
-    23900 uses
-    24000 uses
-    24100 uses
-    24200 uses
-    24300 uses
-    24400 uses
-    24500 uses
-    24600 uses
-    24700 uses
-    24800 uses
-    24900 uses
-    25000 uses
-    25100 uses
-    25200 uses
-    25300 uses
-    25400 uses
-    25500 uses
-    25600 uses
-    25700 uses
-    25800 uses
-    25900 uses
-    26000 uses
-    26100 uses
-    26200 uses
-    26300 uses
-    26400 uses
-    26500 uses
-    26600 uses
-    26700 uses
-    26800 uses
-    26900 uses
-    27000 uses
-    27100 uses
-    27200 uses
-    27300 uses
-    27400 uses
-    27500 uses
-    27600 uses
-    27700 uses
-    27800 uses
-    27900 uses
-    28000 uses
-    28100 uses
-    28200 uses
-    28300 uses
-    28400 uses
-    28500 uses
-    28600 uses
-    28700 uses
-    28800 uses
-    28900 uses
-    29000 uses
-    29100 uses
-    29200 uses
-    29300 uses
-    29400 uses
-    29500 uses
-    29600 uses
-    29700 uses
-    29800 uses
-    29900 uses
-    30000 uses
-    30100 uses
-    30200 uses
-    30300 uses
-    30400 uses
-    30500 uses
 Reading "sb_2__0_".
     100 uses
     200 uses
@@ -1691,136 +1733,6 @@
     6300 uses
     6400 uses
     6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-    6900 uses
-    7000 uses
-    7100 uses
-    7200 uses
-    7300 uses
-    7400 uses
-    7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
 Reading "sb_1__2_".
     100 uses
     200 uses
@@ -1932,1958 +1844,6 @@
     10800 uses
     10900 uses
     11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-    21200 uses
-    21300 uses
-    21400 uses
-    21500 uses
-    21600 uses
-    21700 uses
-    21800 uses
-    21900 uses
-    22000 uses
-    22100 uses
-    22200 uses
-    22300 uses
-    22400 uses
-    22500 uses
-    22600 uses
-    22700 uses
-    22800 uses
-    22900 uses
-    23000 uses
-    23100 uses
-    23200 uses
-    23300 uses
-    23400 uses
-    23500 uses
-    23600 uses
-    23700 uses
-    23800 uses
-    23900 uses
-    24000 uses
-    24100 uses
-    24200 uses
-    24300 uses
-    24400 uses
-    24500 uses
-    24600 uses
-    24700 uses
-    24800 uses
-    24900 uses
-    25000 uses
-    25100 uses
-    25200 uses
-    25300 uses
-    25400 uses
-    25500 uses
-    25600 uses
-    25700 uses
-    25800 uses
-    25900 uses
-    26000 uses
-    26100 uses
-    26200 uses
-    26300 uses
-    26400 uses
-    26500 uses
-    26600 uses
-    26700 uses
-    26800 uses
-    26900 uses
-    27000 uses
-    27100 uses
-    27200 uses
-    27300 uses
-    27400 uses
-    27500 uses
-    27600 uses
-    27700 uses
-    27800 uses
-    27900 uses
-    28000 uses
-    28100 uses
-    28200 uses
-    28300 uses
-    28400 uses
-    28500 uses
-    28600 uses
-    28700 uses
-    28800 uses
-    28900 uses
-    29000 uses
-    29100 uses
-    29200 uses
-    29300 uses
-    29400 uses
-    29500 uses
-    29600 uses
-    29700 uses
-    29800 uses
-    29900 uses
-    30000 uses
-    30100 uses
-    30200 uses
-    30300 uses
-    30400 uses
-    30500 uses
-    30600 uses
-    30700 uses
-    30800 uses
-    30900 uses
-    31000 uses
-    31100 uses
-    31200 uses
-    31300 uses
-    31400 uses
-    31500 uses
-    31600 uses
-    31700 uses
-    31800 uses
-    31900 uses
-    32000 uses
-    32100 uses
-    32200 uses
-    32300 uses
-    32400 uses
-    32500 uses
-    32600 uses
-    32700 uses
-    32800 uses
-    32900 uses
-    33000 uses
-    33100 uses
-Reading "sb_1__0_".
-    100 uses
-    200 uses
-    300 uses
-    400 uses
-    500 uses
-    600 uses
-    700 uses
-    800 uses
-    900 uses
-    1000 uses
-    1100 uses
-    1200 uses
-    1300 uses
-    1400 uses
-    1500 uses
-    1600 uses
-    1700 uses
-    1800 uses
-    1900 uses
-    2000 uses
-    2100 uses
-    2200 uses
-    2300 uses
-    2400 uses
-    2500 uses
-    2600 uses
-    2700 uses
-    2800 uses
-    2900 uses
-    3000 uses
-    3100 uses
-    3200 uses
-    3300 uses
-    3400 uses
-    3500 uses
-    3600 uses
-    3700 uses
-    3800 uses
-    3900 uses
-    4000 uses
-    4100 uses
-    4200 uses
-    4300 uses
-    4400 uses
-    4500 uses
-    4600 uses
-    4700 uses
-    4800 uses
-    4900 uses
-    5000 uses
-    5100 uses
-    5200 uses
-    5300 uses
-    5400 uses
-    5500 uses
-    5600 uses
-    5700 uses
-    5800 uses
-    5900 uses
-    6000 uses
-    6100 uses
-    6200 uses
-    6300 uses
-    6400 uses
-    6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-    6900 uses
-    7000 uses
-    7100 uses
-    7200 uses
-    7300 uses
-    7400 uses
-    7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-    21200 uses
-    21300 uses
-    21400 uses
-    21500 uses
-    21600 uses
-    21700 uses
-    21800 uses
-    21900 uses
-    22000 uses
-    22100 uses
-    22200 uses
-    22300 uses
-    22400 uses
-    22500 uses
-    22600 uses
-    22700 uses
-    22800 uses
-    22900 uses
-    23000 uses
-    23100 uses
-    23200 uses
-    23300 uses
-    23400 uses
-    23500 uses
-    23600 uses
-    23700 uses
-    23800 uses
-    23900 uses
-    24000 uses
-    24100 uses
-    24200 uses
-    24300 uses
-    24400 uses
-    24500 uses
-    24600 uses
-    24700 uses
-    24800 uses
-    24900 uses
-    25000 uses
-    25100 uses
-    25200 uses
-    25300 uses
-    25400 uses
-    25500 uses
-    25600 uses
-    25700 uses
-    25800 uses
-    25900 uses
-    26000 uses
-    26100 uses
-    26200 uses
-    26300 uses
-    26400 uses
-    26500 uses
-    26600 uses
-    26700 uses
-    26800 uses
-    26900 uses
-    27000 uses
-    27100 uses
-    27200 uses
-    27300 uses
-    27400 uses
-    27500 uses
-    27600 uses
-    27700 uses
-    27800 uses
-    27900 uses
-    28000 uses
-    28100 uses
-    28200 uses
-    28300 uses
-    28400 uses
-    28500 uses
-    28600 uses
-    28700 uses
-    28800 uses
-    28900 uses
-    29000 uses
-    29100 uses
-    29200 uses
-    29300 uses
-    29400 uses
-    29500 uses
-    29600 uses
-    29700 uses
-    29800 uses
-    29900 uses
-    30000 uses
-    30100 uses
-    30200 uses
-    30300 uses
-    30400 uses
-    30500 uses
-    30600 uses
-    30700 uses
-    30800 uses
-    30900 uses
-    31000 uses
-    31100 uses
-    31200 uses
-    31300 uses
-    31400 uses
-    31500 uses
-    31600 uses
-    31700 uses
-    31800 uses
-    31900 uses
-    32000 uses
-    32100 uses
-    32200 uses
-    32300 uses
-    32400 uses
-    32500 uses
-    32600 uses
-    32700 uses
-    32800 uses
-    32900 uses
-    33000 uses
-Reading "sb_0__2_".
-    100 uses
-    200 uses
-    300 uses
-    400 uses
-    500 uses
-    600 uses
-    700 uses
-    800 uses
-    900 uses
-    1000 uses
-    1100 uses
-    1200 uses
-    1300 uses
-    1400 uses
-    1500 uses
-    1600 uses
-    1700 uses
-    1800 uses
-    1900 uses
-    2000 uses
-    2100 uses
-    2200 uses
-    2300 uses
-    2400 uses
-    2500 uses
-    2600 uses
-    2700 uses
-    2800 uses
-    2900 uses
-    3000 uses
-    3100 uses
-    3200 uses
-    3300 uses
-    3400 uses
-    3500 uses
-    3600 uses
-    3700 uses
-    3800 uses
-    3900 uses
-    4000 uses
-    4100 uses
-    4200 uses
-    4300 uses
-    4400 uses
-    4500 uses
-    4600 uses
-    4700 uses
-    4800 uses
-    4900 uses
-    5000 uses
-    5100 uses
-    5200 uses
-    5300 uses
-    5400 uses
-    5500 uses
-    5600 uses
-    5700 uses
-    5800 uses
-    5900 uses
-    6000 uses
-    6100 uses
-    6200 uses
-    6300 uses
-    6400 uses
-    6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-    6900 uses
-    7000 uses
-    7100 uses
-    7200 uses
-    7300 uses
-    7400 uses
-    7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-Reading "sb_0__0_".
-    100 uses
-    200 uses
-    300 uses
-    400 uses
-    500 uses
-    600 uses
-    700 uses
-    800 uses
-    900 uses
-    1000 uses
-    1100 uses
-    1200 uses
-    1300 uses
-    1400 uses
-    1500 uses
-    1600 uses
-    1700 uses
-    1800 uses
-    1900 uses
-    2000 uses
-    2100 uses
-    2200 uses
-    2300 uses
-    2400 uses
-    2500 uses
-    2600 uses
-    2700 uses
-    2800 uses
-    2900 uses
-    3000 uses
-    3100 uses
-    3200 uses
-    3300 uses
-    3400 uses
-    3500 uses
-    3600 uses
-    3700 uses
-    3800 uses
-    3900 uses
-    4000 uses
-    4100 uses
-    4200 uses
-    4300 uses
-    4400 uses
-    4500 uses
-    4600 uses
-    4700 uses
-    4800 uses
-    4900 uses
-    5000 uses
-    5100 uses
-    5200 uses
-    5300 uses
-    5400 uses
-    5500 uses
-    5600 uses
-    5700 uses
-    5800 uses
-    5900 uses
-    6000 uses
-    6100 uses
-    6200 uses
-    6300 uses
-    6400 uses
-    6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-    6900 uses
-    7000 uses
-    7100 uses
-    7200 uses
-    7300 uses
-    7400 uses
-    7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-Reading "cby_2__1_".
-    100 uses
-    200 uses
-    300 uses
-    400 uses
-    500 uses
-    600 uses
-    700 uses
-    800 uses
-    900 uses
-    1000 uses
-    1100 uses
-    1200 uses
-    1300 uses
-    1400 uses
-    1500 uses
-    1600 uses
-    1700 uses
-    1800 uses
-    1900 uses
-    2000 uses
-    2100 uses
-    2200 uses
-    2300 uses
-    2400 uses
-    2500 uses
-    2600 uses
-    2700 uses
-    2800 uses
-    2900 uses
-    3000 uses
-    3100 uses
-    3200 uses
-    3300 uses
-    3400 uses
-    3500 uses
-    3600 uses
-    3700 uses
-    3800 uses
-    3900 uses
-    4000 uses
-    4100 uses
-    4200 uses
-    4300 uses
-    4400 uses
-    4500 uses
-    4600 uses
-    4700 uses
-    4800 uses
-    4900 uses
-    5000 uses
-    5100 uses
-    5200 uses
-    5300 uses
-    5400 uses
-    5500 uses
-    5600 uses
-    5700 uses
-    5800 uses
-    5900 uses
-    6000 uses
-    6100 uses
-    6200 uses
-    6300 uses
-    6400 uses
-    6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-    6900 uses
-    7000 uses
-    7100 uses
-    7200 uses
-    7300 uses
-    7400 uses
-    7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-    21200 uses
-    21300 uses
-    21400 uses
-    21500 uses
-    21600 uses
-    21700 uses
-    21800 uses
-    21900 uses
-    22000 uses
-    22100 uses
-    22200 uses
-    22300 uses
-    22400 uses
-Reading "cby_1__1_".
-    100 uses
-    200 uses
-    300 uses
-    400 uses
-    500 uses
-    600 uses
-    700 uses
-    800 uses
-    900 uses
-    1000 uses
-    1100 uses
-    1200 uses
-    1300 uses
-    1400 uses
-    1500 uses
-    1600 uses
-    1700 uses
-    1800 uses
-    1900 uses
-    2000 uses
-    2100 uses
-    2200 uses
-    2300 uses
-    2400 uses
-    2500 uses
-    2600 uses
-    2700 uses
-    2800 uses
-    2900 uses
-    3000 uses
-    3100 uses
-    3200 uses
-    3300 uses
-    3400 uses
-    3500 uses
-    3600 uses
-    3700 uses
-    3800 uses
-    3900 uses
-    4000 uses
-    4100 uses
-    4200 uses
-    4300 uses
-    4400 uses
-    4500 uses
-    4600 uses
-    4700 uses
-    4800 uses
-    4900 uses
-    5000 uses
-    5100 uses
-    5200 uses
-    5300 uses
-    5400 uses
-    5500 uses
-    5600 uses
-    5700 uses
-    5800 uses
-    5900 uses
-    6000 uses
-    6100 uses
-    6200 uses
-    6300 uses
-    6400 uses
-    6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-    6900 uses
-    7000 uses
-    7100 uses
-    7200 uses
-    7300 uses
-    7400 uses
-    7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-Reading "cbx_1__0_".
-    100 uses
-    200 uses
-    300 uses
-    400 uses
-    500 uses
-    600 uses
-    700 uses
-    800 uses
-    900 uses
-    1000 uses
-    1100 uses
-    1200 uses
-    1300 uses
-    1400 uses
-    1500 uses
-    1600 uses
-    1700 uses
-    1800 uses
-    1900 uses
-    2000 uses
-    2100 uses
-    2200 uses
-    2300 uses
-    2400 uses
-    2500 uses
-    2600 uses
-    2700 uses
-    2800 uses
-    2900 uses
-    3000 uses
-    3100 uses
-    3200 uses
-    3300 uses
-    3400 uses
-    3500 uses
-    3600 uses
-    3700 uses
-    3800 uses
-    3900 uses
-    4000 uses
-    4100 uses
-    4200 uses
-    4300 uses
-    4400 uses
-    4500 uses
-    4600 uses
-    4700 uses
-    4800 uses
-    4900 uses
-    5000 uses
-    5100 uses
-    5200 uses
-    5300 uses
-    5400 uses
-    5500 uses
-    5600 uses
-    5700 uses
-    5800 uses
-    5900 uses
-    6000 uses
-    6100 uses
-    6200 uses
-    6300 uses
-    6400 uses
-    6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-    6900 uses
-    7000 uses
-    7100 uses
-    7200 uses
-    7300 uses
-    7400 uses
-    7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-Reading "cby_0__1_".
-    100 uses
-    200 uses
-    300 uses
-    400 uses
-    500 uses
-    600 uses
-    700 uses
-    800 uses
-    900 uses
-    1000 uses
-    1100 uses
-    1200 uses
-    1300 uses
-    1400 uses
-    1500 uses
-    1600 uses
-    1700 uses
-    1800 uses
-    1900 uses
-    2000 uses
-    2100 uses
-    2200 uses
-    2300 uses
-    2400 uses
-    2500 uses
-    2600 uses
-    2700 uses
-    2800 uses
-    2900 uses
-    3000 uses
-    3100 uses
-    3200 uses
-    3300 uses
-    3400 uses
-    3500 uses
-    3600 uses
-    3700 uses
-    3800 uses
-    3900 uses
-    4000 uses
-    4100 uses
-    4200 uses
-    4300 uses
-    4400 uses
-    4500 uses
-    4600 uses
-    4700 uses
-    4800 uses
-    4900 uses
-    5000 uses
-    5100 uses
-    5200 uses
-    5300 uses
-    5400 uses
-    5500 uses
-    5600 uses
-    5700 uses
-    5800 uses
-    5900 uses
-    6000 uses
-    6100 uses
-    6200 uses
-    6300 uses
-    6400 uses
-    6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-Reading "cbx_1__2_".
-    100 uses
-    200 uses
-    300 uses
-    400 uses
-    500 uses
-    600 uses
-    700 uses
-    800 uses
-    900 uses
-    1000 uses
-    1100 uses
-    1200 uses
-    1300 uses
-    1400 uses
-    1500 uses
-    1600 uses
-    1700 uses
-    1800 uses
-    1900 uses
-    2000 uses
-    2100 uses
-    2200 uses
-    2300 uses
-    2400 uses
-    2500 uses
-    2600 uses
-    2700 uses
-    2800 uses
-    2900 uses
-    3000 uses
-    3100 uses
-    3200 uses
-    3300 uses
-    3400 uses
-    3500 uses
-    3600 uses
-    3700 uses
-    3800 uses
-    3900 uses
-    4000 uses
-    4100 uses
-    4200 uses
-    4300 uses
-    4400 uses
-    4500 uses
-    4600 uses
-    4700 uses
-    4800 uses
-    4900 uses
-    5000 uses
-    5100 uses
-    5200 uses
-    5300 uses
-    5400 uses
-    5500 uses
-    5600 uses
-    5700 uses
-    5800 uses
-    5900 uses
-    6000 uses
-    6100 uses
-    6200 uses
-    6300 uses
-    6400 uses
-    6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-    6900 uses
-    7000 uses
-    7100 uses
-    7200 uses
-    7300 uses
-    7400 uses
-    7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-    21200 uses
-    21300 uses
-    21400 uses
-    21500 uses
-    21600 uses
-    21700 uses
-    21800 uses
-    21900 uses
-    22000 uses
-    22100 uses
-    22200 uses
-    22300 uses
-    22400 uses
-    22500 uses
-    22600 uses
-    22700 uses
-Reading "cbx_1__1_".
-    100 uses
-    200 uses
-    300 uses
-    400 uses
-    500 uses
-    600 uses
-    700 uses
-    800 uses
-    900 uses
-    1000 uses
-    1100 uses
-    1200 uses
-    1300 uses
-    1400 uses
-    1500 uses
-    1600 uses
-    1700 uses
-    1800 uses
-    1900 uses
-    2000 uses
-    2100 uses
-    2200 uses
-    2300 uses
-    2400 uses
-    2500 uses
-    2600 uses
-    2700 uses
-    2800 uses
-    2900 uses
-    3000 uses
-    3100 uses
-    3200 uses
-    3300 uses
-    3400 uses
-    3500 uses
-    3600 uses
-    3700 uses
-    3800 uses
-    3900 uses
-    4000 uses
-    4100 uses
-    4200 uses
-    4300 uses
-    4400 uses
-    4500 uses
-    4600 uses
-    4700 uses
-    4800 uses
-    4900 uses
-    5000 uses
-    5100 uses
-    5200 uses
-    5300 uses
-    5400 uses
-    5500 uses
-    5600 uses
-    5700 uses
-    5800 uses
-    5900 uses
-    6000 uses
-    6100 uses
-    6200 uses
-    6300 uses
-    6400 uses
-    6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-    6900 uses
-    7000 uses
-    7100 uses
-    7200 uses
-    7300 uses
-    7400 uses
-    7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-    21200 uses
-    21300 uses
-    21400 uses
-    21500 uses
-    21600 uses
-    21700 uses
 Reading "sb_1__1_".
     100 uses
     200 uses
@@ -4043,323 +2003,7 @@
     15600 uses
     15700 uses
     15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-    21200 uses
-    21300 uses
-    21400 uses
-    21500 uses
-    21600 uses
-    21700 uses
-    21800 uses
-    21900 uses
-    22000 uses
-    22100 uses
-    22200 uses
-    22300 uses
-    22400 uses
-    22500 uses
-    22600 uses
-    22700 uses
-    22800 uses
-    22900 uses
-    23000 uses
-    23100 uses
-    23200 uses
-    23300 uses
-    23400 uses
-    23500 uses
-    23600 uses
-    23700 uses
-    23800 uses
-    23900 uses
-    24000 uses
-    24100 uses
-    24200 uses
-    24300 uses
-    24400 uses
-    24500 uses
-    24600 uses
-    24700 uses
-    24800 uses
-    24900 uses
-    25000 uses
-    25100 uses
-    25200 uses
-    25300 uses
-    25400 uses
-    25500 uses
-    25600 uses
-    25700 uses
-    25800 uses
-    25900 uses
-    26000 uses
-    26100 uses
-    26200 uses
-    26300 uses
-    26400 uses
-    26500 uses
-    26600 uses
-    26700 uses
-    26800 uses
-    26900 uses
-    27000 uses
-    27100 uses
-    27200 uses
-    27300 uses
-    27400 uses
-    27500 uses
-    27600 uses
-    27700 uses
-    27800 uses
-    27900 uses
-    28000 uses
-    28100 uses
-    28200 uses
-    28300 uses
-    28400 uses
-    28500 uses
-    28600 uses
-    28700 uses
-    28800 uses
-    28900 uses
-    29000 uses
-    29100 uses
-    29200 uses
-    29300 uses
-    29400 uses
-    29500 uses
-    29600 uses
-    29700 uses
-    29800 uses
-    29900 uses
-    30000 uses
-    30100 uses
-    30200 uses
-    30300 uses
-    30400 uses
-    30500 uses
-    30600 uses
-    30700 uses
-    30800 uses
-    30900 uses
-    31000 uses
-    31100 uses
-    31200 uses
-    31300 uses
-    31400 uses
-    31500 uses
-    31600 uses
-    31700 uses
-    31800 uses
-    31900 uses
-    32000 uses
-    32100 uses
-    32200 uses
-    32300 uses
-    32400 uses
-    32500 uses
-    32600 uses
-    32700 uses
-    32800 uses
-    32900 uses
-    33000 uses
-    33100 uses
-    33200 uses
-    33300 uses
-    33400 uses
-    33500 uses
-    33600 uses
-    33700 uses
-    33800 uses
-    33900 uses
-    34000 uses
-    34100 uses
-    34200 uses
-    34300 uses
-    34400 uses
-    34500 uses
-    34600 uses
-    34700 uses
-    34800 uses
-    34900 uses
-    35000 uses
-    35100 uses
-    35200 uses
-    35300 uses
-    35400 uses
-    35500 uses
-    35600 uses
-    35700 uses
-    35800 uses
-    35900 uses
-    36000 uses
-    36100 uses
-    36200 uses
-    36300 uses
-    36400 uses
-    36500 uses
-    36600 uses
-    36700 uses
-    36800 uses
-    36900 uses
-    37000 uses
-    37100 uses
-    37200 uses
-    37300 uses
-    37400 uses
-    37500 uses
-    37600 uses
-    37700 uses
-    37800 uses
-    37900 uses
-    38000 uses
-    38100 uses
-    38200 uses
-    38300 uses
-    38400 uses
-    38500 uses
-    38600 uses
-    38700 uses
-    38800 uses
-    38900 uses
-    39000 uses
-    39100 uses
-    39200 uses
-    39300 uses
-    39400 uses
-    39500 uses
-    39600 uses
-    39700 uses
-    39800 uses
-    39900 uses
-    40000 uses
-    40100 uses
-    40200 uses
-    40300 uses
-    40400 uses
-    40500 uses
-    40600 uses
-    40700 uses
-    40800 uses
-    40900 uses
-    41000 uses
-    41100 uses
-    41200 uses
-    41300 uses
-    41400 uses
-    41500 uses
-    41600 uses
-    41700 uses
-    41800 uses
-    41900 uses
-    42000 uses
-    42100 uses
-    42200 uses
-    42300 uses
-    42400 uses
-    42500 uses
-    42600 uses
-    42700 uses
-    42800 uses
-    42900 uses
-    43000 uses
-    43100 uses
-    43200 uses
-    43300 uses
-    43400 uses
-    43500 uses
-    43600 uses
-    43700 uses
-    43800 uses
-    43900 uses
-    44000 uses
-    44100 uses
-    44200 uses
-    44300 uses
-    44400 uses
-    44500 uses
-    44600 uses
-    44700 uses
-    44800 uses
-    44900 uses
-    45000 uses
-    45100 uses
-    45200 uses
-    45300 uses
-    45400 uses
-    45500 uses
-    45600 uses
-    45700 uses
-    45800 uses
-    45900 uses
-    46000 uses
-    46100 uses
-    46200 uses
-    46300 uses
-    46400 uses
-    46500 uses
-    46600 uses
-    46700 uses
-    46800 uses
-    46900 uses
-    47000 uses
-    47100 uses
-    47200 uses
-    47300 uses
-    47400 uses
-Reading "sb_0__1_".
+Reading "sb_1__0_".
     100 uses
     200 uses
     300 uses
@@ -4470,179 +2114,194 @@
     10800 uses
     10900 uses
     11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-    21200 uses
-    21300 uses
-    21400 uses
-    21500 uses
-    21600 uses
-    21700 uses
-    21800 uses
-    21900 uses
-    22000 uses
-    22100 uses
-    22200 uses
-    22300 uses
-    22400 uses
-    22500 uses
-    22600 uses
-    22700 uses
-    22800 uses
-    22900 uses
-    23000 uses
-    23100 uses
-    23200 uses
-    23300 uses
-    23400 uses
-    23500 uses
-    23600 uses
-    23700 uses
-    23800 uses
-    23900 uses
-    24000 uses
-    24100 uses
-    24200 uses
-    24300 uses
-    24400 uses
-    24500 uses
-    24600 uses
-    24700 uses
-    24800 uses
-    24900 uses
-    25000 uses
-    25100 uses
-    25200 uses
-    25300 uses
-    25400 uses
-    25500 uses
-    25600 uses
-    25700 uses
-    25800 uses
-    25900 uses
-    26000 uses
-    26100 uses
-    26200 uses
-    26300 uses
-    26400 uses
-    26500 uses
-    26600 uses
-    26700 uses
-    26800 uses
-    26900 uses
-    27000 uses
-    27100 uses
-    27200 uses
-    27300 uses
-    27400 uses
-    27500 uses
-    27600 uses
-    27700 uses
-    27800 uses
-    27900 uses
-    28000 uses
-    28100 uses
-    28200 uses
-    28300 uses
+Reading "sb_0__2_".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+Reading "sb_0__1_".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+    4700 uses
+    4800 uses
+    4900 uses
+    5000 uses
+    5100 uses
+    5200 uses
+    5300 uses
+    5400 uses
+    5500 uses
+    5600 uses
+    5700 uses
+    5800 uses
+    5900 uses
+    6000 uses
+    6100 uses
+    6200 uses
+    6300 uses
+    6400 uses
+    6500 uses
+    6600 uses
+    6700 uses
+    6800 uses
+    6900 uses
+    7000 uses
+    7100 uses
+    7200 uses
+    7300 uses
+    7400 uses
+    7500 uses
+    7600 uses
+    7700 uses
+    7800 uses
+    7900 uses
+    8000 uses
+    8100 uses
+    8200 uses
+    8300 uses
+    8400 uses
+    8500 uses
+    8600 uses
+    8700 uses
+    8800 uses
+    8900 uses
+    9000 uses
+    9100 uses
+    9200 uses
+    9300 uses
+    9400 uses
+Reading "sb_0__0_".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
 Reading "grid_clb".
     100 uses
     200 uses
@@ -4742,204 +2401,6 @@
     9600 uses
     9700 uses
     9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-    21200 uses
-    21300 uses
-    21400 uses
-    21500 uses
-    21600 uses
-    21700 uses
-    21800 uses
-    21900 uses
-    22000 uses
-    22100 uses
-    22200 uses
-    22300 uses
-    22400 uses
-    22500 uses
-    22600 uses
-    22700 uses
-    22800 uses
-    22900 uses
-    23000 uses
-    23100 uses
-    23200 uses
-    23300 uses
-    23400 uses
-    23500 uses
-    23600 uses
-    23700 uses
-    23800 uses
-    23900 uses
-    24000 uses
-    24100 uses
-    24200 uses
-    24300 uses
-    24400 uses
-    24500 uses
-    24600 uses
-    24700 uses
-    24800 uses
-    24900 uses
-    25000 uses
-    25100 uses
-    25200 uses
-    25300 uses
-    25400 uses
-    25500 uses
-    25600 uses
-    25700 uses
-    25800 uses
-    25900 uses
-    26000 uses
-    26100 uses
-    26200 uses
-    26300 uses
-    26400 uses
-    26500 uses
-    26600 uses
-    26700 uses
-    26800 uses
-    26900 uses
-    27000 uses
-    27100 uses
-    27200 uses
-    27300 uses
-    27400 uses
-    27500 uses
-    27600 uses
-    27700 uses
-    27800 uses
-    27900 uses
-    28000 uses
-    28100 uses
-    28200 uses
-    28300 uses
-    28400 uses
-    28500 uses
-    28600 uses
-    28700 uses
-    28800 uses
-    28900 uses
-    29000 uses
-    29100 uses
-    29200 uses
-    29300 uses
-    29400 uses
-    29500 uses
-    29600 uses
 Reading "sky130_fd_io__overlay_vddio_hvc".
 Reading "sky130_fd_io__overlay_vccd_lvc".
 Reading "sky130_fd_io__top_power_lvc_wpad".
@@ -4971,7 +2432,7 @@
 Reading "sky130_fd_pr__via_m2m3__example_55959141808714".
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808766".
 Reading "sky130_fd_io__gpio_buf_localesdv2".
-Error while reading cell "sky130_fd_io__gpio_buf_localesdv2" (byte position 64673052): Unknown layer/datatype in boundary, layer=81 type=6
+Error while reading cell "sky130_fd_io__gpio_buf_localesdv2" (byte position 43159236): Unknown layer/datatype in boundary, layer=81 type=6
 Reading "sky130_fd_io__com_res_weak_v2".
 Reading "sky130_fd_io__xres_inv_hysv2".
 Reading "sky130_fd_io__tk_tie_r_out_esd".
@@ -4982,73 +2443,73 @@
     100 uses
 Reading "sky130_fd_io__corner_bus_overlay".
 Reading "sky130_fd_sc_hvl__conb_1".
-Error while reading cell "sky130_fd_sc_hvl__conb_1" (byte position 69081326): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__conb_1" (byte position 47563238): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__and3b_4".
-Error while reading cell "sky130_fd_sc_hd__and3b_4" (byte position 69088170): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__and3b_4" (byte position 47570218): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__mux4_1".
-Error while reading cell "sky130_fd_sc_hd__mux4_1" (byte position 69103714): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__mux4_1" (byte position 47580788): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__nor3b_4".
-Error while reading cell "sky130_fd_sc_hd__nor3b_4" (byte position 69113882): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__nor3b_4" (byte position 47593118): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__clkbuf_4".
-Error while reading cell "sky130_fd_sc_hd__clkbuf_4" (byte position 69119108): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__clkbuf_4" (byte position 47601992): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__nor4b_2".
-Error while reading cell "sky130_fd_sc_hd__nor4b_2" (byte position 69128446): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__nor4b_2" (byte position 47608320): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__and4b_2".
-Error while reading cell "sky130_fd_sc_hd__and4b_2" (byte position 69136726): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__and4b_2" (byte position 47617386): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__and4bb_2".
-Error while reading cell "sky130_fd_sc_hd__and4bb_2" (byte position 69144732): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__and4bb_2" (byte position 47626084): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__and4_2".
-Error while reading cell "sky130_fd_sc_hd__and4_2" (byte position 69152018): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__and4_2" (byte position 47633190): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__dlclkp_1".
-Error while reading cell "sky130_fd_sc_hd__dlclkp_1" (byte position 69162054): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__dlclkp_1" (byte position 47642560): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__and2_1".
-Error while reading cell "sky130_fd_sc_hd__and2_1" (byte position 69166964): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__and2_1" (byte position 47649984): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__dfxtp_1".
-Error while reading cell "sky130_fd_sc_hd__dfxtp_1" (byte position 69179094): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__dfxtp_1" (byte position 47658048): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__or2_2".
-Error while reading cell "sky130_fd_sc_hd__or2_2" (byte position 69183518): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__or2_2" (byte position 47667102): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__einvp_1".
-Error while reading cell "sky130_fd_sc_hd__einvp_1" (byte position 69188098): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__einvp_1" (byte position 47671498): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__clkinv_2".
-Error while reading cell "sky130_fd_sc_hd__clkinv_2" (byte position 69192410): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__clkinv_2" (byte position 47675872): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__clkinv_8".
-Error while reading cell "sky130_fd_sc_hd__clkinv_8" (byte position 69201670): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__clkinv_8" (byte position 47681048): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__einvn_8".
-Error while reading cell "sky130_fd_sc_hd__einvn_8" (byte position 69214002): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__einvn_8" (byte position 47691458): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__clkbuf_2".
-Error while reading cell "sky130_fd_sc_hd__clkbuf_2" (byte position 69218606): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__clkbuf_2" (byte position 47702048): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__einvp_2".
-Error while reading cell "sky130_fd_sc_hd__einvp_2" (byte position 69224862): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__einvp_2" (byte position 47707050): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__einvn_4".
-Error while reading cell "sky130_fd_sc_hd__einvn_4" (byte position 69232708): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__einvn_4" (byte position 47713738): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__and4_4".
-Error while reading cell "sky130_fd_sc_hd__and4_4" (byte position 69240166): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__and4_4" (byte position 47721454): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__a22oi_4".
-Error while reading cell "sky130_fd_sc_hd__a22oi_4" (byte position 69252226): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__a22oi_4" (byte position 47729698): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__a21o_4".
-Error while reading cell "sky130_fd_sc_hd__a21o_4" (byte position 69268572): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__a21o_4" (byte position 47741292): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__a21bo_4".
-Error while reading cell "sky130_fd_sc_hd__a21bo_4" (byte position 69285150): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__a21bo_4" (byte position 47749734): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__o21ai_4".
-Error while reading cell "sky130_fd_sc_hd__o21ai_4" (byte position 69301340): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__o21ai_4" (byte position 47757666): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__o32a_4".
-Error while reading cell "sky130_fd_sc_hd__o32a_4" (byte position 69313720): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__o32a_4" (byte position 47766858): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__or4_4".
-Error while reading cell "sky130_fd_sc_hd__or4_4" (byte position 69328228): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__or4_4" (byte position 47777940): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__o22a_4".
-Error while reading cell "sky130_fd_sc_hd__o22a_4" (byte position 69347562): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__o22a_4" (byte position 47786070): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__ebufn_2".
-Error while reading cell "sky130_fd_sc_hd__ebufn_2" (byte position 69354890): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__ebufn_2" (byte position 47794902): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__nor2_4".
-Error while reading cell "sky130_fd_sc_hd__nor2_4" (byte position 69369000): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__nor2_4" (byte position 47801876): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__or3_4".
-Error while reading cell "sky130_fd_sc_hd__or3_4" (byte position 69383196): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__or3_4" (byte position 47809132): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__a2bb2o_4".
-Error while reading cell "sky130_fd_sc_hd__a2bb2o_4" (byte position 69406088): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__a2bb2o_4" (byte position 47817814): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__o21a_4".
-Error while reading cell "sky130_fd_sc_hd__o21a_4" (byte position 69414144): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__o21a_4" (byte position 47828148): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__a211o_4".
-Error while reading cell "sky130_fd_sc_hd__a211o_4" (byte position 69432282): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__a211o_4" (byte position 47836702): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "pk_sram_1rw1r_32_256_8_sky130".
     100 uses
     200 uses
@@ -6609,44 +4070,40 @@
     155700 uses
     155800 uses
 Reading "sky130_fd_sc_hd__and3_4".
-Error while reading cell "sky130_fd_sc_hd__and3_4" (byte position 75766824): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__and3_4" (byte position 54165608): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__clkbuf_16".
-Error while reading cell "sky130_fd_sc_hd__clkbuf_16" (byte position 75792228): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__clkbuf_16" (byte position 54173910): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__and2_4".
-Error while reading cell "sky130_fd_sc_hd__and2_4" (byte position 75803682): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__and2_4" (byte position 54184986): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__a32o_4".
-Error while reading cell "sky130_fd_sc_hd__a32o_4" (byte position 75828036): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__a32o_4" (byte position 54192548): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__nand2_4".
-Error while reading cell "sky130_fd_sc_hd__nand2_4" (byte position 75843282): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__nand2_4" (byte position 54203058): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__or2_4".
-Error while reading cell "sky130_fd_sc_hd__or2_4" (byte position 75854766): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__or2_4" (byte position 54210608): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__dfrtp_4".
-Error while reading cell "sky130_fd_sc_hd__dfrtp_4" (byte position 75872762): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__dfrtp_4" (byte position 54221616): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__decap_8".
-Error while reading cell "sky130_fd_sc_hd__decap_8" (byte position 75879720): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__decap_8" (byte position 54233416): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
 Reading "sky130_fd_sc_hd__decap_4".
-Error while reading cell "sky130_fd_sc_hd__decap_4" (byte position 75891818): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__decap_4" (byte position 54240290): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__decap_12".
-Error while reading cell "sky130_fd_sc_hd__decap_12" (byte position 75900058): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__decap_12" (byte position 54243030): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__decap_3".
-Error while reading cell "sky130_fd_sc_hd__decap_3" (byte position 75905352): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__decap_3" (byte position 54247240): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__decap_6".
-Error while reading cell "sky130_fd_sc_hd__decap_6" (byte position 75911606): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__decap_6" (byte position 54249882): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hvl__lsbufhv2lv_1".
-Error while reading cell "sky130_fd_sc_hvl__lsbufhv2lv_1" (byte position 75930310): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__lsbufhv2lv_1" (byte position 54258326): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hvl__fill_2".
-Error while reading cell "sky130_fd_sc_hvl__fill_2" (byte position 75933178): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__fill_2" (byte position 54272138): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hvl__fill_1".
-Error while reading cell "sky130_fd_sc_hvl__fill_1" (byte position 75935614): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__fill_1" (byte position 54274958): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hvl__decap_8".
-Error while reading cell "sky130_fd_sc_hvl__decap_8" (byte position 75942502): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__decap_8" (byte position 54278198): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hvl__decap_4".
-Error while reading cell "sky130_fd_sc_hvl__decap_4" (byte position 75947310): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__dfxtp_4".
-Error while reading cell "sky130_fd_sc_hd__dfxtp_4" (byte position 75975580): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__diode_2".
-Error while reading cell "sky130_fd_sc_hd__diode_2" (byte position 75982418): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__decap_4" (byte position 54284862): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "fpga_top".
     100 uses
     200 uses
@@ -10075,6862 +7532,6 @@
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 Reading "sky130_ef_io__vddio_hvc_pad".
 Reading "sky130_ef_io__disconnect_vccd_slice_5um".
 Reading "sky130_ef_io__disconnect_vdda_slice_5um".
@@ -17363,9 +7964,9 @@
     40100 uses
     40200 uses
 Reading "sky130_fd_sc_hd__a41o_4".
-Error while reading cell "sky130_fd_sc_hd__a41o_4" (byte position 192169638): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__a41o_4" (byte position 127127052): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__o41a_4".
-Error while reading cell "sky130_fd_sc_hd__o41a_4" (byte position 192182810): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__o41a_4" (byte position 127139522): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "digital_pll".
     100 uses
     200 uses
@@ -17380,14 +7981,18 @@
     1100 uses
     1200 uses
 Reading "sky130_fd_sc_hd__a2111o_4".
-Error while reading cell "sky130_fd_sc_hd__a2111o_4" (byte position 194580694): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__a2111o_4" (byte position 129538238): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__a21oi_4".
-Error while reading cell "sky130_fd_sc_hd__a21oi_4" (byte position 194589296): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__a21oi_4" (byte position 129549700): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Error while reading cell "sky130_fd_sc_hd__dfxtp_4" (byte position 129560590): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sram_1rw1r_32_256_8_sky130".
 Reading "sky130_fd_sc_hd__dfstp_4".
-Error while reading cell "sky130_fd_sc_hd__dfstp_4" (byte position 194630678): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__dfstp_4" (byte position 129599540): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__diode_2".
+Error while reading cell "sky130_fd_sc_hd__diode_2" (byte position 129611794): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__einvp_8".
-Error while reading cell "sky130_fd_sc_hd__einvp_8" (byte position 194643368): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__einvp_8" (byte position 129618204): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
 Reading "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
 Reading "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
@@ -17397,14 +8002,14 @@
 Reading "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
 Reading "sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
 Reading "sky130_fd_sc_hvl__buf_8".
-Error while reading cell "sky130_fd_sc_hvl__buf_8" (byte position 194751174): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__buf_8" (byte position 129718556): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hvl__schmittbuf_1".
-Error while reading cell "sky130_fd_sc_hvl__schmittbuf_1" (byte position 194762346): Unknown layer/datatype in boundary, layer=236 type=0
-Error while reading cell "sky130_fd_sc_hvl__schmittbuf_1" (byte position 194762410): Unknown layer/datatype in boundary, layer=65 type=14
+Error while reading cell "sky130_fd_sc_hvl__schmittbuf_1" (byte position 129738526): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__schmittbuf_1" (byte position 129746250): Unknown layer/datatype in boundary, layer=65 type=14
 Reading "sky130_fd_sc_hvl__inv_8".
-Error while reading cell "sky130_fd_sc_hvl__inv_8" (byte position 194779708): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__inv_8" (byte position 129749582): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hvl__fill_4".
-Error while reading cell "sky130_fd_sc_hvl__fill_4" (byte position 194783296): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__fill_4" (byte position 129765120): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
 Reading "sky130_fd_pr__cap_mim_m3_2_W5U4AW".
 Reading "sky130_fd_pr__cap_mim_m3_1_WRT4AW".
diff --git a/checks/magic_merge_user_project_wrapper.log b/checks/magic_merge_user_project_wrapper.log
index a81f71f..19bbd9b 100644
--- a/checks/magic_merge_user_project_wrapper.log
+++ b/checks/magic_merge_user_project_wrapper.log
@@ -12,7 +12,7 @@
 Loading "../SOFA-Chips/SCRIPT/merge_fpga_top.tcl" from command line.
 Warning: Calma reading is not undoable!  I hope that's OK.
 Library written using GDS-II Release 5.0
-Library name: fpga_top_icv_in_design.gdsgz.merge566544152
+Library name: fpga_top_icv_in_design.gdsgz.merge1354503035
 Reading "sky130_fd_sc_hd__a2111o_1".
 Reading "sky130_fd_sc_hd__a2111o_2".
 Reading "sky130_fd_sc_hd__a2111o_4".
@@ -5189,17 +5189,17 @@
    Writing cell $$M2M3_PR
    Writing cell $$M1M2_PR
    Writing cell $$M4M5_PR_16000_16000_2_1
-   Writing cell sky130_fd_sc_hd__fill_2
-   Writing cell sky130_fd_sc_hd__fill_8
    Writing cell sky130_fd_sc_hd__fill_4
+   Writing cell sky130_fd_sc_hd__fill_8
    Writing cell sky130_fd_sc_hd__fill_1
+   Writing cell sky130_fd_sc_hd__fill_2
    Writing cell sky130_fd_sc_hd__buf_1
    Writing cell sky130_fd_sc_hd__clkbuf_1
+   Writing cell sky130_fd_sc_hd__buf_2
    Writing cell sky130_fd_sc_hd__buf_6
    Writing cell sky130_fd_sc_hd__bufbuf_16
    Writing cell sky130_fd_sc_hd__buf_4
    Writing cell sky130_fd_sc_hd__buf_8
-   Writing cell sky130_fd_sc_hd__buf_2
    Writing cell sky130_fd_sc_hd__dfrtp_1
    Writing cell sky130_uuopenfpga_cc_hd_invmux3_1
    Writing cell sky130_fd_sc_hd__nor2_1
@@ -5208,9 +5208,9 @@
    Writing cell sky130_fd_sc_hd__inv_1
    Writing cell sky130_fd_sc_hd__sdfrtp_1
    Writing cell sky130_fd_sc_hd__mux2_1
+   Writing cell sky130_fd_sc_hd__inv_2
    Writing cell sky130_fd_sc_hd__or2_0
    Writing cell sky130_fd_sc_hd__inv_8
-   Writing cell sky130_fd_sc_hd__inv_2
    Writing cell sky130_fd_sc_hd__dlygate4sd1_1
    Writing cell sky130_fd_sc_hd__dlygate4sd3_1
    Writing cell sky130_fd_sc_hd__clkbuf_8
diff --git a/checks/manifest_check.mag.log b/checks/manifest_check.mag.log
index 293ab27..40c81e2 100644
--- a/checks/manifest_check.mag.log
+++ b/checks/manifest_check.mag.log
@@ -1,2 +1,2 @@
 caravel.mag: OK
-.magicrc: FAILED
+.magicrc: OK
diff --git a/checks/spdx_compliance_report.log b/checks/spdx_compliance_report.log
index 023741b..cbc42ba 100644
--- a/checks/spdx_compliance_report.log
+++ b/checks/spdx_compliance_report.log
@@ -4,8 +4,6 @@
 /usr/local/workspace/Caravel-SOFA-CHD/source_commit_hash.txt
 /usr/local/workspace/Caravel-SOFA-CHD/doc/caravel_datasheet.ps
 /usr/local/workspace/Caravel-SOFA-CHD/mag/clamp_list.txt
-/usr/local/workspace/Caravel-SOFA-CHD/mag/.magicrc
-/usr/local/workspace/Caravel-SOFA-CHD/maglef/.magicrc
 /usr/local/workspace/Caravel-SOFA-CHD/openlane/chip_dimensions.txt
 /usr/local/workspace/Caravel-SOFA-CHD/openlane/mgmt_protect/pdn.tcl
 /usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/DFFRAM.spice
diff --git a/gds/caravel.gds.gz b/gds/caravel.gds.gz
index e7d23e1..44f8a3c 100644
--- a/gds/caravel.gds.gz
+++ b/gds/caravel.gds.gz
Binary files differ
diff --git a/gds/fpga_top_icv_in_design.gds.gz.sha1 b/gds/fpga_top_icv_in_design.gds.gz.sha1
new file mode 100644
index 0000000..61f76cd
--- /dev/null
+++ b/gds/fpga_top_icv_in_design.gds.gz.sha1
@@ -0,0 +1 @@
+0e8c834d847b254163f74bf3cc1a780f5d87c5be ./gds/fpga_top_icv_in_design.gds.gz
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 4a873b8..d33ce77 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/source_commit_hash.txt b/source_commit_hash.txt
index 68728c6..23289f0 100644
--- a/source_commit_hash.txt
+++ b/source_commit_hash.txt
@@ -1,4 +1,7 @@
 = = = = = = = = = = = = = = = =
+Date       Sun Dec 27 16:26:44 UTC 2020
+GITHUB_SHA -
+= = = = = = = = = = = = = = = =
 Date       Sun Dec 20 23:06:10 UTC 2020
 GITHUB_SHA -
 = = = = = = = = = = = = = = = =
diff --git a/verilog/OpenFPGA_Verilog/fabric_netlists.v b/verilog/OpenFPGA_Verilog/fabric_netlists.v
index 6529b19..d818117 100644
--- a/verilog/OpenFPGA_Verilog/fabric_netlists.v
+++ b/verilog/OpenFPGA_Verilog/fabric_netlists.v
@@ -12,18 +12,18 @@
 `include "./SRC/fpga_defines.v"
 
 //
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/sky130_fd_sc_hd_wrapper.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/sky130_fd_sc_hd_wrapper.v"
 //
 `include "./SRC/sub_module/inv_buf_passgate.v"
 `include "./SRC/sub_module/arch_encoder.v"
diff --git a/verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v b/verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
index ec041fb..4b5409c 100644
--- a/verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
+++ b/verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
@@ -76,7 +76,8 @@
 
 wire [0:0] direct_interc_10_out;
 wire [0:0] direct_interc_11_out;
-wire [0:0] direct_interc_2_out;
+wire [0:0] direct_interc_12_out;
+wire [0:0] direct_interc_13_out;
 wire [0:0] direct_interc_3_out;
 wire [0:0] direct_interc_4_out;
 wire [0:0] direct_interc_5_out;
@@ -87,9 +88,8 @@
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q;
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q;
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout;
 wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out;
-wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin;
-wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cout;
 wire [0:0] mux_1level_size2_0_out;
 wire [0:1] mux_1level_size2_0_sram;
 wire [0:0] mux_1level_size2_1_out;
@@ -112,28 +112,28 @@
 	logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
 		.pReset(pReset[0]),
 		.prog_clk(prog_clk[0]),
-		.frac_logic_in({direct_interc_2_out[0], direct_interc_3_out[0], direct_interc_4_out[0], direct_interc_5_out[0]}),
-		.frac_logic_cin(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin[0]),
+		.frac_logic_in({direct_interc_3_out[0], direct_interc_4_out[0], direct_interc_5_out[0], direct_interc_6_out[0]}),
+		.frac_logic_cin(direct_interc_7_out[0]),
 		.ccff_head(ccff_head[0]),
 		.frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0:1]),
-		.frac_logic_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cout[0]),
+		.frac_logic_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout[0]),
 		.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0]));
 
 	logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
 		.Test_en(Test_en[0]),
 		.ff_D(mux_1level_size2_0_out[0]),
-		.ff_DI(direct_interc_6_out[0]),
-		.ff_reset(direct_interc_7_out[0]),
+		.ff_DI(direct_interc_8_out[0]),
+		.ff_reset(direct_interc_9_out[0]),
 		.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
-		.ff_clk(direct_interc_8_out[0]));
+		.ff_clk(direct_interc_10_out[0]));
 
 	logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
 		.Test_en(Test_en[0]),
 		.ff_D(mux_1level_size2_1_out[0]),
-		.ff_DI(direct_interc_9_out[0]),
-		.ff_reset(direct_interc_10_out[0]),
+		.ff_DI(direct_interc_11_out[0]),
+		.ff_reset(direct_interc_12_out[0]),
 		.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),
-		.ff_clk(direct_interc_11_out[0]));
+		.ff_clk(direct_interc_13_out[0]));
 
 	mux_1level_tapbuf_size2 mux_fabric_out_0 (
 		.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}),
@@ -170,45 +170,53 @@
 		.out(fabric_sc_out[0]));
 
 	direct_interc direct_interc_2_ (
-		.in(fabric_in[0]),
-		.out(direct_interc_2_out[0]));
+		.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout[0]),
+		.out(fabric_cout[0]));
 
 	direct_interc direct_interc_3_ (
-		.in(fabric_in[1]),
+		.in(fabric_in[0]),
 		.out(direct_interc_3_out[0]));
 
 	direct_interc direct_interc_4_ (
-		.in(fabric_in[2]),
+		.in(fabric_in[1]),
 		.out(direct_interc_4_out[0]));
 
 	direct_interc direct_interc_5_ (
-		.in(fabric_in[3]),
+		.in(fabric_in[2]),
 		.out(direct_interc_5_out[0]));
 
 	direct_interc direct_interc_6_ (
-		.in(fabric_sc_in[0]),
+		.in(fabric_in[3]),
 		.out(direct_interc_6_out[0]));
 
 	direct_interc direct_interc_7_ (
-		.in(fabric_reset[0]),
+		.in(fabric_cin[0]),
 		.out(direct_interc_7_out[0]));
 
 	direct_interc direct_interc_8_ (
-		.in(fabric_clk[0]),
+		.in(fabric_sc_in[0]),
 		.out(direct_interc_8_out[0]));
 
 	direct_interc direct_interc_9_ (
-		.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
+		.in(fabric_reset[0]),
 		.out(direct_interc_9_out[0]));
 
 	direct_interc direct_interc_10_ (
-		.in(fabric_reset[0]),
+		.in(fabric_clk[0]),
 		.out(direct_interc_10_out[0]));
 
 	direct_interc direct_interc_11_ (
-		.in(fabric_clk[0]),
+		.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
 		.out(direct_interc_11_out[0]));
 
+	direct_interc direct_interc_12_ (
+		.in(fabric_reset[0]),
+		.out(direct_interc_12_out[0]));
+
+	direct_interc direct_interc_13_ (
+		.in(fabric_clk[0]),
+		.out(direct_interc_13_out[0]));
+
 	mux_1level_size2 mux_ff_0_D_0 (
 		.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0], fabric_reg_in[0]}),
 		.sram(mux_1level_size2_0_sram[0:1]),
diff --git a/verilog/gl/caravel_sofa_chd_top.v b/verilog/gl/caravel_sofa_chd_top.v
index cb5b743..8d31ce2 100644
--- a/verilog/gl/caravel_sofa_chd_top.v
+++ b/verilog/gl/caravel_sofa_chd_top.v
@@ -5,30 +5,35 @@
 //
 //
 module cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , 
-    prog_clk , ccff_head , ccff_tail , mem_out ) ;
+    prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
 
 wire copt_net_117 ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_117 ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_117 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_118 ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1368 ( .A ( copt_net_117 ) , 
-    .X ( copt_net_115 ) ) ;
+    .X ( copt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1370 ( .A ( copt_net_115 ) , 
-    .X ( mem_out[0] ) ) ;
+    .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1371 ( .A ( mem_out[0] ) , 
-    .X ( copt_net_118 ) ) ;
+    .X ( copt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
-    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
 input  SOC_IN ;
 output SOC_OUT ;
 output SOC_DIR ;
@@ -36,25 +41,34 @@
 input  FPGA_OUT ;
 input  FPGA_DIR ;
 input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
-    .B ( IO_ISOL_N ) , .Y ( aps_rename_513_ ) ) ;
-sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_79 ) , .Y ( SOC_DIR_N ) ) ;
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_513_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_79 ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
-    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
-    .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) ) ;
+    .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_513_ ) , 
-    .Y ( BUF_net_81 ) ) ;
+    .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , 
     prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
-    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -65,25 +79,31 @@
 input  [0:0] ccff_head ;
 output [0:0] iopad_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
 
 cby_2__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
     .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
     .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
     .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
     .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
-    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
-    ccff_tail ) ;
+    ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -94,6 +114,11 @@
 input  [0:0] ccff_head ;
 output [0:0] io_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
@@ -101,296 +126,428 @@
     .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
     .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
-    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size10_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size10_mem_6 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size10_mem_5 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size10_mem_4 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size10_mem_3 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size10_mem_2 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size10_mem_1 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size10_mem_0 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input2_mem2 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input2_mem2 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_58 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_58 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_57 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_57 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_32 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_32 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size10 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size10 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -401,166 +558,225 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_512_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_512_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_32 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_57 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_58 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_2__1__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( aps_rename_512_ ) , 
-    .Y ( BUF_net_100 ) ) ;
+    .Y ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input2_mem2_6 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input2_mem2_6 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_56 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_55 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_55 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_54 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_54 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_31 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_31 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_30 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_30 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size10_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -571,166 +787,225 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_511_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_511_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_31 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_54 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_55 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_56 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_2__1__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_511_ ) , 
-    .Y ( BUF_net_98 ) ) ;
+    .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input2_mem2_5 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input2_mem2_5 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_52 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_52 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_51 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_51 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_29 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_29 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_28 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_28 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size10_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -741,166 +1016,225 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_510_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_510_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_29 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_51 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_52 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_53 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_2__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) , 
-    .Y ( BUF_net_96 ) ) ;
+    .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input2_mem2_4 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input2_mem2_4 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_49 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_49 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_48 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_48 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_27 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_27 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_26 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_26 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size10_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -911,163 +1245,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_27 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_48 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_49 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_50 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_2__1__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input2_mem2_3 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input2_mem2_3 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_46 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_46 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_45 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_45 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_25 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_25 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_24 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_24 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size10_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -1078,163 +1470,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_25 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_45 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_46 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_47 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_2__1__mux_2level_basis_input2_mem2_3 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input2_mem2_2 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input2_mem2_2 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_43 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_43 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_42 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_42 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_23 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_23 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_22 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_22 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size10_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -1245,166 +1695,225 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_509_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_509_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_23 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_42 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_43 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_44 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_2__1__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_509_ ) , 
-    .Y ( BUF_net_94 ) ) ;
+    .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input2_mem2_1 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input2_mem2_1 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_40 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_40 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_39 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_39 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_21 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_21 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_20 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_20 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size10_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -1415,164 +1924,223 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_92 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_92 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_21 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_39 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_40 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_41 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_2__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( net_net_92 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( net_net_92 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input2_mem2_0 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input2_mem2_0 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_37 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_37 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_36 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_36 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_19 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_19 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_18 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_18 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size10_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -1583,366 +2151,515 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_19 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_36 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_37 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_38 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_2__1__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size12_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size12_mem_7 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size12_mem_6 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size12_mem_5 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size12_mem_4 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size12_mem_3 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size12_mem_2 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size12_mem_1 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size12_mem_0 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_123 ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( ccff_head[0] ) , 
-    .X ( copt_net_108 ) ) ;
+    .X ( copt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( copt_net_108 ) , 
-    .X ( copt_net_109 ) ) ;
+    .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_111 ) , 
-    .X ( copt_net_110 ) ) ;
+    .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( copt_net_109 ) , 
-    .X ( copt_net_111 ) ) ;
+    .X ( copt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1365 ( .A ( copt_net_110 ) , 
-    .X ( copt_net_112 ) ) ;
+    .X ( copt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1366 ( .A ( copt_net_112 ) , 
-    .X ( copt_net_113 ) ) ;
+    .X ( copt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1374 ( .A ( copt_net_113 ) , 
-    .X ( ropt_net_121 ) ) ;
+    .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1375 ( .A ( ropt_net_121 ) , 
-    .X ( ropt_net_122 ) ) ;
+    .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 ropt_h_inst_1376 ( .A ( ropt_net_122 ) , 
-    .X ( ropt_net_123 ) ) ;
+    .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_34 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_34 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_17 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_17 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_16 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_16 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size12 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -1953,171 +2670,231 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_17 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_32 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_33 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_34 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_35 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( aps_rename_508_ ) , 
-    .Y ( BUF_net_91 ) ) ;
+    .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_15 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_15 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_14 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_14 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size12_7 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size12_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -2128,168 +2905,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_15 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_28 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_29 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_30 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_13 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_13 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_12 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_12 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size12_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -2300,171 +3136,231 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_13 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_24 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_25 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_26 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_507_ ) , 
-    .Y ( BUF_net_89 ) ) ;
+    .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_11 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_11 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_10 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_10 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size12_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -2475,169 +3371,229 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_87 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_87 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_11 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_20 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_21 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_22 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( net_net_87 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( net_net_87 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_9 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_9 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_8 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_8 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size12_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -2648,168 +3604,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_9 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_16 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_17 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_18 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_7 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_7 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_6 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size12_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -2820,171 +3835,231 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_7 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_12 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_13 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_14 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_506_ ) , 
-    .Y ( BUF_net_86 ) ) ;
+    .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_5 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_4 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size12_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -2995,169 +4070,229 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_84 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_84 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_8 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_9 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_10 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( net_net_84 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( net_net_84 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_3 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,