gds from drc cleaned mag file
1 file changed
tree: 9e6e1cc336db300b1ef586067ef33a027db94983
  1. .travis.yml
  2. .travisCI/
  4. Makefile
  6. def/
  7. doc/
  8. gds/
  9. info.yaml
  10. lef/
  11. macros/
  12. mag/
  13. maglef/
  15. ngspice/
  16. openlane/
  17. qflow/
  18. scripts/
  19. spi/
  20. utils/
  21. verilog/

Analog & RF IPs

LVDS Receiver

Design of an LVDS receiver in Skywater 130nm. The receiver architecture consists of a biasing stage followed by two amplification stages—the simulated maximum frequency of 1.5Gs at 1.8V, TT corner & 25C.


Biasing Stage – AC coupled with common-mode biasing of 1.2V

CML Stage – Amplification stage with a gain of 5

Differential Stage – Gain of ~8

Ring Oscillator

7 stage RO with enable

Designed with Skywater standard cells library. AND gate followed by 7 smallest inverters

Differential VCO

5 stages of differential delay cells. Delay cell consists of symmetric loads


Self bias generator with startup circuit

Power Amplifier

Linear Class AB power amplifier. On-chip inductor is designed as a test structure by using top metal layer. Actual inductance & Q factor is unknown

Folded Cascode

Differential input single ended Folded Cascode Opamp; 1Mhz unity gain frequency, 60 degree phase margin & a gain of 79dB