final gds & drc results
282 files changed
tree: 4da9d8cc062aa1227da8e67378cc6da9c870734f
  1. .travis.yml
  2. .travisCI/
  3. LICENSE
  4. Makefile
  5. Makefile.master
  6. README.md
  7. def/
  8. docs/
  9. gds/
  10. info.yaml
  11. lef/
  12. macros/
  13. mag/
  14. maglef/
  15. manifest
  16. mpw-one-b.md
  17. ngspice/
  18. openlane/
  19. qflow/
  20. scripts/
  21. signoff/
  22. spi/
  23. utils/
  24. verilog/
README.md

Analog & RF IPs

LVDS Receiver

Design of an LVDS receiver in Skywater 130nm. The receiver architecture consists of a biasing stage followed by two amplification stages—the simulated maximum frequency of 1.5Gs at 1.8V, TT corner & 25C.

Submodules:

Biasing Stage – AC coupled with common-mode biasing of 1.2V

CML Stage – Amplification stage with a gain of 5

Differential Stage – Gain of ~8

Ring Oscillator

7 stage RO with enable

Designed with Skywater standard cells library. AND gate followed by 7 smallest inverters

Differential VCO

5 stages of differential delay cells. Delay cell consists of symmetric loads

Submodule:

Self bias generator with startup circuit

Power Amplifier

Linear Class AB power amplifier. On-chip inductor is designed as a test structure by using top metal layer. Actual inductance & Q factor is unknown

Folded Cascode

Differential input single ended Folded Cascode Opamp; 1Mhz unity gain frequency, 60 degree phase margin & a gain of 79dB