analog-collection: Collection of analog circuits including LVDS receiver, ring oscillator, differential VCO, power amplifier and folded cascode opamp.

Clone this repo:
  1. b44c4ba final gds & drc results by Jeff DiCorpo · 4 months ago main mpw-one-final
  2. b398074 Corrected the MiM cap. by Tim Edwards · 5 months ago
  3. 040355e final gds & drc results by Jeff DiCorpo · 5 months ago
  4. 9164ebc gds from drc cleaned mag file by affanabbasi · 5 months ago
  5. 6c4c06c Delete user_project_wrapper.gds by affanabbasi · 5 months ago

Analog & RF IPs

LVDS Receiver

Design of an LVDS receiver in Skywater 130nm. The receiver architecture consists of a biasing stage followed by two amplification stages—the simulated maximum frequency of 1.5Gs at 1.8V, TT corner & 25C.


Biasing Stage – AC coupled with common-mode biasing of 1.2V

CML Stage – Amplification stage with a gain of 5

Differential Stage – Gain of ~8

Ring Oscillator

7 stage RO with enable

Designed with Skywater standard cells library. AND gate followed by 7 smallest inverters

Differential VCO

5 stages of differential delay cells. Delay cell consists of symmetric loads


Self bias generator with startup circuit

Power Amplifier

Linear Class AB power amplifier. On-chip inductor is designed as a test structure by using top metal layer. Actual inductance & Q factor is unknown

Folded Cascode

Differential input single ended Folded Cascode Opamp; 1Mhz unity gain frequency, 60 degree phase margin & a gain of 79dB