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  1. .travis.yml
  2. .travisCI/
  3. LICENSE
  4. Makefile
  5. README.md
  6. def/
  7. doc/
  8. gds/
  9. info.yaml
  10. lef/
  11. macros/
  12. mag/
  13. maglef/
  14. mpw-one-b.md
  15. ngspice/
  16. openlane/
  17. qflow/
  18. scripts/
  19. spi/
  20. utils/
  21. verilog/
README.md

Caravel_N5_SoC

The repo contains the N5 SoC integratin with the Caravel chip. For the SoC related development, refer to N5 SoC

Caravel Integration

Verilog View

The SoC utilizes the caravel IO ports and logic analyzer probes. Refer to user_project_wrapper.v

Caravel-IOChameloen SoCMode
io[13:0]GPIOBi-directional
io[17:14]flashBi-directional
io[18]flash clkOutput
io[19]flash enableOutput
io[20]UART0 RXInput
io[21]UART0 TXOutput
io[22]UART1 RXInput
io[23]UART1 TXOutput
io[24]SPI0 IInput
io[25]SPI0 OOutput
io[26]SPI0 SSnOutput
io[27]SPI0 CLKOutput
io[28]SPI1 IInput
io[29]SPI1 OOutput
io[30]SPI1 SSnOutput
io[31]SPI1 CLKOutput
io[32]I2C0 IOBi-directional
io[33]I2C0 IOBi-directional
io[34]I2C1 IOBi-directional
io[35]I2C1 IOBi-directional
io[36]pwm0Output
io[37]pwm1Output

GDS View