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  1. d11e1f2 final gds & drc results by Jeff DiCorpo · 2 days ago master
  2. 7e3e0b9 Added macros summary by manarabdelaty · 10 days ago
  3. e3dce55 Added nfive summary to the report by Mohamed Shalan · 10 days ago
  4. ed3a9f7 Added by Mohamed Shalan · 11 days ago
  5. 20e0af1 Added final summary report by Mohamed Shalan · 11 days ago


The repo contains the N5 SoC integratin with the Caravel chip. For the SoC related development, refer to N5 SoC

Caravel Integration

Verilog View

The SoC utilizes the caravel IO ports and logic analyzer probes. Refer to user_project_wrapper.v

Caravel-IOChameloen SoCMode
io[18]flash clkOutput
io[19]flash enableOutput
io[20]UART0 RXInput
io[21]UART0 TXOutput
io[22]UART1 RXInput
io[23]UART1 TXOutput
io[24]SPI0 IInput
io[25]SPI0 OOutput
io[26]SPI0 SSnOutput
io[27]SPI0 CLKOutput
io[28]SPI1 IInput
io[29]SPI1 OOutput
io[30]SPI1 SSnOutput
io[31]SPI1 CLKOutput
io[32]I2C0 IOBi-directional
io[33]I2C0 IOBi-directional
io[34]I2C1 IOBi-directional
io[35]I2C1 IOBi-directional

GDS View