SoC-nfive32: SoC built around N5 (RV32IC) CPU to validate several open-source IPs.

Clone this repo:
  1. c1ebee9 update info.yaml from user repo by Jeff DiCorpo · 8 weeks ago master
  2. c7de030 final gds & drc results by Jeff DiCorpo · 9 weeks ago mpw-one-final
  3. a9446f9 final gds & drc results by Jeff DiCorpo · 3 months ago
  4. a256605 Update wrapper to have correct pdn offset by Mohamed Shalan · 3 months ago
  5. 7e3e0b9 Added macros summary by manarabdelaty · 3 months ago

Caravel_N5_SoC

The repo contains the N5 SoC integratin with the Caravel chip. For the SoC related development, refer to N5 SoC

Caravel Integration

Verilog View

The SoC utilizes the caravel IO ports and logic analyzer probes. Refer to user_project_wrapper.v

Caravel-IOChameloen SoCMode
io[13:0]GPIOBi-directional
io[17:14]flashBi-directional
io[18]flash clkOutput
io[19]flash enableOutput
io[20]UART0 RXInput
io[21]UART0 TXOutput
io[22]UART1 RXInput
io[23]UART1 TXOutput
io[24]SPI0 IInput
io[25]SPI0 OOutput
io[26]SPI0 SSnOutput
io[27]SPI0 CLKOutput
io[28]SPI1 IInput
io[29]SPI1 OOutput
io[30]SPI1 SSnOutput
io[31]SPI1 CLKOutput
io[32]I2C0 IOBi-directional
io[33]I2C0 IOBi-directional
io[34]I2C1 IOBi-directional
io[35]I2C1 IOBi-directional
io[36]pwm0Output
io[37]pwm1Output

GDS View