final gds & drc results
329 files changed
tree: b3b4cbb4e692c52298288057775bd3d31a2cbc2a
  1. .travis.yml
  2. .travisCI/
  3. LICENSE
  4. Makefile
  5. Makefile.master
  6. README.md
  7. checks/
  8. def/
  9. docs/
  10. gds/
  11. info.yaml
  12. lef/
  13. macros/
  14. mag/
  15. maglef/
  16. manifest
  17. mpw-one-b.md
  18. ngspice/
  19. openlane/
  20. qflow/
  21. scripts/
  22. signoff/
  23. spi/
  24. utils/
  25. verilog/
README.md

Caravel-OpenFPGA-EF

The repo contains the FPGA layout integration with the Caravel chip. Thee layout is an 8x8 FPGA fabric generated using OpenFPGA and hardened using OpenLANE.

Caravel Integration

Verilog View

The 8x8 fpga interface to the managent area can be found at user_project_wrapper.v . The fabric is conncted to the managemtent area logic analyzer, wishbone bus, and IO-ports.

Caravel-IOFPGAMode
io[0]test_enInput
io[1]IO_ISOL_NInput
io[7:2]EMBED-IO[10:15]Bi-directional
io[11]sc_tailOutput
io[12]ccff_headInput
io[13:14]EMBED-IO[8:9]Bi-directional
io[17:23]EMBED-IO[1:8]Bi-directional
io[24]EMBED-IO[0]*Bi-directional
io[25]wb_la_switchInput
io[26]sc_headInput
io[27:34]EMBED-IO[88-95]Bi-directional
io[35]ccff_tailOutput
io[36]clkInput
io[37]prog_clkInput

GDS View