Updated layout to remove floating pins
32 files changed
tree: 9208f2435fe2e227598fb6f662e0ffe9070d7c0a
  1. .travis.yml
  2. .travisCI/
  4. Makefile
  5. README.md
  6. def/
  7. doc/
  8. gds/
  9. info.yaml
  10. lef/
  11. macros/
  12. mag/
  13. maglef/
  14. mpw-one-b.md
  15. ngspice/
  16. openlane/
  17. qflow/
  18. scripts/
  19. spi/
  20. utils/
  21. verilog/


The repo contains the FPGA layout integration with the Caravel chip. Thee layout is an 8x8 FPGA fabric generated using OpenFPGA and hardened using OpenLANE.

Caravel Integration

Verilog View

The 8x8 fpga interface to the managent area can be found at fpga_top.v . The fabric is conncted to the managemtent area logic analyzer and wishbone bus.

GDS View

To Do

  1. Functional and Gate-level verification
  2. DRC and LVS checks