Clone this repo:

Branches

  1. d3475fa final gds & drc results by Jeff DiCorpo · 4 days ago master
  2. b73a73e Updated summary report to include all macros by Mohamed Shalan · 10 days ago
  3. 88a492b Added reports by Mohamed Shalan · 11 days ago
  4. 038a13a Update README.md by Manar · 11 days ago
  5. 53ba239 Updated layout to remove floating pins by manarabdelaty · 3 weeks ago

Caravel-OpenFPGA-EF

The repo contains the FPGA layout integration with the Caravel chip. Thee layout is an 8x8 FPGA fabric generated using OpenFPGA and hardened using OpenLANE.

Caravel Integration

Verilog View

The 8x8 fpga interface to the managent area can be found at user_project_wrapper.v . The fabric is conncted to the managemtent area logic analyzer, wishbone bus, and IO-ports.

Caravel-IOFPGAMode
io[0]test_enInput
io[1]IO_ISOL_NInput
io[7:2]EMBED-IO[10:15]Bi-directional
io[11]sc_tailOutput
io[12]ccff_headInput
io[13:14]EMBED-IO[8:9]Bi-directional
io[17:23]EMBED-IO[1:8]Bi-directional
io[24]EMBED-IO[0]*Bi-directional
io[25]wb_la_switchInput
io[26]sc_headInput
io[27:34]EMBED-IO[88-95]Bi-directional
io[35]ccff_tailOutput
io[36]clkInput
io[37]prog_clkInput

GDS View