Add Microwatt to Caravel

This adds the Microwatt OpenPOWER core to the Caravel project.
diff --git a/README.rst b/README.rst
index 62c2da9..3d69ae9 100644
--- a/README.rst
+++ b/README.rst
@@ -18,251 +18,18 @@
    # SPDX-License-Identifier: Apache-2.0
    -->
 
-CIIC Harness
-============
+Microwatt on Caravel
+====================
 
-|License| |Documentation Status| |Build Status|
-
-A template SoC for Google SKY130 free shuttles. It is still WIP. The
-current SoC architecture is given below.
+The Microwatt 64 bit OpenPOWER core integrated into the Caravel Google SKY130 free shuttles.
 
 .. raw:: html
 
    <p align="center">
-   <img src="/docs/source/_static/ciic_harness.png" width="75%" height="75%">
+   <img src="/docs/source/_static/microwatt-caravel.png" width="75%" height="75%">
    </p>
 
-Datasheet and detailed documentation exists here:
-https://caravel-harness.readthedocs.io/en/develop/
+Tests
+=====
 
-.. raw:: html
-
-   <!---
-   # SPDX-FileCopyrightText: 2020 Efabless Corporation
-   #
-   # Licensed under the Apache License, Version 2.0 (the "License");
-   # you may not use this file except in compliance with the License.
-   # You may obtain a copy of the License at
-   #
-   #      http://www.apache.org/licenses/LICENSE-2.0
-   #
-   # Unless required by applicable law or agreed to in writing, software
-   # distributed under the License is distributed on an "AS IS" BASIS,
-   # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-   # See the License for the specific language governing permissions and
-   # limitations under the License.
-   #
-   # SPDX-License-Identifier: Apache-2.0
-   -->
-.. _getting-started:
-
-Getting Started
-===============
-
--  For information on tooling and versioning, please refer to `tool-versioning.rst <./docs/source/tool-versioning.rst>`__.
-
-Start by cloning the repo and uncompressing the files.
-
-.. code:: bash
-
-    git clone https://github.com/efabless/caravel.git
-    cd caravel
-    make uncompress
-
-Then you need to install the open\_pdks prerequisite:
-
--  `Magic VLSI Layout
-   Tool <http://opencircuitdesign.com/magic/index.html>`__ is needed to
-   run open\_pdks -- version >= 8.3.60\*
-
-   **NOTE:**
-
-      You can avoid the need for the magic prerequisite by using
-      the openlane docker to do the installation step in open\_pdks. This
-      could be done by cloning
-      `openlane <https://github.com/efabless/openlane/tree/master>`__ and
-      following the instructions given there to use the Makefile.
-
-Install the required version of the PDK by running the following
-commands:
-
-.. code:: bash
-
-    export PDK_ROOT=<The place where you want to install the pdk>
-    make pdk
-
-Then, you can learn more about the caravel chip by watching these video:
-
--  Caravel User Project Features -- https://youtu.be/zJhnmilXGPo
--  Aboard Caravel -- How to put your design on Caravel? --
-   https://youtu.be/9QV8SDelURk
--  Things to Clarify About Caravel -- What versions to use with Caravel?
-   -- https://youtu.be/-LZ522mxXMw
-
-   -  You could only use openlane:rc6
-   -  Make sure you have the commit hashes provided here inside the
-      `Makefile <https://github.com/efabless/caravel/blob/master/Makefile>`__
-
-Aboard Caravel
---------------
-
-Your area is the full user\_project\_wrapper, so feel free to add your
-project there or create a differnt macro and harden it seperately then
-insert it into the user\_project\_wrapper. For example, if your design
-is analog or you're using a different tool other than OpenLANE.
-
-If you will use OpenLANE to harden your design, go through the
-instructions in this `README <https://github.com/efabless/caravel/blob/develop/openlane/README.rst>`__.
-
-You must copy your synthesized gate-level-netlist for
-``user_project_wrapper`` to ``verilog/gl/`` and overwrite
-``user_project_wrapper.v``. Otherwise, you can point to it in
-`info.yaml <https://github.com/efabless/caravel/blob/master/info.yaml>`__.
-
-**NOTE:**
-
-    If you're using openlane to harden your design, this should
-    happen automatically.
-
-Then, you will need to put your design aboard the Caravel chip. Make
-sure you have the following:
-
--  `Magic VLSI Layout
-   Tool <http://opencircuitdesign.com/magic/index.html>`__ installed on
-   your machine. We may provide a Dockerized version later.\*
--  You have your user\_project\_wrapper.gds under ``./gds/`` in the
-   Caravel directory.
-
-**NOTE:**
-
-    You can avoid the need for the magic prerequisite by
-    using the openlane docker to run the make step. This
-    `section <#running-make-using-openlane-magic>`__ shows how.
-
-Run the following command:
-
-.. code:: bash
-
-    export PDK_ROOT=<The place where the installed pdk resides. The same PDK_ROOT used in the pdk installation step>
-    make
-
-|Expectation_DRC|
-
-Running Make using OpenLANE Magic
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-To use the magic installed inside Openlane to complete the final GDS
-streaming out step, export the following:
-
-.. code:: bash
-
-    export PDK_ROOT=<The location where the pdk is installed>
-    export OPENLANE_ROOT=<the absolute path to the openlane directory cloned or to be cloned>
-    export IMAGE_NAME=<the openlane image name installed on your machine. Preferably openlane:rc6>
-    export CARAVEL_PATH=$(pwd)
-
-Then, mount the docker:
-
-.. code:: bash
-
-    docker run -it -v $CARAVEL_PATH:$CARAVEL_PATH -v $OPENLANE_ROOT:/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e CARAVEL_PATH=$CARAVEL_PATH -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME
-
-Finally, once inside the docker run the following commands:
-
-.. code:: bash
-
-    cd $CARAVEL_PATH
-    make
-    exit
-
-|Expectation_DRC|
-
-IMPORTANT
-^^^^^^^^^
-
-Please make sure to run ``make compress`` before commiting anything to
-your repository. Avoid having 2 versions of the
-gds/user\_project\_wrapper.gds or gds/caravel.gds one compressed and the
-other not compressed.
-
-Required Directory Structure
-----------------------------
-
--  ./gds/ : includes all the gds files used or produced from the
-   project.
--  ./def/ : includes all the def files used or produced from the
-   project.
--  ./lef/ : includes all the lef files used or produced from the
-   project.
--  ./mag/ : includes all the mag files used or produced from the
-   project.
--  ./maglef/ : includes all the maglef files used or produced from the
-   project.
--  ./spi/lvs/ : includes all the maglef files used or produced from the
-   project.
--  ./verilog/dv/ : includes all the simulation test benches and how to
-   run them.
--  ./verilog/gl/ : includes all the synthesized/elaborated netlists.
--  ./verilog/rtl/ : includes all the Verilog RTLs and source files.
--  ./openlane/\ ``<macro>``/ : includes all configuration files used to
-   run openlane on your project.
--  info.yaml: includes all the info required in `this
-   example <https://github.com/efabless/caravel/blob/master/info.yaml>`__. Please make sure that you are pointing to an
-   elaborated caravel netlist as well as a synthesized
-   gate-level-netlist for the user\_project\_wrapper
-
-Managment SoC
--------------
-
-The managment SoC runs firmware that can be used to:
-
--  Configure User Project I/O pads
--  Observe and control User Project signals (through on-chip logic
-   analyzer probes)
--  Control the User Project power supply
-
-The memory map of the management SoC can be found
-`here <https://github.com/efabless/caravel/blob/master/verilog/rtl/README>`__
-
-User Project Area
------------------
-
-This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10).
-
-See `the Caravel premliminary datasheet` https://caravel-harness.readthedocs.io/en/develop/ for details.
-
-The repository contains a `sample user project <https://github.com/efabless/caravel/blob/master/verilog/rtl/user_proj_example.v>`__ that contains a binary 32-bit up counter.
-
-.. raw:: html
-
-   <p align="center">
-   <img src="/docs/source/_static/counter_32.png" width="50%" height="50%">
-   </p>
-
-The firmware running on the Management Area SoC, configures the I/O pads
-used by the counter and uses the logic probes to observe/control the
-counter. Three firmware examples are provided:
-
-#. Configure the User Project I/O pads as o/p. Observe the counter value
-   in the testbench: `IO\_Ports
-   Test <https://github.com/efabless/caravel/blob/master/verilog/dv/caravel/user_proj_example/io_ports>`__.
-#. Configure the User Project I/O pads as o/p. Use the Chip LA to load
-   the counter and observe the o/p till it reaches 500:
-   `LA\_Test1 <https://github.com/efabless/caravel/blob/master/verilog/dv/caravel/user_proj_example/la_test1>`__.
-#. Configure the User Project I/O pads as o/p. Use the Chip LA to
-   control the clock source and reset signals and observe the counter
-   value for five clock cylcles:
-   `LA\_Test2 <https://github.com/efabless/caravel/blob/master/verilog/dv/caravel/user_proj_example/la_test2>`__.
-
-.. |Expectation_DRC| replace:: This should merge the GDSes using magic and you'll end up with your version of ``./gds/caravel.gds``. You should expect ^40 magic DRC violations with the current "development" state of caravel.
-
-.. |License| image:: https://img.shields.io/github/license/efabless/caravel
-   :alt: GitHub license - Apache 2.0
-   :target: https://github.com/efabless/caravel
-.. |Documentation Status| image:: https://readthedocs.org/projects/caravel-harness/badge/?version=latest
-   :alt: ReadTheDocs Badge - https://caravel-harness.rtfd.io
-   :target: https://caravel-harness.readthedocs.io/en/latest/?badge=latest
-.. |Build Status| image:: https://travis-ci.com/efabless/caravel.svg?branch=master
-   :alt: Travis Badge - https://travis-ci.org/efabless/caravel
-   :target: https://travis-ci.com/efabless/caravel
-
+- Check out verilog/dv/caravel/microwatt/README.md
diff --git a/docs/source/_static/microwatt-caravel.png b/docs/source/_static/microwatt-caravel.png
new file mode 100644
index 0000000..b09ae98
--- /dev/null
+++ b/docs/source/_static/microwatt-caravel.png
Binary files differ
diff --git a/info.yaml b/info.yaml
index 35806bf..9c86098 100644
--- a/info.yaml
+++ b/info.yaml
@@ -1,19 +1,18 @@
 --- 
 project: 
-  description: "A template SoC for Google sponsored Open MPW shuttles for SKY130."
+  description: "Microwatt 64 bit OpenPOWER core"
   foundry: "SkyWater"
-  git_url: "https://github.com/efabless/caravel.git"
-  organization: "Efabless"
-  organization_url: "http://efabless.com"
-  owner: "Tim Edwards"
+  git_url: "https://github.com/antonblanchard/microwatt-caravel.git"
+  organization: "IBM"
+  organization_url: "http://ibm.com"
+  owner: "Anton Blanchard"
   process: "SKY130"
-  project_name: "Caravel"
-  project_id: "00000000"
+  project_name: "Microwatt"
+  project_id: "00000077"
   tags: 
     - "Open MPW"
-    - "Test Harness"
-  category: "Test Harness"
+  category: "processor"
   top_level_netlist: "verilog/gl/caravel.v"
   user_level_netlist: "verilog/gl/user_project_wrapper.v"
   version: "1.00"
-  cover_image: "docs/source/_static/ciic_harness.png"
+  cover_image: "docs/source/_static/microwatt-caravel.png"
diff --git a/openlane/RAM_512x64/config.tcl b/openlane/RAM_512x64/config.tcl
index 32dcadf..8715009 100644
--- a/openlane/RAM_512x64/config.tcl
+++ b/openlane/RAM_512x64/config.tcl
@@ -43,7 +43,7 @@
 #set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
 #set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
 
-set ::env(DIODE_INSERTION_STRATEGY) 5
+set ::env(DIODE_INSERTION_STRATEGY) 3
 
 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
 
diff --git a/openlane/dcache/config.tcl b/openlane/dcache/config.tcl
new file mode 100644
index 0000000..55c554d
--- /dev/null
+++ b/openlane/dcache/config.tcl
@@ -0,0 +1,52 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) dcache
+
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/dcache.v"
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 750 750"
+
+# Settings for macros
+set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(GLB_RT_MAXLAYER) 5
+
+# Tracks are ending up on met5 even with GLB_RT_MAXLAYER set
+set ::env(GLB_RT_OBS) "met5 $::env(DIE_AREA)"
+
+# Handle PDN
+set ::env(VDD_NETS) [list {vccd1} ]
+set ::env(GND_NETS) [list {vssd1} ]
+
+# Tuning
+set ::env(PL_TARGET_DENSITY) 0.56
+set ::env(CELL_PAD) 2
+
+set ::env(SYNTH_STRATEGY) "DELAY 2"
+
+set ::env(GLB_RT_L1_ADJUSTMENT) 0.99
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+
+set ::env(DIODE_INSERTION_STRATEGY) 5
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+if {[catch {exec nproc} result] == 0} {
+	set ::env(ROUTING_CORES) $result
+} else {
+	set ::env(ROUTING_CORES) 4
+}
+
+set ::env(RUN_KLAYOUT) 0
+set ::env(RUN_KLAYOUT_DRC) 0
+set ::env(RUN_KLAYOUT_XOR) 0
diff --git a/openlane/dcache/pin_order.cfg b/openlane/dcache/pin_order.cfg
new file mode 100644
index 0000000..1aed545
--- /dev/null
+++ b/openlane/dcache/pin_order.cfg
@@ -0,0 +1,14 @@
+#N
+wishbone_in.*
+wishbone_out.*
+
+#W
+clk
+rst
+m_in.*
+m_out.*
+
+#S
+stall_out
+d_in.*
+d_out.*
diff --git a/openlane/icache/config.tcl b/openlane/icache/config.tcl
new file mode 100644
index 0000000..d9bb310
--- /dev/null
+++ b/openlane/icache/config.tcl
@@ -0,0 +1,45 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) icache
+
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/icache.v"
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_PERIOD) "15"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 680 680"
+
+# Settings for macros
+set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(GLB_RT_MAXLAYER) 5
+
+# Tracks are ending up on met5 even with GLB_RT_MAXLAYER set
+set ::env(GLB_RT_OBS) "met5 $::env(DIE_AREA)"
+
+# Handle PDN
+set ::env(VDD_NETS) [list {vccd1} ]
+set ::env(GND_NETS) [list {vssd1} ]
+
+# Tuning
+set ::env(PL_TARGET_DENSITY) 0.56
+set ::env(CELL_PAD) 4
+
+set ::env(SYNTH_STRATEGY) "DELAY 2"
+
+set ::env(DIODE_INSERTION_STRATEGY) 5
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+if {[catch {exec nproc} result] == 0} {
+	set ::env(ROUTING_CORES) $result
+} else {
+	set ::env(ROUTING_CORES) 4
+}
+
+set ::env(RUN_KLAYOUT) 0
+set ::env(RUN_KLAYOUT_DRC) 0
+set ::env(RUN_KLAYOUT_XOR) 0
diff --git a/openlane/icache/pin_order.cfg b/openlane/icache/pin_order.cfg
new file mode 100644
index 0000000..7334de4
--- /dev/null
+++ b/openlane/icache/pin_order.cfg
@@ -0,0 +1,16 @@
+#N
+wishbone_in.*
+wishbone_out.*
+
+#E
+clk
+rst
+m_in.*
+
+#S
+i_in.* 
+i_out.*
+flush_in
+inval_in
+stall_in
+stall_out
diff --git a/openlane/multiply_4/config.tcl b/openlane/multiply_4/config.tcl
new file mode 100644
index 0000000..7ea0ffe
--- /dev/null
+++ b/openlane/multiply_4/config.tcl
@@ -0,0 +1,52 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) multiply_4
+
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/multiply_4.v"
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_PERIOD) "30"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 1100 1100"
+
+# Settings for macros
+set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(GLB_RT_MAXLAYER) 5
+
+# Tracks are ending up on met5 even with GLB_RT_MAXLAYER set
+set ::env(GLB_RT_OBS) "met5 $::env(DIE_AREA)"
+
+# Handle PDN
+set ::env(VDD_NETS) [list {vccd1} ]
+set ::env(GND_NETS) [list {vssd1} ]
+
+# Tuning
+set ::env(PL_TARGET_DENSITY) 0.55
+set ::env(CELL_PAD) 4
+
+set ::env(SYNTH_STRATEGY) "DELAY 2"
+
+set ::env(GLB_RT_L1_ADJUSTMENT) 0.99
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+
+set ::env(DIODE_INSERTION_STRATEGY) 5
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+if {[catch {exec nproc} result] == 0} {
+	set ::env(ROUTING_CORES) $result
+} else {
+	set ::env(ROUTING_CORES) 4
+}
+
+set ::env(RUN_KLAYOUT) 0
+set ::env(RUN_KLAYOUT_DRC) 0
+set ::env(RUN_KLAYOUT_XOR) 0
diff --git a/openlane/multiply_4/pin_order.cfg b/openlane/multiply_4/pin_order.cfg
new file mode 100644
index 0000000..1f9b365
--- /dev/null
+++ b/openlane/multiply_4/pin_order.cfg
@@ -0,0 +1,6 @@
+#N
+clk
+m_in.*
+
+#E
+m_out.*
diff --git a/openlane/register_file/config.tcl b/openlane/register_file/config.tcl
new file mode 100644
index 0000000..3798972
--- /dev/null
+++ b/openlane/register_file/config.tcl
@@ -0,0 +1,52 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) register_file
+
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/register_file.v"
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_PERIOD) "20"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 1100 1100"
+
+# Settings for macros
+set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(GLB_RT_MAXLAYER) 5
+
+# Tracks are ending up on met5 even with GLB_RT_MAXLAYER set
+set ::env(GLB_RT_OBS) "met5 $::env(DIE_AREA)"
+
+# Handle PDN
+set ::env(VDD_NETS) [list {vccd1} ]
+set ::env(GND_NETS) [list {vssd1} ]
+
+# Tuning
+set ::env(PL_TARGET_DENSITY) 0.55
+set ::env(CELL_PAD) 4
+
+set ::env(SYNTH_STRATEGY) "DELAY 2"
+
+set ::env(GLB_RT_L1_ADJUSTMENT) 0.99
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+
+set ::env(DIODE_INSERTION_STRATEGY) 5
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+if {[catch {exec nproc} result] == 0} {
+	set ::env(ROUTING_CORES) $result
+} else {
+	set ::env(ROUTING_CORES) 4
+}
+
+set ::env(RUN_KLAYOUT) 0
+set ::env(RUN_KLAYOUT_DRC) 0
+set ::env(RUN_KLAYOUT_XOR) 0
diff --git a/openlane/register_file/pin_order.cfg b/openlane/register_file/pin_order.cfg
new file mode 100644
index 0000000..1fa4e07
--- /dev/null
+++ b/openlane/register_file/pin_order.cfg
@@ -0,0 +1,7 @@
+#N
+clk
+d_in.*
+d_out.*
+
+#W
+w_in.*
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index e60639f..4d27b15 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -25,13 +25,15 @@
 ## Source Verilog Files
 set ::env(VERILOG_FILES) "\
 	$script_dir/../../verilog/rtl/defines.v \
+	$script_dir/../../verilog/rtl/microwatt.v \
 	$script_dir/../../verilog/rtl/user_project_wrapper.v"
 
 ## Clock configurations
-set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
+# Should we switch to independent clock?
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
 
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PERIOD) "35"
 
 ## Internal Macros
 ### Macro Placement
@@ -39,25 +41,63 @@
 
 ### Black-box verilog and views
 set ::env(VERILOG_FILES_BLACKBOX) "\
-	$script_dir/../../verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_proj_example.v"
+        $script_dir/../../verilog/rtl/RAM_512x64.v \
+        $script_dir/../../verilog/rtl/register_file.v \
+        $script_dir/../../verilog/rtl/multiply_4.v \
+        $script_dir/../../verilog/rtl/icache.v \
+        $script_dir/../../verilog/rtl/dcache.v"
 
 set ::env(EXTRA_LEFS) "\
-	$script_dir/../../lef/user_proj_example.lef"
+        $script_dir/../../lef/RAM_512x64.lef \
+        $script_dir/../../lef/register_file.lef \
+        $script_dir/../../lef/multiply_4.lef \
+        $script_dir/../../lef/icache.lef \
+        $script_dir/../../lef/dcache.lef"
 
 set ::env(EXTRA_GDS_FILES) "\
-	$script_dir/../../gds/user_proj_example.gds"
+        $script_dir/../../gds/RAM_512x64.gds \
+        $script_dir/../../gds/register_file.gds \
+        $script_dir/../../gds/multiply_4.gds \
+        $script_dir/../../gds/icache.gds \
+        $script_dir/../../gds/dcache.gds"
 
+# Tuning
+set ::env(PL_TARGET_DENSITY) 0.20
+set ::env(CELL_PAD) 8
 
-# The following is because there are no std cells in the example wrapper project.
-set ::env(SYNTH_TOP_LEVEL) 1
-set ::env(PL_RANDOM_GLB_PLACEMENT) 1
 set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
-set ::env(DIODE_INSERTION_STRATEGY) 0
-set ::env(FILL_INSERTION) 0
-set ::env(TAP_DECAP_INSERTION) 0
-set ::env(CLOCK_TREE_SYNTH) 0
 
+#set ::env(SYNTH_STRATEGY) "DELAY 2"
+
+#set ::env(FP_TAPCELL_DIST) 13
+
+set ::env(GLB_RT_OBS) "met5 60.000 2720.000 2860.000 3420.000, met4 60.000 2720.000 2860.000 3420.000, met5 60.000 1740.000 740.000 2420.000, met4 60.000 1740.000 740.000 2420.000, met5 2110.000 1720.000 2860.000 2470.000, met4 2110.000 1720.000 2860.000 2470.000, met5 60.000 100.000 1160.000 1200.000, met4 60.000 100.000 1160.000 1200.000, met5 1760.000 100.000 2860.000 1200.000, met4 1760.000 100.000 2860.000 1200.000"
+
+set ::env(FP_HORIZONTAL_HALO) 70
+set ::env(FP_VERTICAL_HALO) 47.5
+
+set ::env(GLB_RT_L1_ADJUSTMENT) 0.99
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+
+set ::env(DIODE_INSERTION_STRATEGY) 5
+
+set ::env(GLB_RT_ALLOW_CONGESTION) 1
+
+set ::env(PL_DIAMOND_SEARCH_HEIGHT) 400
+
+if {[catch {exec nproc} result] == 0} {
+	set ::env(ROUTING_CORES) $result
+} else {
+	set ::env(ROUTING_CORES) 4
+}
+
+set ::env(RUN_KLAYOUT) 0
+set ::env(RUN_KLAYOUT_DRC) 0
+set ::env(RUN_KLAYOUT_XOR) 0
 
 # DON'T TOUCH THE FOLLOWING SECTIONS
 
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index cab6c9d..6a71318 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1,5 @@
-mprj 1175 1700 N
+microwatt_0.soc0.bram.bram0.ram_0.memory_0         60.000 2720.000 N
+microwatt_0.soc0.processor.icache_0                60.000 1740.000 N
+microwatt_0.soc0.processor.dcache_0              2110.000 1720.000 N
+microwatt_0.soc0.processor.execute1_0.multiply_0   60.000  100.000 N
+microwatt_0.soc0.processor.register_file_0       1760.000  100.000 N
diff --git a/openlane/user_project_wrapper/scripts/layout.py b/openlane/user_project_wrapper/scripts/layout.py
new file mode 100755
index 0000000..61661b7
--- /dev/null
+++ b/openlane/user_project_wrapper/scripts/layout.py
@@ -0,0 +1,73 @@
+#!/usr/bin/python3
+
+import re
+import os
+
+X=0
+Y=1
+
+# Wrapper size
+die_size   = (2920, 3520)
+
+r = re.compile('SIZE ([0-9\.]+) BY ([0-9\.]+) ;')
+
+def get_macro_size(name):
+    lef_file = os.path.dirname(os.path.abspath(__file__)) + '/../../../lef/' + name + '.lef'
+    with open(lef_file) as f:
+        for line in f:
+            m = r.search(line)
+            if m:
+                lx = float(m.group(1))
+                ly = float(m.group(2))
+                return (lx, ly)
+
+
+# Macro sizes
+#ram        = (2800,  550)
+#icache     = ( 660,  660)
+#dcache     = ( 720,  720)
+#multiply_4 = ( 800,  800)
+#regfile    = (1000, 1000)
+ram = get_macro_size('RAM_512x64')
+icache = get_macro_size('icache')
+dcache = get_macro_size('dcache')
+multiply_4 = get_macro_size('multiply_4')
+regfile = get_macro_size('register_file')
+
+horizontal_margin = 60
+vertical_margin   = 100
+
+# Macro layout
+
+# RAM at top
+ram_l    =     (horizontal_margin,                        die_size[Y]-ram[Y]-vertical_margin)
+
+# Caches in the middle
+icache_l     = (horizontal_margin,                        die_size[Y]-icache[Y]-1100)
+dcache_l     = (die_size[X]-dcache[X]-horizontal_margin,  die_size[Y]-dcache[Y]-1050)
+
+# Multiply and regfile at bottom
+multiply_4_l = (horizontal_margin,                        vertical_margin)
+regfile_l    = (die_size[X]-regfile[X]-horizontal_margin, vertical_margin)
+
+print('microwatt_0.soc0.bram.bram0.ram_0.memory_0       %8.3f %8.3f N' % ram_l)
+print('microwatt_0.soc0.processor.icache_0              %8.3f %8.3f N' % icache_l)
+print('microwatt_0.soc0.processor.dcache_0              %8.3f %8.3f N' % dcache_l)
+print('microwatt_0.soc0.processor.execute1_0.multiply_0 %8.3f %8.3f N' % multiply_4_l)
+print('microwatt_0.soc0.processor.register_file_0       %8.3f %8.3f N' % regfile_l)
+
+def print_obs(sz, base, last=False):
+    sep = ''
+    if not last:
+        sep = ', '
+    print('met5 %.3f %.3f %.3f %.3f, ' % (base[X], base[Y], base[X]+sz[X], base[Y]+sz[Y]), end='')
+    print('met4 %.3f %.3f %.3f %.3f%s' % (base[X], base[Y], base[X]+sz[X], base[Y]+sz[Y], sep), end='')
+
+print()
+print('set ::env(GLB_RT_OBS) "', end='')
+print_obs(ram, ram_l)
+print_obs(icache, icache_l)
+print_obs(dcache, dcache_l)
+print_obs(multiply_4, multiply_4_l)
+print_obs(regfile, regfile_l, last=True)
+print('"')
diff --git a/scripts/microwatt-build-caravel.sh b/scripts/microwatt-build-caravel.sh
new file mode 100755
index 0000000..d1c5639
--- /dev/null
+++ b/scripts/microwatt-build-caravel.sh
@@ -0,0 +1,9 @@
+#!/bin/bash -e
+
+cd $CARAVEL_PATH
+make uncompress
+cd openlane
+
+make user_project_wrapper
+
+docker run --rm -v $CARAVEL_PATH:$CARAVEL_PATH -v $OPENLANE_ROOT:/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e CARAVEL_PATH=$CARAVEL_PATH -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME sh -c "cd $CARAVEL_PATH && make"
diff --git a/scripts/microwatt-build-macros.sh b/scripts/microwatt-build-macros.sh
new file mode 100755
index 0000000..46dc226
--- /dev/null
+++ b/scripts/microwatt-build-macros.sh
@@ -0,0 +1,12 @@
+#!/bin/bash -e
+
+cd $CARAVEL_PATH
+make uncompress
+cd openlane
+
+for macro in icache dcache register_file multiply_4 RAM_512x64
+do
+	make $macro < /dev/null &
+done
+
+wait
diff --git a/scripts/microwatt-commit-caravel.py b/scripts/microwatt-commit-caravel.py
new file mode 100755
index 0000000..840e377
--- /dev/null
+++ b/scripts/microwatt-commit-caravel.py
@@ -0,0 +1,95 @@
+#!/usr/bin/env python3
+
+import os
+import sys
+import subprocess
+
+compress_size = 100*1000*1000
+gzip_compress_size_max = 200*1000*1000
+gzip_compress_cmd = [ 'gzip', '-9', '-f' ]
+xz_compress_cmd = [ 'xz', '-9', '-f' ]
+gzip_uncompress_cmd = [ 'gzip', '-d', '-f' ]
+xz_uncompress_cmd = [ 'xz', '-d', '-f' ]
+
+files = [ "def/user_project_wrapper.def",
+          "gds/user_project_wrapper.gds",
+          "lef/user_project_wrapper.lef",
+          "mag/user_project_wrapper.mag",
+          "maglef/user_project_wrapper.mag",
+          "spi/lvs/user_project_wrapper.spice",
+          "verilog/gl/user_project_wrapper.v",
+          "gds/caravel.gds"
+]
+
+# Check all the files exist
+for fname in files:
+    try:
+        s = os.stat(fname)
+    except:
+        print("%s doesn't exist" % fname)
+        sys.exit(1)
+
+
+add_files = list()
+rm_files = list()
+
+for fname in files:
+    sz = os.stat(fname).st_size
+    if sz > gzip_compress_size_max:
+        cmd = xz_compress_cmd.copy()
+        cmd.append(fname)
+        print(cmd)
+        subprocess.check_call(cmd)
+
+        rm_files.append(fname)
+        rm_files.append(fname + '.gz')
+        add_files.append(fname + '.xz')
+    elif sz > compress_size or 'gds' in fname:
+        cmd = gzip_compress_cmd.copy()
+        cmd.append(fname)
+        print(cmd)
+        subprocess.check_call(cmd)
+
+        rm_files.append(fname)
+        rm_files.append(fname + '.xz')
+        add_files.append(fname + '.gz')
+    else:
+        rm_files.append(fname + '.gz')
+        rm_files.append(fname + '.xz')
+        add_files.append(fname)
+
+
+checked_rm_files = list()
+for f in rm_files:
+    cmd = [ 'git', 'rm', f ]
+    try:
+        print(cmd)
+        subprocess.check_call(cmd)
+        checked_rm_files.append(f)
+    except:
+        pass
+
+
+cmd = [ 'git', 'add' ]
+cmd.extend(add_files)
+print(cmd)
+subprocess.check_call(cmd)
+
+cmd = [ 'git', 'commit', '-m', 'Tape out' ]
+cmd.extend(checked_rm_files)
+cmd.extend(add_files)
+print(cmd)
+subprocess.check_call(cmd)
+
+# Uncompress files now they've been checked in
+for fname in add_files:
+    if fname.endswith('.gz'):
+        cmd = gzip_uncompress_cmd.copy()
+        cmd.append(fname)
+        print(cmd)
+        subprocess.check_call(cmd)
+    elif fname.endswith('.xz'):
+        cmd = xz_uncompress_cmd.copy()
+        cmd.append(fname)
+        print(cmd)
+        subprocess.check_call(cmd)
diff --git a/scripts/microwatt-commit-macros.py b/scripts/microwatt-commit-macros.py
new file mode 100755
index 0000000..8fa3bae
--- /dev/null
+++ b/scripts/microwatt-commit-macros.py
@@ -0,0 +1,87 @@
+#!/usr/bin/env python3
+
+import os
+import sys
+import subprocess
+
+compress_size = 100*1000*1000
+gzip_compress_cmd = [ 'gzip', '-9', '-f' ]
+gzip_uncompress_cmd = [ 'gzip', '-d', '-f' ]
+
+macros = [ 'RAM_512x64',
+           'dcache',
+           'icache',
+           'multiply_4',
+           'register_file'
+]
+
+# Directories and extensions
+dirs = [ ('def', 'def'),
+         ('gds', 'gds'),
+         ('lef', 'lef'),
+         ('mag', 'mag'),
+         ('maglef', 'mag'),
+         ('spi/lvs', 'spice'),
+         ('verilog/gl', 'v')
+]
+
+# Check all the files exist
+for (dir, ext) in dirs:
+    for macro in macros:
+        fname = '%s/%s.%s' % (dir, macro, ext)
+        try:
+            s = os.stat(fname)
+        except:
+            print("%s doesn't exist" % fname)
+            sys.exit(1)
+
+
+add_files = list()
+rm_files = list()
+
+for (dir, ext) in dirs:
+    for macro in macros:
+        fname = '%s/%s.%s' % (dir, macro, ext)
+        sz = os.stat(fname).st_size
+        if sz > compress_size or 'gds' in dir:
+            cmd = gzip_compress_cmd.copy()
+            cmd.append(fname)
+            print(cmd)
+            subprocess.check_call(cmd)
+
+            rm_files.append(fname)
+            add_files.append(fname + '.gz')
+        else:
+            rm_files.append(fname + '.gz')
+            add_files.append(fname)
+
+
+checked_rm_files = list()
+for f in rm_files:
+    cmd = [ 'git', 'rm', f ]
+    try:
+        print(cmd)
+        subprocess.check_call(cmd)
+        checked_rm_files.append(f)
+    except:
+        pass
+
+
+cmd = [ 'git', 'add' ]
+cmd.extend(add_files)
+print(cmd)
+subprocess.check_call(cmd)
+
+cmd = [ 'git', 'commit', '-m', 'Build macros' ]
+cmd.extend(checked_rm_files)
+cmd.extend(add_files)
+print(cmd)
+subprocess.check_call(cmd)
+
+# Uncompress files now they've been checked in
+for fname in add_files:
+    if fname.endswith('.gz'):
+        cmd = gzip_uncompress_cmd.copy()
+        cmd.append(fname)
+        print(cmd)
+        subprocess.check_call(cmd)
diff --git a/scripts/microwatt-tape-out.sh b/scripts/microwatt-tape-out.sh
new file mode 100755
index 0000000..82efa30
--- /dev/null
+++ b/scripts/microwatt-tape-out.sh
@@ -0,0 +1,13 @@
+#!/bin/bash -e
+
+export OPENLANE_IMAGE_NAME=localhost/openlane:rc7
+export IMAGE_NAME=$OPENLANE_IMAGE_NAME
+export PDK_ROOT=/shared/anton/pdk.rc7
+export OPENLANE_ROOT=/shared/anton/openlane.rc7
+
+export CARAVEL_PATH="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"/../
+
+$CARAVEL_PATH/scripts/microwatt-build-macros.sh
+$CARAVEL_PATH/scripts/microwatt-commit-macros.py
+$CARAVEL_PATH/scripts/microwatt-build-caravel.sh
+$CARAVEL_PATH/scripts/microwatt-commit-caravel.py
diff --git a/verilog/dv/caravel/microwatt/README.md b/verilog/dv/caravel/microwatt/README.md
new file mode 100644
index 0000000..7661dd8
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/README.md
@@ -0,0 +1,46 @@
+# Microwatt Tests
+
+To run these you need icarus verilog, a riscv toolchain and a ppc64le
+toolchain. On Fedora these are available as packages:
+
+```
+sudo dnf install iverilog gcc-riscv64-linux-gnu gcc-powerpc64le-linux-gnu
+```
+
+And on Ubuntu:
+
+```
+sudo apt install iverilog gcc-riscv64-linux-gnu gcc-powerpc64le-linux-gnu
+```
+
+The test cases need a path to the PDK, eg:
+
+```
+make PDK_PATH=/home/anton/pdk/sky130A
+```
+
+## minimal
+This is probably where you should start. This is a minimal test that verifies
+that Microwatt is running. The SPI flash controller is lightly tested because
+Microwatt uses it to fetch instructions for the test case. The logic analyzer
+is also lightly tested because Microwatt uses that to signal back to the
+management engine that it is alive.
+
+## uart
+This tests the management engine handing over the TX and RX I/O pins to
+Microwatt, and Microwatt receiving a character and echoing it back.
+
+## logic_analyzer
+Microwatt has 32 LA inputs and 32 LA outputs hooked up.  This tests that
+functionality by ping ponging an LFSR sequence between the management engine
+and Microwatt. Each value in the sequence is checked before emitting the next
+one.
+
+## spi_flash
+Before starting flash is initialized with a hash of the offset. The test case
+then does reads at various offsets and checks if the values returned are
+correct.
+
+## memory_test
+A simple memory tester. Writes hashes of the offset of memory into memory,
+then reads them back.
diff --git a/verilog/dv/caravel/microwatt/external_bus_minimal/Makefile b/verilog/dv/caravel/microwatt/external_bus_minimal/Makefile
new file mode 100644
index 0000000..ccbe467
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/external_bus_minimal/Makefile
@@ -0,0 +1,59 @@
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+PDK_PATH?=/ef/tech/SW/sky130A
+
+RISCV_CROSS_COMPILE?=riscv64-linux-gnu-
+RISCV_CFLAGS=-static -Os -g -Wall -march=rv32imc -mabi=ilp32 -ffreestanding -nostdlib
+
+POWERPC_CROSS_COMPILE?=powerpc64le-linux-gnu-
+POWERPC_CFLAGS=-static -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -ffreestanding -fdata-sections -ffunction-sections -nostdlib -I../include
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = external_bus_minimal
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v mgmt_engine.hex microwatt.hex
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+else
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+# Management engine code
+
+mgmt_engine.elf: mgmt_engine.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	$(RISCV_CROSS_COMPILE)gcc $(RISCV_CFLAGS) -Wl,-T,$(FIRMWARE_PATH)/sections.lds -o $@ $(FIRMWARE_PATH)/start.s $<
+
+mgmt_engine.hex: mgmt_engine.elf
+	$(RISCV_CROSS_COMPILE)objcopy -O verilog $< $@
+	# to fix flash base address
+	sed -i 's/@1000/@0000/g' $@
+
+# Microwatt code
+microwatt.elf: microwatt.c ../lib/console.c ../lib/head.S ../microwatt.lds
+	$(POWERPC_CROSS_COMPILE)gcc $(POWERPC_CFLAGS) -Wl,-T,../microwatt.lds -o $@ microwatt.c ../lib/console.c ../lib/head.S
+
+microwatt.hex: microwatt.elf
+	$(POWERPC_CROSS_COMPILE)objcopy -O verilog $< $@
+	# to fix flash base address
+	sed -i 's/@F000/@0000/g' $@
+
+clean:
+	rm -f *.vvp *.vcd *.elf *.bin *.o *.vvp *.vcd *.log *.hex
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/microwatt/external_bus_minimal/external_bus_minimal_tb.v b/verilog/dv/caravel/microwatt/external_bus_minimal/external_bus_minimal_tb.v
new file mode 100644
index 0000000..b2d2e27
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/external_bus_minimal/external_bus_minimal_tb.v
@@ -0,0 +1,333 @@
+`default_nettype none
+/*
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *  Copyright (C) 2020  Anton Blanchard <anton@linux.ibm.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+
+module external_bus_tb (
+	input clk,
+
+	input [7:0] ext_bus_in,
+	input ext_bus_pty_in,
+
+	output [7:0] ext_bus_out,
+	output ext_bus_pty_out
+);
+	localparam [7:0] CMD_READ = 8'h2;
+	localparam [7:0] CMD_WRITE = 8'h3;
+	localparam [7:0] CMD_READ_ACK = 8'h82;
+	localparam [7:0] CMD_WRITE_ACK = 8'h83;
+
+	localparam [3:0] ADDR_BYTES = 4;
+	localparam [3:0] DATA_BYTES = 8;
+
+	localparam [3:0] READ_DELAY_CYCLES = 8;
+
+	localparam [3:0] RECV_STATE_IDLE = 0;
+	localparam [3:0] RECV_STATE_WRITE_ADDR = 1;
+	localparam [3:0] RECV_STATE_WRITE_DATA = 2;
+	localparam [3:0] RECV_STATE_WRITE_SEL = 3;
+	localparam [3:0] RECV_STATE_READ_ADDR = 4;
+	localparam [3:0] RECV_STATE_READ_DELAY = 5;
+	reg [3:0] recv_state;
+
+	reg [31:0] recv_addr;
+	reg [63:0] recv_data;
+	reg [7:0] recv_sel;
+	reg [3:0] recv_count;
+	reg [127:0] tx_data;
+
+	reg [7:0] bus_out;
+
+	assign ext_bus_out = bus_out;
+	assign ext_bus_pty_out = ~^bus_out;
+
+	initial begin
+		bus_out <= 8'h0;
+		recv_state <= 0;
+		recv_addr <= 0;
+		recv_sel <= 0;
+		recv_data <= 0;
+		recv_count <= 0;
+		tx_data <= 0;
+	end
+
+	// receive on positive edge
+	always @(posedge clk) begin
+		if (ext_bus_pty_in != ~^ext_bus_in) begin
+			$display("Bad parity on bus");
+			$fatal;
+		end
+
+		case (recv_state)
+			RECV_STATE_IDLE: begin
+				//$display("Idle state");
+
+				if (ext_bus_in == CMD_WRITE) begin
+					$display("Got write command");
+					recv_state <= RECV_STATE_WRITE_ADDR;
+					recv_addr <= 0;
+					recv_sel <= 0;
+					recv_data <= 0;
+					recv_count <= ADDR_BYTES;
+				end
+				if (ext_bus_in == CMD_READ) begin
+					$display("Got read command");
+					recv_state <= RECV_STATE_READ_ADDR;
+					recv_addr <= 0;
+					recv_sel <= 0;
+					recv_data <= 0;
+					recv_count <= ADDR_BYTES;
+				end
+			end
+
+			RECV_STATE_WRITE_ADDR: begin
+				$display("RECV_STATE_WRITE_ADDR state");
+
+				recv_addr <= { ext_bus_in, recv_addr[23:8] };
+				$display("A: %02x", ext_bus_in);
+				if (recv_count == 1) begin
+					recv_state <= RECV_STATE_WRITE_SEL;
+				end else begin
+					recv_count <= recv_count - 1;
+				end
+			end
+
+			RECV_STATE_WRITE_SEL: begin
+				$display("RECV_STATE_WRITE_SEL state");
+
+				$display("S: %02x", ext_bus_in);
+				recv_sel <= ext_bus_in;
+				recv_state <= RECV_STATE_WRITE_DATA;
+				recv_count <= DATA_BYTES;
+			end
+
+			RECV_STATE_WRITE_DATA: begin
+				$display("RECV_STATE_WRITE_DATA state");
+
+				recv_data <= { ext_bus_in, recv_addr[23:8] };
+				$display("D: %02x", ext_bus_in);
+				if (recv_count == 1) begin
+					tx_data <= CMD_WRITE_ACK;
+					recv_state <= RECV_STATE_IDLE;
+				end else begin
+					recv_count <= recv_count - 1;
+				end
+			end
+
+			RECV_STATE_READ_ADDR: begin
+				$display("RECV_STATE_READ_ADDR state");
+
+				recv_addr <= { ext_bus_in, recv_addr[23:8] };
+				$display("A: %02x", ext_bus_in);
+				if (recv_count == 1) begin
+					recv_count <= READ_DELAY_CYCLES;
+					recv_state <= RECV_STATE_READ_DELAY;
+				end else begin
+					recv_count <= recv_count - 1;
+				end
+			end
+
+			RECV_STATE_READ_DELAY: begin
+				$display("RECV_STATE_READ_DELAY state");
+				if (recv_count == 1) begin
+					tx_data <= { 64'h0102030405060708, CMD_READ_ACK};
+					recv_state <= RECV_STATE_IDLE;
+				end else begin
+					recv_count <= recv_count - 1;
+				end
+			end
+
+			default: begin
+				$display("BAD state");
+				$fatal;
+			end
+		endcase
+	end
+
+	// transmit on negative edge
+	always @(negedge clk) begin
+		if (|tx_data) begin
+			$display("T: %02x", tx_data[7:0]);
+			bus_out <= tx_data[7:0];
+			tx_data <= tx_data[127:8];
+		end else begin
+			bus_out <= 8'h0;
+		end
+	end
+endmodule
+
+module external_bus_minimal_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+	reg power1, power2;
+
+	wire gpio;
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire [37:0] mprj_io;
+	wire [3:0] checkbits;
+	wire user_flash_csb;
+	wire user_flash_clk;
+	inout user_flash_io0;
+	inout user_flash_io1;
+	wire ext_bus_clk;
+	wire [7:0] ext_bus_in;
+	wire ext_bus_pty_in;
+	wire [7:0] ext_bus_out;
+	wire ext_bus_pty_out;
+
+	assign user_flash_csb = mprj_io[8];
+	assign user_flash_clk = mprj_io[9];
+	assign user_flash_io0 = mprj_io[10];
+	assign mprj_io[11] = user_flash_io1;
+
+	assign checkbits = mprj_io[17:16];
+
+	assign ext_bus_clk = mprj_io[18];
+	assign ext_bus_out[7:0] = mprj_io[26:19];
+	assign ext_bus_pty_out = mprj_io[27];
+	assign mprj_io[35:28] = ext_bus_in[7:0];
+	assign mprj_io[36] = ext_bus_pty_in;
+
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	// 50 MHz clock
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("external_bus_minimal.vcd");
+		$dumpvars(0, external_bus_minimal_tb);
+
+		$display("Microwatt external bus minimal test");
+
+		repeat (1000000) begin
+			@(posedge clock);
+		end
+
+		$display("Timeout, test failed");
+		$fatal;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#1000;
+		RSTB <= 1'b1;		// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+	initial begin
+		wait(checkbits == 2'h1);
+		$display("Management engine started");
+
+		wait(checkbits == 2'h2);
+		$display("Microwatt alive!");
+
+		// Wait for Microwatt to respond with success
+		wait(checkbits == 2'h3);
+		$display("Success!");
+		$finish;
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("mgmt_engine.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+	spiflash #(
+		.FILENAME("microwatt.hex")
+	) spiflash_microwatt (
+		.csb(user_flash_csb),
+		.clk(user_flash_clk),
+		.io0(user_flash_io0),
+		.io1(user_flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+	external_bus_tb external_bus_tb (
+		.clk(ext_bus_clk),
+		.ext_bus_in(ext_bus_out),
+		.ext_bus_pty_in(ext_bus_pty_out),
+		.ext_bus_out(ext_bus_in),
+		.ext_bus_pty_out(ext_bus_pty_in)
+	);
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/microwatt/external_bus_minimal/mgmt_engine.c b/verilog/dv/caravel/microwatt/external_bus_minimal/mgmt_engine.c
new file mode 100644
index 0000000..97203bc
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/external_bus_minimal/mgmt_engine.c
@@ -0,0 +1,30 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../include/microwatt_util.h"
+#include "../include/mgmt_engine_util.h"
+
+// --------------------------------------------------------
+
+void main(void)
+{
+	mgmt_engine_io_setup(false, true);
+
+	// Take microwatt out of reset
+	reg_la2_data &= ~0x00000002;
+
+	while ((reg_la0_data != LA_MICROWATT_START) && (reg_la0_data != LA_MICROWATT_SUCCESS))
+		/* Do Nothing */ ;
+
+	// Signal to TB that microwatt is alive
+	reg_mprj_datal = GPIO1_MICROWATT_START;
+
+	while (reg_la0_data != LA_MICROWATT_SUCCESS)
+		/* Do Nothing */ ;
+
+	// Signal success to the TB
+	reg_mprj_datal = GPIO1_SUCCESS;
+
+	while (1)
+		/* Do Nothing */;
+}
diff --git a/verilog/dv/caravel/microwatt/external_bus_minimal/microwatt.c b/verilog/dv/caravel/microwatt/external_bus_minimal/microwatt.c
new file mode 100644
index 0000000..ca28e1a
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/external_bus_minimal/microwatt.c
@@ -0,0 +1,25 @@
+#include <stdint.h>
+
+#include "microwatt_util.h"
+
+#define EXT_BUS_OFFSET 0x40000000
+
+int main(void)
+{
+	uint64_t *p = (uint64_t *)EXT_BUS_OFFSET;
+
+	microwatt_alive();
+
+	__asm__ __volatile__("");
+	*p = 0x5A5A5A5A5A5A5A5A;
+	__asm__ __volatile__("");
+	*p = 0x0f0f0f0f0f0f0f0f;
+	__asm__ __volatile__("");
+	*p = 0xACEACEACEACEACEA;
+	__asm__ __volatile__("");
+
+	microwatt_success();
+
+	while (1)
+		/* Do Nothing */ ;
+}
diff --git a/verilog/dv/caravel/microwatt/include/console.h b/verilog/dv/caravel/microwatt/include/console.h
new file mode 100644
index 0000000..e49d569
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/include/console.h
@@ -0,0 +1,12 @@
+#include <stddef.h>
+#include <stdbool.h>
+
+void console_init(void);
+void console_set_irq_en(bool rx_irq, bool tx_irq);
+int getchar(void);
+int putchar(int c);
+int puts(const char *str);
+
+#ifndef __USE_LIBC
+size_t strlen(const char *s);
+#endif
diff --git a/verilog/dv/caravel/microwatt/include/io.h b/verilog/dv/caravel/microwatt/include/io.h
new file mode 100644
index 0000000..d148046
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/include/io.h
@@ -0,0 +1,55 @@
+#ifndef __IO_H
+#define __IO_H
+
+#include <stdint.h>
+
+static inline uint8_t readb(unsigned long addr)
+{
+	uint8_t val;
+	__asm__ volatile("sync; lbzcix %0,0,%1" : "=r" (val) : "r" (addr) : "memory");
+	return val;
+}
+
+static inline uint16_t readw(unsigned long addr)
+{
+	uint16_t val;
+	__asm__ volatile("sync; lhzcix %0,0,%1" : "=r" (val) : "r" (addr) : "memory");
+	return val;
+}
+
+static inline uint32_t readl(unsigned long addr)
+{
+	uint32_t val;
+	__asm__ volatile("sync; lwzcix %0,0,%1" : "=r" (val) : "r" (addr) : "memory");
+	return val;
+}
+
+static inline uint64_t readq(unsigned long addr)
+{
+	uint64_t val;
+	__asm__ volatile("sync; ldcix %0,0,%1" : "=r" (val) : "r" (addr) : "memory");
+	return val;
+}
+
+static inline void writeb(uint8_t val, unsigned long addr)
+{
+	__asm__ volatile("sync; stbcix %0,0,%1" : : "r" (val), "r" (addr) : "memory");
+}
+
+static inline void writew(uint16_t val, unsigned long addr)
+{
+	__asm__ volatile("sync; sthcix %0,0,%1" : : "r" (val), "r" (addr) : "memory");
+}
+
+static inline void writel(uint32_t val, unsigned long addr)
+{
+	__asm__ volatile("sync; stwcix %0,0,%1" : : "r" (val), "r" (addr) : "memory");
+}
+
+static inline void writeq(uint64_t val, unsigned long addr)
+{
+	__asm__ volatile("sync; stdcix %0,0,%1" : : "r" (val), "r" (addr) : "memory");
+}
+
+#endif /* __IO_H */
+
diff --git a/verilog/dv/caravel/microwatt/include/mgmt_engine_util.h b/verilog/dv/caravel/microwatt/include/mgmt_engine_util.h
new file mode 100644
index 0000000..25730a2
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/include/mgmt_engine_util.h
@@ -0,0 +1,84 @@
+#include <stdbool.h>
+
+#include "../../defs.h"
+
+static void inline mgmt_engine_io_setup(bool jtag, bool external_bus)
+{
+	// Set LA[65] as output to act as a reset pin for microwatt and
+	// LA[66] as output to specify reset location (RAM or FLASH)
+	reg_la2_ena = 0xFFFFFFF9;
+
+	// Put microwatt into reset and tell it to fetch from flash
+	reg_la2_data = 0x00000002 | 0x00000004;
+
+	// Set up the housekeeping SPI to be connected internally so
+	// that external pin changes don't affect it.
+	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+					// connect to housekeeping SPI
+
+	// Communicate status with test case over GPIO 7 and 37
+	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+	// Signal to the tb that we are alive
+	reg_mprj_datal = GPIO1_MGMT_ENGINE_START;
+
+	// Configure UART
+	reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+	reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
+
+	// 7 unused
+
+	// Configure SPI
+	reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;		// CSB
+	reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;		// SCK
+	reg_mprj_io_10 = GPIO_MODE_USER_STD_BIDIRECTIONAL;	// IO0/MOSI
+	reg_mprj_io_11 = GPIO_MODE_USER_STD_BIDIRECTIONAL;	// IO1/MISO
+	reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL;	// IO2
+	reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL;	// IO3
+
+	// Configure JTAG
+	if (jtag) {
+		// Overlaps our testbench status bits
+		reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;		// TDO
+		reg_mprj_io_15 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;	// TMS
+		reg_mprj_io_16 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;	// TCK
+		reg_mprj_io_17 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;	// TDI
+	}
+
+	// Configure external bus
+	if (external_bus) {
+		reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+		reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+		reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+		reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+		reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+		reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+		reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+		reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
+		reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+		reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+	}
+	reg_mprj_io_28 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+	reg_mprj_io_29 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+	reg_mprj_io_30 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+	reg_mprj_io_31 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+	reg_mprj_io_32 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+	reg_mprj_io_33 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+	reg_mprj_io_34 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+	reg_mprj_io_35 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+	reg_mprj_io_36 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+
+	// 37 unused
+
+	// Now, apply the configuration
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1)
+		/* Do Nothing */;
+
+	// Configure LA bits 0-31 as inputs from Microwatt
+	reg_la0_ena = 0xFFFFFFFF;	// [31:0]
+
+	// Configure LA bits 63-32 as outputs from Microwatt
+	reg_la1_ena = 0x00000000;	// [63:32]
+}
diff --git a/verilog/dv/caravel/microwatt/include/microwatt_soc.h b/verilog/dv/caravel/microwatt/include/microwatt_soc.h
new file mode 100644
index 0000000..a224d74
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/include/microwatt_soc.h
@@ -0,0 +1,155 @@
+#ifndef __MICROWATT_SOC_H
+#define __MICROWATT_SOC_H
+
+/*
+ * Microwatt SoC memory map
+ */
+
+#define MEMORY_BASE     0x00000000  /* "Main" memory alias, either BRAM or DRAM */
+#define DRAM_BASE       0x40000000  /* DRAM if present */
+#define BRAM_BASE       0x80000000  /* Internal BRAM */
+
+#define SYSCON_BASE	0xc0000000  /* System control regs */
+#define UART_BASE	0xc0002000  /* UART */
+#define XICS_ICP_BASE   0xc0004000  /* Interrupt controller */
+#define XICS_ICS_BASE   0xc0005000  /* Interrupt controller */
+#define SPI_FCTRL_BASE  0xc0006000  /* SPI flash controller registers */
+#define DRAM_CTRL_BASE	0xc8000000  /* LiteDRAM control registers */
+#define LETH_CSR_BASE	0xc8020000  /* LiteEth CSR registers */
+#define LETH_SRAM_BASE	0xc8030000  /* LiteEth MMIO space */
+#define SPI_FLASH_BASE  0xf0000000  /* SPI Flash memory map */
+#define DRAM_INIT_BASE  0xff000000  /* Internal DRAM init firmware */
+
+/*
+ * Interrupt numbers
+ */
+#define IRQ_UART0       0
+#define IRQ_ETHERNET    1
+
+/*
+ * Register definitions for the syscon registers
+ */
+
+#define SYS_REG_SIGNATURE		0x00
+#define SYS_REG_INFO			0x08
+#define   SYS_REG_INFO_HAS_UART 		(1ull << 0)
+#define   SYS_REG_INFO_HAS_DRAM 		(1ull << 1)
+#define   SYS_REG_INFO_HAS_BRAM 		(1ull << 2)
+#define   SYS_REG_INFO_HAS_SPI_FLASH 		(1ull << 3)
+#define   SYS_REG_INFO_HAS_LITEETH 		(1ull << 4)
+#define   SYS_REG_INFO_HAS_LARGE_SYSCON	        (1ull << 5)
+#define   SYS_REG_INFO_HAS_UART1 		(1ull << 6)
+#define   SYS_REG_INFO_HAS_ARTB                 (1ull << 7)
+#define SYS_REG_BRAMINFO		0x10
+#define   SYS_REG_BRAMINFO_SIZE_MASK		0xfffffffffffffull
+#define SYS_REG_DRAMINFO		0x18
+#define   SYS_REG_DRAMINFO_SIZE_MASK		0xfffffffffffffull
+#define SYS_REG_CLKINFO			0x20
+#define   SYS_REG_CLKINFO_FREQ_MASK		0xffffffffffull
+#define SYS_REG_CTRL			0x28
+#define   SYS_REG_CTRL_DRAM_AT_0		(1ull << 0)
+#define   SYS_REG_CTRL_CORE_RESET		(1ull << 1)
+#define   SYS_REG_CTRL_SOC_RESET		(1ull << 2)
+#define SYS_REG_DRAMINITINFO		0x30
+#define SYS_REG_SPI_INFO		0x38
+#define   SYS_REG_SPI_INFO_FLASH_OFF_MASK	0xffffffff
+#define SYS_REG_UART0_INFO		0x40
+#define SYS_REG_UART1_INFO		0x48
+#define   SYS_REG_UART_IS_16550			(1ull << 32)
+
+
+/*
+ * Register definitions for the potato UART
+ */
+#define POTATO_CONSOLE_TX		0x00
+#define POTATO_CONSOLE_RX		0x08
+#define POTATO_CONSOLE_STATUS		0x10
+#define   POTATO_CONSOLE_STATUS_RX_EMPTY		0x01
+#define   POTATO_CONSOLE_STATUS_TX_EMPTY		0x02
+#define   POTATO_CONSOLE_STATUS_RX_FULL			0x04
+#define   POTATO_CONSOLE_STATUS_TX_FULL			0x08
+#define POTATO_CONSOLE_CLOCK_DIV	0x18
+#define POTATO_CONSOLE_IRQ_EN		0x20
+#define   POTATO_CONSOLE_IRQ_RX				0x01
+#define   POTATO_CONSOLE_IRQ_TX				0x02
+
+/*
+ * Register definitionss for our standard (16550 style) UART
+ */
+#define UART_REG_RX       0x00
+#define UART_REG_TX       0x00
+#define UART_REG_DLL      0x00
+#define UART_REG_IER      0x04
+#define   UART_REG_IER_RDI      0x01
+#define   UART_REG_IER_THRI     0x02
+#define   UART_REG_IER_RLSI     0x04
+#define   UART_REG_IER_MSI      0x08
+#define UART_REG_DLM      0x04
+#define UART_REG_IIR      0x08
+#define UART_REG_FCR      0x08
+#define   UART_REG_FCR_EN_FIFO  0x01
+#define   UART_REG_FCR_CLR_RCVR 0x02
+#define   UART_REG_FCR_CLR_XMIT 0x04
+#define   UART_REG_FCR_TRIG1    0x00
+#define   UART_REG_FCR_TRIG4    0x40
+#define   UART_REG_FCR_TRIG8    0x80
+#define   UART_REG_FCR_TRIG14   0xc0
+#define UART_REG_LCR      0x0c
+#define   UART_REG_LCR_5BIT	0x00
+#define   UART_REG_LCR_6BIT	0x01
+#define   UART_REG_LCR_7BIT	0x02
+#define   UART_REG_LCR_8BIT	0x03
+#define   UART_REG_LCR_STOP     0x04
+#define   UART_REG_LCR_PAR      0x08
+#define   UART_REG_LCR_EVEN_PAR 0x10
+#define   UART_REG_LCR_STIC_PAR 0x20
+#define   UART_REG_LCR_BREAK    0x40
+#define   UART_REG_LCR_DLAB     0x80
+#define UART_REG_MCR      0x10
+#define   UART_REG_MCR_DTR      0x01
+#define   UART_REG_MCR_RTS      0x02
+#define   UART_REG_MCR_OUT1     0x04
+#define   UART_REG_MCR_OUT2     0x08
+#define   UART_REG_MCR_LOOP     0x10
+#define UART_REG_LSR      0x14
+#define   UART_REG_LSR_DR       0x01
+#define   UART_REG_LSR_OE       0x02
+#define   UART_REG_LSR_PE       0x04
+#define   UART_REG_LSR_FE       0x08
+#define   UART_REG_LSR_BI       0x10
+#define   UART_REG_LSR_THRE     0x20
+#define   UART_REG_LSR_TEMT     0x40
+#define   UART_REG_LSR_FIFOE    0x80
+#define UART_REG_MSR      0x18
+#define UART_REG_SCR      0x1c
+
+
+/*
+ * Register definitions for the SPI controller
+ */
+#define SPI_REG_DATA       		0x00 /* Byte access: single wire transfer */
+#define SPI_REG_DATA_DUAL       	0x01 /* Byte access: dual wire transfer */
+#define SPI_REG_DATA_QUAD       	0x02 /* Byte access: quad wire transfer */
+#define SPI_REG_CTRL			0x04 /* Reset and manual mode control */
+#define   SPI_REG_CTRL_RESET            	0x01  /* reset all registers */
+#define   SPI_REG_CTRL_MANUAL_CS	        0x02  /* assert CS, enable manual mode */
+#define   SPI_REG_CTRL_CKDIV_SHIFT		8     /* clock div */
+#define   SPI_REG_CTRL_CKDIV_MASK		(0xff << SPI_REG_CTRL_CKDIV_SHIFT)
+#define SPI_REG_AUTO_CFG		0x08 /* Automatic map configuration */
+#define   SPI_REG_AUTO_CFG_CMD_SHIFT		0     /* Command to use for reads */
+#define   SPI_REG_AUTO_CFG_CMD_MASK		(0xff << SPI_REG_AUTO_CFG_CMD_SHIFT)
+#define   SPI_REG_AUTO_CFG_DUMMIES_SHIFT        8     /* # dummy cycles */
+#define   SPI_REG_AUTO_CFG_DUMMIES_MASK         (0x7  << SPI_REG_AUTO_CFG_DUMMIES_SHIFT)
+#define   SPI_REG_AUTO_CFG_MODE_SHIFT           11    /* SPI wire mode */
+#define   SPI_REG_AUTO_CFG_MODE_MASK            (0x3  << SPI_REG_AUTO_CFG_MODE_SHIFT)
+#define     SPI_REG_AUT_CFG_MODE_SINGLE         (0 << 11)
+#define     SPI_REG_AUT_CFG_MODE_DUAL           (2 << 11)
+#define     SPI_REG_AUT_CFG_MODE_QUAD           (3 << 11)
+#define   SPI_REG_AUTO_CFG_ADDR4                (1u << 13) /* 3 or 4 addr bytes */
+#define   SPI_REG_AUTO_CFG_CKDIV_SHIFT          16    /* clock div */
+#define   SPI_REG_AUTO_CFG_CKDIV_MASK           (0xff << SPI_REG_AUTO_CFG_CKDIV_SHIFT)
+#define   SPI_REG_AUTO_CFG_CSTOUT_SHIFT         24    /* CS timeout */
+#define   SPI_REG_AUTO_CFG_CSTOUT_MASK          (0x3f << SPI_REG_AUTO_CFG_CSTOUT_SHIFT)
+
+
+#endif /* __MICROWATT_SOC_H */
diff --git a/verilog/dv/caravel/microwatt/include/microwatt_util.h b/verilog/dv/caravel/microwatt/include/microwatt_util.h
new file mode 100644
index 0000000..cd10a8c
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/include/microwatt_util.h
@@ -0,0 +1,34 @@
+#ifndef __MICROWATT_UTIL_H
+#define __MICROWATT_UTIL_H
+
+#include "io.h"
+
+#define LA_REG			0xc8020000
+
+#define LA_MICROWATT_START	0xbadc0ffe
+#define LA_MICROWATT_SUCCESS	0x0ddf00d5
+#define LA_MICROWATT_FAILURE 	0x71077345
+
+#define GPIO1_MGMT_ENGINE_START	0x00010000
+#define GPIO1_MICROWATT_START	0x00020000
+#define GPIO1_SUCCESS		0x00030000
+#define GPIO1_FAILURE		0x00000000
+
+#ifdef __powerpc64__
+static inline void microwatt_alive(void)
+{
+	writel(LA_MICROWATT_START, LA_REG);
+}
+
+static inline void microwatt_success(void)
+{
+	writel(LA_MICROWATT_SUCCESS, LA_REG);
+}
+
+static inline void microwatt_failure(void)
+{
+	writel(LA_MICROWATT_FAILURE, LA_REG);
+}
+#endif
+
+#endif
diff --git a/verilog/dv/caravel/microwatt/lib/console.c b/verilog/dv/caravel/microwatt/lib/console.c
new file mode 100644
index 0000000..29bd749
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/lib/console.c
@@ -0,0 +1,131 @@
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "console.h"
+#include "microwatt_soc.h"
+#include "io.h"
+
+#define UART_BAUDS 115200
+
+/*
+ * Core UART functions to implement for a port
+ */
+
+static uint64_t uart_base;
+
+static unsigned long uart_divisor(unsigned long uart_freq, unsigned long bauds)
+{
+	return uart_freq / (bauds * 16);
+}
+
+static bool std_uart_rx_empty(void)
+{
+	return !(readb(uart_base + UART_REG_LSR) & UART_REG_LSR_DR);
+}
+
+static uint8_t std_uart_read(void)
+{
+	return readb(uart_base + UART_REG_RX);
+}
+
+static bool std_uart_tx_full(void)
+{
+	return !(readb(uart_base + UART_REG_LSR) & UART_REG_LSR_THRE);
+}
+
+static void std_uart_write(uint8_t c)
+{
+	writeb(c, uart_base + UART_REG_TX);
+}
+
+static void std_uart_set_irq_en(bool rx_irq, bool tx_irq)
+{
+	uint8_t ier = 0;
+
+	if (tx_irq)
+		ier |= UART_REG_IER_THRI;
+	if (rx_irq)
+		ier |= UART_REG_IER_RDI;
+	writeb(ier, uart_base + UART_REG_IER);
+}
+
+static void std_uart_init(uint64_t uart_freq)
+{
+	unsigned long div = uart_divisor(uart_freq, UART_BAUDS);
+
+	writeb(UART_REG_LCR_DLAB,     uart_base + UART_REG_LCR);
+	writeb(div & 0xff,            uart_base + UART_REG_DLL);
+	writeb(div >> 8,              uart_base + UART_REG_DLM);
+	writeb(UART_REG_LCR_8BIT,     uart_base + UART_REG_LCR);
+	writeb(UART_REG_MCR_DTR |
+	       UART_REG_MCR_RTS,      uart_base + UART_REG_MCR);
+	writeb(UART_REG_FCR_EN_FIFO |
+	       UART_REG_FCR_CLR_RCVR |
+	       UART_REG_FCR_CLR_XMIT, uart_base + UART_REG_FCR);
+}
+
+int getchar(void)
+{
+	while (std_uart_rx_empty())
+		/* Do nothing */ ;
+	return std_uart_read();
+}
+
+int putchar(int c)
+{
+	while(std_uart_tx_full())
+		/* Do Nothing */;
+	std_uart_write(c);
+	return c;
+}
+
+int puts(const char *str)
+{
+	unsigned int i;
+
+	for (i = 0; *str; i++) {
+		char c = *(str++);
+		if (c == 10)
+			putchar(13);
+		putchar(c);
+	}
+	return 0;
+}
+
+#ifndef __USE_LIBC
+size_t strlen(const char *s)
+{
+	size_t len = 0;
+
+	while (*s++)
+		len++;
+
+	return len;
+}
+#endif
+
+void console_init(void)
+{
+	uint64_t sys_info;
+	uint64_t proc_freq;
+	uint64_t uart_info = 0;
+	uint64_t uart_freq = 0;
+
+	proc_freq = readq(SYSCON_BASE + SYS_REG_CLKINFO) & SYS_REG_CLKINFO_FREQ_MASK;
+	sys_info  = readq(SYSCON_BASE + SYS_REG_INFO);
+
+	if (sys_info & SYS_REG_INFO_HAS_LARGE_SYSCON) {
+		uart_info = readq(SYSCON_BASE + SYS_REG_UART0_INFO);
+		uart_freq = uart_info & 0xffffffff;
+	}
+	if (uart_freq == 0)
+		uart_freq = proc_freq;
+
+	uart_base = UART_BASE;
+	std_uart_init(proc_freq);
+}
+
+void console_set_irq_en(bool rx_irq, bool tx_irq)
+{
+	std_uart_set_irq_en(rx_irq, tx_irq);
+}
diff --git a/verilog/dv/caravel/microwatt/lib/head.S b/verilog/dv/caravel/microwatt/lib/head.S
new file mode 100644
index 0000000..029e4be
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/lib/head.S
@@ -0,0 +1,59 @@
+/* Copyright 2013-2014 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * 	http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#define LA_REG  0xc8020000
+#define FLASH_AUTO_CFG_REG 0xc0006008
+
+/* Load an immediate 64-bit value into a register */
+#define LOAD_IMM64(r, e)			\
+	lis	r,(e)@highest;			\
+	ori	r,r,(e)@higher;			\
+	rldicr	r,r, 32, 31;			\
+	oris	r,r, (e)@h;			\
+	ori	r,r, (e)@l;
+
+	.section ".head","ax"
+	.global _start
+_start:
+	// Set SPI flash divider to 1
+	LOAD_IMM64(3, FLASH_AUTO_CFG_REG)
+	lwzcix	%r5,0,%r3
+	lis	%r0,0xF
+	andc	%r5,%r5,%r0
+	lis	%r4,0x1
+	or	%r5,%r5,%r4
+	stwcix	%r5,0,%r3
+
+	// Zero BSS
+	LOAD_IMM64(%r10,__bss_start)
+	LOAD_IMM64(%r11,__bss_end)
+	subf	%r11,%r10,%r11
+	addi	%r11,%r11,63
+	srdi.	%r11,%r11,6
+	beq	2f
+	mtctr	%r11
+1:	dcbz	0,%r10
+	addi	%r10,%r10,64
+	bdnz	1b
+
+2:	LOAD_IMM64(%r1,__stack_top)
+	li	%r0,0
+	stdu	%r0,-16(%r1)
+	LOAD_IMM64(%r12, main)
+	mtctr	%r12
+	bctrl
+	attn // terminate on exit
+	b .
diff --git a/verilog/dv/caravel/microwatt/logic_analyzer/Makefile b/verilog/dv/caravel/microwatt/logic_analyzer/Makefile
new file mode 100644
index 0000000..407840d
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/logic_analyzer/Makefile
@@ -0,0 +1,59 @@
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+PDK_PATH?=/ef/tech/SW/sky130A
+
+RISCV_CROSS_COMPILE?=riscv64-linux-gnu-
+RISCV_CFLAGS=-static -Os -g -Wall -march=rv32imc -mabi=ilp32 -ffreestanding -nostdlib
+
+POWERPC_CROSS_COMPILE?=powerpc64le-linux-gnu-
+POWERPC_CFLAGS=-static -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -ffreestanding -fdata-sections -ffunction-sections -nostdlib -I../include
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = logic_analyzer
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v mgmt_engine.hex microwatt.hex
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+else
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+# Management engine code
+
+mgmt_engine.elf: mgmt_engine.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s lfsr32.c
+	$(RISCV_CROSS_COMPILE)gcc $(RISCV_CFLAGS) -Wl,-T,$(FIRMWARE_PATH)/sections.lds -o $@ $(FIRMWARE_PATH)/start.s lfsr32.c $<
+
+mgmt_engine.hex: mgmt_engine.elf
+	$(RISCV_CROSS_COMPILE)objcopy -O verilog $< $@
+	# to fix flash base address
+	sed -i 's/@1000/@0000/g' $@
+
+# Microwatt code
+microwatt.elf: microwatt.c ../lib/console.c ../lib/head.S ../microwatt.lds lfsr32.c
+	$(POWERPC_CROSS_COMPILE)gcc $(POWERPC_CFLAGS) -Wl,-T,../microwatt.lds -o $@ microwatt.c ../lib/console.c ../lib/head.S lfsr32.c
+
+microwatt.hex: microwatt.elf
+	$(POWERPC_CROSS_COMPILE)objcopy -O verilog $< $@
+	# to fix flash base address
+	sed -i 's/@F000/@0000/g' $@
+
+clean:
+	rm -f *.vvp *.vcd *.elf *.bin *.o *.vvp *.vcd *.log *.hex
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/microwatt/logic_analyzer/lfsr32.c b/verilog/dv/caravel/microwatt/logic_analyzer/lfsr32.c
new file mode 100644
index 0000000..5f78425
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/logic_analyzer/lfsr32.c
@@ -0,0 +1,15 @@
+#include "lfsr32.h"
+#include <stdint.h>
+
+#define LFSR_32 ((1 << (32-1)) | (1 << (22-1)) | (1 << (2-1)) | (1 << (1-1)))
+
+uint32_t lfsr32(uint32_t prev)
+{
+	uint32_t lsb = prev & 1;
+
+	prev >>= 1;
+	if (lsb == 1)
+		prev ^= LFSR_32;
+
+	return prev;
+}
diff --git a/verilog/dv/caravel/microwatt/logic_analyzer/lfsr32.h b/verilog/dv/caravel/microwatt/logic_analyzer/lfsr32.h
new file mode 100644
index 0000000..2679a78
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/logic_analyzer/lfsr32.h
@@ -0,0 +1,10 @@
+#ifndef __LFSR32_H
+#define __LFSR32_H
+
+#include <stdint.h>
+
+#define LFSR32_INIT 0x73983355
+
+uint32_t lfsr32(uint32_t prev);
+
+#endif
diff --git a/verilog/dv/caravel/microwatt/logic_analyzer/logic_analyzer_tb.v b/verilog/dv/caravel/microwatt/logic_analyzer/logic_analyzer_tb.v
new file mode 100644
index 0000000..77393c0
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/logic_analyzer/logic_analyzer_tb.v
@@ -0,0 +1,168 @@
+`default_nettype none
+/*
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *  Copyright (C) 2020  Anton Blanchard <anton@linux.ibm.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module logic_analyzer_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+	reg power1, power2;
+
+	wire gpio;
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire [37:0] mprj_io;
+	wire [3:0] checkbits;
+	wire user_flash_csb;
+	wire user_flash_clk;
+	inout user_flash_io0;
+	inout user_flash_io1;
+
+	assign user_flash_csb = mprj_io[8];
+	assign user_flash_clk = mprj_io[9];
+	assign user_flash_io0 = mprj_io[10];
+	assign mprj_io[11] = user_flash_io1;
+
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	assign checkbits = mprj_io[17:16];
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#1000;
+		RSTB <= 1'b1;		// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	// 50 MHz clock
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("logic_analyzer.vcd");
+		$dumpvars(0, logic_analyzer_tb);
+
+		$display("Microwatt logic analyzer test");
+
+		// Set the timeout at around 10x what the test should finish
+		// in
+		repeat (1000000) begin
+			@(posedge clock);
+		end
+
+		$display("Timeout, test failed");
+		$fatal;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+	initial begin
+		wait(checkbits == 2'h1);
+		$display("Management engine started");
+
+		wait(checkbits == 2'h2);
+		$display("Microwatt alive!");
+
+		wait(checkbits == 2'h3);
+		$display("Success!");
+		$finish;
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("mgmt_engine.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+	spiflash #(
+		.FILENAME("microwatt.hex")
+	) spiflash_microwatt (
+		.csb(user_flash_csb),
+		.clk(user_flash_clk),
+		.io0(user_flash_io0),
+		.io1(user_flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/microwatt/logic_analyzer/mgmt_engine.c b/verilog/dv/caravel/microwatt/logic_analyzer/mgmt_engine.c
new file mode 100644
index 0000000..a8ec0ce
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/logic_analyzer/mgmt_engine.c
@@ -0,0 +1,44 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../include/microwatt_util.h"
+#include "../include/mgmt_engine_util.h"
+
+#include "lfsr32.h"
+
+// --------------------------------------------------------
+
+void main(void)
+{
+	unsigned long lfsr = LFSR32_INIT;
+
+	mgmt_engine_io_setup(false, true);
+
+	// Take microwatt out of reset
+	reg_la2_data &= ~0x00000002;
+
+	while (reg_la0_data != LA_MICROWATT_START)
+		/* Do Nothing */ ;
+
+	// Signal to TB that microwatt is alive
+	reg_mprj_datal = GPIO1_MICROWATT_START;
+
+	for (unsigned long i = 0; i < 10; i++) {
+		// Send next LFSR in the sequence to Microwatt
+		reg_la1_data = lfsr;
+
+		lfsr = lfsr32(lfsr);
+
+		// Wait for next LFSR in the sequence from Microwatt
+		while (reg_la0_data != lfsr)
+			/* Do Nothing */ ;
+
+		lfsr = lfsr32(lfsr);
+	}
+
+	// Signal success to the TB
+	reg_mprj_datal = GPIO1_SUCCESS;
+
+	while (1)
+		/* Do Nothing */;
+}
diff --git a/verilog/dv/caravel/microwatt/logic_analyzer/microwatt.c b/verilog/dv/caravel/microwatt/logic_analyzer/microwatt.c
new file mode 100644
index 0000000..18be89b
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/logic_analyzer/microwatt.c
@@ -0,0 +1,26 @@
+#include <stdint.h>
+
+#include "microwatt_util.h"
+#include "lfsr32.h"
+
+#define LA_OFFSET 0xc8020000
+
+int main(void)
+{
+	uint32_t lfsr = LFSR32_INIT;
+
+	microwatt_alive();
+
+	while (1) {
+		// Wait for next LFSR in the sequence from Microwatt
+		while (readl(LA_OFFSET) != lfsr)
+			/* Do Nothing */ ;
+
+		lfsr = lfsr32(lfsr);
+
+		// Send next LFSR in the sequence to Microwatt
+		writel(lfsr, LA_OFFSET);
+
+		lfsr = lfsr32(lfsr);
+	}
+}
diff --git a/verilog/dv/caravel/microwatt/memory_test/Makefile b/verilog/dv/caravel/microwatt/memory_test/Makefile
new file mode 100644
index 0000000..4959234
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/memory_test/Makefile
@@ -0,0 +1,59 @@
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+PDK_PATH?=/ef/tech/SW/sky130A
+
+RISCV_CROSS_COMPILE?=riscv64-linux-gnu-
+RISCV_CFLAGS=-static -Os -g -Wall -march=rv32imc -mabi=ilp32 -ffreestanding -nostdlib
+
+POWERPC_CROSS_COMPILE?=powerpc64le-linux-gnu-
+POWERPC_CFLAGS=-static -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -ffreestanding -fdata-sections -ffunction-sections -nostdlib -I../include
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = memory_test
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v mgmt_engine.hex microwatt.hex
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+else
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+# Management engine code
+
+mgmt_engine.elf: mgmt_engine.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	$(RISCV_CROSS_COMPILE)gcc $(RISCV_CFLAGS) -Wl,-T,$(FIRMWARE_PATH)/sections.lds -o $@ $(FIRMWARE_PATH)/start.s $<
+
+mgmt_engine.hex: mgmt_engine.elf
+	$(RISCV_CROSS_COMPILE)objcopy -O verilog $< $@
+	# to fix flash base address
+	sed -i 's/@1000/@0000/g' $@
+
+# Microwatt code
+microwatt.elf: microwatt.c ../lib/console.c ../lib/head.S ../microwatt.lds hash.h
+	$(POWERPC_CROSS_COMPILE)gcc $(POWERPC_CFLAGS) -Wl,-T,../microwatt.lds -o $@ microwatt.c ../lib/console.c ../lib/head.S
+
+microwatt.hex: microwatt.elf
+	$(POWERPC_CROSS_COMPILE)objcopy -O verilog $< $@
+	# to fix flash base address
+	sed -i 's/@F000/@0000/g' $@
+
+clean:
+	rm -f *.vvp *.vcd *.elf *.bin *.o *.vvp *.vcd *.log *.hex
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/microwatt/memory_test/hash.h b/verilog/dv/caravel/microwatt/memory_test/hash.h
new file mode 100644
index 0000000..88c3d98
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/memory_test/hash.h
@@ -0,0 +1,10 @@
+#ifndef __HASH_H
+#define __HASH_H
+
+#define GOLDEN_RATIO_64 0x61C8864680B583EBull
+
+static inline uint64_t hash_64(uint64_t val, uint32_t bits)
+{
+	return val * GOLDEN_RATIO_64 >> (64 - bits);
+}
+#endif
diff --git a/verilog/dv/caravel/microwatt/memory_test/memory_test_tb.v b/verilog/dv/caravel/microwatt/memory_test/memory_test_tb.v
new file mode 100644
index 0000000..67abecc
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/memory_test/memory_test_tb.v
@@ -0,0 +1,185 @@
+`default_nettype none
+/*
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *  Copyright (C) 2020  Anton Blanchard <anton@linux.ibm.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart_modified.v"
+
+module memory_test;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+	reg power1, power2;
+
+	wire gpio;
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire [37:0] mprj_io;
+	wire [1:0] checkbits;
+	wire uart_tx;
+	wire user_flash_csb;
+	wire user_flash_clk;
+	inout user_flash_io0;
+	inout user_flash_io1;
+	inout user_flash_io2;
+	inout user_flash_io3;
+
+	assign user_flash_csb = mprj_io[8];
+	assign user_flash_clk = mprj_io[9];
+
+	// Without output enables, how can we hook up bidirectional pins?
+	assign user_flash_io0 = mprj_io[10];
+	assign mprj_io[11] = user_flash_io1;
+	assign user_flash_io2 = mprj_io[12];
+	assign user_flash_io3 = mprj_io[13];
+
+	assign checkbits = mprj_io[17:16];
+
+	assign uart_tx = mprj_io[6];
+	assign mprj_io[5] = 1'b1;
+
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	// 50 MHz clock
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("memory_test.vcd");
+		$dumpvars(0, memory_test);
+
+		$display("Microwatt memory test");
+
+		repeat (500000) @(posedge clock);
+		$display("Timeout");
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#1000;
+		RSTB <= 1'b1;		// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+	always @(checkbits) begin
+                wait(checkbits == 2'h1);
+                $display("Management engine started");
+
+                wait(checkbits == 2'h2);
+                $display("Microwatt alive!");
+
+		wait(checkbits != 2'h2);
+
+		if(checkbits == 2'h0) begin
+			$display("Fail");
+			$finish;
+		end
+
+		if(checkbits == 2'h3) begin
+			$display("Success");
+			$finish;
+		end
+
+		$display("Unknown Failure %x", checkbits);
+		$finish;
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("mgmt_engine.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+	spiflash #(
+		.FILENAME("microwatt.hex")
+	) spiflash_microwatt (
+		.csb(user_flash_csb),
+		.clk(user_flash_clk),
+		.io0(user_flash_io0),
+		.io1(user_flash_io1),
+		.io2(user_flash_io2),
+		.io3(user_flash_io3)
+	);
+
+	tbuart_modified #(
+		.baud_rate(115200)
+	) tbuart (
+		.ser_rx(uart_tx)
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/microwatt/memory_test/mgmt_engine.c b/verilog/dv/caravel/microwatt/memory_test/mgmt_engine.c
new file mode 100644
index 0000000..0711a5d
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/memory_test/mgmt_engine.c
@@ -0,0 +1,39 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../include/microwatt_util.h"
+#include "../include/mgmt_engine_util.h"
+
+// --------------------------------------------------------
+
+void main(void)
+{
+	mgmt_engine_io_setup(false, true);
+
+	// Take microwatt out of reset
+	reg_la2_data &= ~0x00000002;
+
+	while (reg_la0_data != LA_MICROWATT_START)
+		/* Do Nothing */ ;
+
+	// Signal to TB that microwatt is alive
+	reg_mprj_datal = GPIO1_MICROWATT_START;
+
+	while (1) {
+		if (reg_la0_data == LA_MICROWATT_SUCCESS) {
+			// Signal success to the TB
+			reg_mprj_datal = GPIO1_SUCCESS;
+			goto out;
+		}
+
+		if (reg_la0_data == LA_MICROWATT_FAILURE) {
+			// Signal failure to the TB
+			reg_mprj_datal = GPIO1_FAILURE;
+			goto out;
+		}
+	}
+
+out:
+	while (1)
+		/* Do Nothing */ ;
+}
diff --git a/verilog/dv/caravel/microwatt/memory_test/microwatt.c b/verilog/dv/caravel/microwatt/memory_test/microwatt.c
new file mode 100644
index 0000000..0fce0fe
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/memory_test/microwatt.c
@@ -0,0 +1,53 @@
+#include <stdint.h>
+
+#include "microwatt_util.h"
+#include "console.h"
+#include "hash.h"
+
+static void print_hex(unsigned long val)
+{
+	int i, x;
+
+	for (i = 60; i >= 0; i -= 4) {
+		x = (val >> i) & 0xf;
+		if (x >= 10)
+			putchar(x + 'a' - 10);
+		else
+			putchar(x + '0');
+	}
+}
+
+int main(void)
+{
+	console_init();
+	microwatt_alive();
+
+	// gcc will optimise away a NULL pointer access, so start at offset 1
+	for (unsigned long i = 1; i < 4096; i += 8)
+		*(unsigned long *)i = hash_64(i, 64);
+
+	for (unsigned long i = 1; i < 4096; i+=8) {
+		unsigned long exp;
+		unsigned long got;
+
+		exp = hash_64(i, 64);
+		got = *(unsigned long *)i;
+
+		if (exp != got) {
+			print_hex(exp);
+			putchar(' ');
+			print_hex(got);
+
+			/* Signal success to management engine */
+			microwatt_failure();
+			goto out;
+		}
+	}
+
+	/* Signal success to management engine */
+	microwatt_success();
+
+out:
+	while (1)
+		/* Do Nothing */ ;
+}
diff --git a/verilog/dv/caravel/microwatt/memory_test/tbuart_modified.v b/verilog/dv/caravel/microwatt/memory_test/tbuart_modified.v
new file mode 100644
index 0000000..ad9b8f9
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/memory_test/tbuart_modified.v
@@ -0,0 +1,83 @@
+`default_nettype none
+/*
+ *  PicoSoC - A simple example SoC using PicoRV32
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+/* tbuart --- mimic an external UART display, operating at 9600 baud	*/
+/* and accepting ASCII characters for display.				*/
+
+/* To do:  Match a known UART 3.3V 16x2 LCD display.  However, it	*/
+/* should be possible on a testing system to interface to the UART	*/
+/* pins on a Raspberry Pi, also running at 3.3V.			*/
+
+module tbuart_modified # (
+	parameter baud_rate = 115200
+) (
+	input  ser_rx
+);
+	reg [3:0] recv_state;
+	reg [2:0] recv_divcnt;
+	reg [7:0] recv_pattern;
+
+	reg clk;
+
+	initial begin
+		clk <= 1'b0;
+		recv_state <= 0;
+		recv_divcnt <= 0;
+		recv_pattern <= 0;
+	end
+
+	// Our simulation is in nanosecond steps and we want 5 clocks per bit,
+	// ie 10 clock transitions
+	always #(1000000000/baud_rate/10) clk <= (clk === 1'b0);
+
+	always @(posedge clk) begin
+		recv_divcnt <= recv_divcnt + 1;
+		case (recv_state)
+			0: begin
+				if (!ser_rx)
+					recv_state <= 1;
+				recv_divcnt <= 0;
+			end
+			1: begin
+				if (2*recv_divcnt > 3'd3) begin
+					recv_state <= 2;
+					recv_divcnt <= 0;
+				end
+			end
+			10: begin
+				if (recv_divcnt > 3'd3) begin
+					recv_state <= 0;
+					$write("%c", recv_pattern);
+					$fflush();
+				end
+			end
+			default: begin
+				if (recv_divcnt > 3'd3) begin
+					recv_pattern <= {ser_rx, recv_pattern[7:1]};
+					recv_state <= recv_state + 1;
+					recv_divcnt <= 0;
+				end
+			end
+		endcase
+	end
+
+endmodule
diff --git a/verilog/dv/caravel/microwatt/microwatt-nia/Cargo.toml b/verilog/dv/caravel/microwatt/microwatt-nia/Cargo.toml
new file mode 100644
index 0000000..3bf1207
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/microwatt-nia/Cargo.toml
@@ -0,0 +1,8 @@
+[package]
+name = "microwatt-nia"
+version = "0.1.0"
+authors = ["Anton Blanchard <anton@linux.ibm.com>"]
+edition = "2018"
+
+[dependencies]
+vcd = "0.6.1"
diff --git a/verilog/dv/caravel/microwatt/microwatt-nia/README.md b/verilog/dv/caravel/microwatt/microwatt-nia/README.md
new file mode 100644
index 0000000..2b9807c
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/microwatt-nia/README.md
@@ -0,0 +1,8 @@
+# microwatt-nia
+
+Parses a caravel-microwatt VCD file and prints all the Microwatt NIAs. It requires
+a rust toolchain to build. To build:
+
+```
+cargo build  --release
+```
diff --git a/verilog/dv/caravel/microwatt/microwatt-nia/src/main.rs b/verilog/dv/caravel/microwatt/microwatt-nia/src/main.rs
new file mode 100644
index 0000000..b367ac3
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/microwatt-nia/src/main.rs
@@ -0,0 +1,76 @@
+use std::env;
+use std::io::BufReader;
+use std::fs::File;
+use std::io;
+use std::io::ErrorKind::InvalidInput;
+use vcd::{ self, Value, ScopeItem };
+
+fn read_vcd<R: io::Read>(r: &mut R) -> io::Result<()> {
+    let mut parser = vcd::Parser::new(r);
+
+    let header = parser.parse_header()?;
+
+    // Find top level scope
+    let top_scope = match &header.items[0] {
+        ScopeItem::Scope(sc) => sc,
+        x => panic!("Expected Scope, found {:?}", x),
+    };
+
+    let reset = header.find_var(&[&top_scope.identifier[..], "uut", "mprj", "microwatt_0", "ext_rst"])
+                      .ok_or_else(|| io::Error::new(InvalidInput, "Could not find microwatt reset"))?.code;
+
+    let nia = header.find_var(&[&top_scope.identifier[..], "uut", "mprj", "microwatt_0", "soc0", "processor", "debug_0", "nia"])
+                    .ok_or_else(|| io::Error::new(InvalidInput, "Could not find microwatt nia signal"))?.code;
+
+    let mut nia_val : u64;
+    let mut in_reset = true;
+
+    for command_result in parser {
+        use vcd::Command::*;
+        let command = command_result?;
+        match command {
+            ChangeVector(i, v) if i == nia => {
+                if in_reset == false {
+                    nia_val = 0;
+
+                    for x in v.iter() {
+                        match x {
+                            Value::V1 => {
+                                nia_val = (nia_val << 1) | 1;
+                            }
+                            Value::V0 => {
+                                nia_val = (nia_val << 1) | 0;
+                            }
+                            _ => {
+                                panic!("NIA is X or Z state");
+                            }
+                        }
+                    }
+
+                    println!("{:#018x}", nia_val);
+                }
+            }
+
+            ChangeScalar(i, v) if i == reset => {
+                if v == Value::V0{
+                    in_reset = false;
+                }
+            }
+
+            _ => (),
+        }
+    }
+
+    Ok(())
+}
+
+fn main() -> std::io::Result<()> {
+    let filename = env::args().nth(1).expect("No VCD file given");
+    let file = File::open(filename)?;
+    // The VCD parser isn't buffering reads, this speeds things up a bunch
+    let mut reader = BufReader::new(file);
+
+    read_vcd(&mut reader).expect("Failed to parse VCD file");
+
+    Ok(())
+}
diff --git a/verilog/dv/caravel/microwatt/microwatt.lds b/verilog/dv/caravel/microwatt/microwatt.lds
new file mode 100644
index 0000000..e1fb499
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/microwatt.lds
@@ -0,0 +1,57 @@
+MEMORY {
+	FLASH(rx)	: ORIGIN = 0xf0000000, LENGTH = 0x400000	/* 4MB */
+	RAM(xrw)	: ORIGIN = 0x00000000, LENGTH = 0x0400		/* 1024 kB */
+}
+
+SECTIONS
+{
+	. = 0xf0000000;
+	_start = .;
+	.text : {
+		KEEP(*(.head))
+		*(.text)
+		*(.text.*)
+		*(.sfpr)
+		*(.eh_frame)
+		*(.rodata)
+		*(.rodata.*)
+		. = ALIGN(8);
+		_etext = .;		/* define a global symbol at end of code */
+		_sidata = _etext;	/* This is used by the startup to initialize data */
+ 	} > FLASH
+
+	.data : AT ( _sidata ) {
+		. = ALIGN(8);
+		_sdata = .;
+		_ram_start = .;
+		. = ALIGN(8);
+		*(.data)
+		*(.data*)
+		*(.sdata)
+		*(.sdata*)
+		. = ALIGN(8);
+		_edata = .;
+	} > RAM
+
+	.bss : {
+		__bss_start = .;
+		*(.dynsbss)
+		*(.sbss)
+		*(.scommon)
+		*(.dynbss)
+		*(.bss)
+		*(.common)
+		*(.bss.*)
+
+		. = . + 0x300;
+		__stack_top = .;
+
+		. = ALIGN(0x80);
+		__bss_end = .;
+	} > RAM
+
+	/DISCARD/ :
+	{
+		*(.note.gnu.build-id)
+	}
+}
diff --git a/verilog/dv/caravel/microwatt/minimal/Makefile b/verilog/dv/caravel/microwatt/minimal/Makefile
new file mode 100644
index 0000000..348256e
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/minimal/Makefile
@@ -0,0 +1,59 @@
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+PDK_PATH?=/ef/tech/SW/sky130A
+
+RISCV_CROSS_COMPILE?=riscv64-linux-gnu-
+RISCV_CFLAGS=-static -Os -g -Wall -march=rv32imc -mabi=ilp32 -ffreestanding -nostdlib
+
+POWERPC_CROSS_COMPILE?=powerpc64le-linux-gnu-
+POWERPC_CFLAGS=-static -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -ffreestanding -fdata-sections -ffunction-sections -nostdlib -I../include
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = minimal
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v mgmt_engine.hex microwatt.hex
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+else
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+# Management engine code
+
+mgmt_engine.elf: mgmt_engine.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	$(RISCV_CROSS_COMPILE)gcc $(RISCV_CFLAGS) -Wl,-T,$(FIRMWARE_PATH)/sections.lds -o $@ $(FIRMWARE_PATH)/start.s $<
+
+mgmt_engine.hex: mgmt_engine.elf
+	$(RISCV_CROSS_COMPILE)objcopy -O verilog $< $@
+	# to fix flash base address
+	sed -i 's/@1000/@0000/g' $@
+
+# Microwatt code
+microwatt.elf: head.S ../microwatt.lds
+	$(POWERPC_CROSS_COMPILE)gcc $(POWERPC_CFLAGS) -Wl,-T,../microwatt.lds -o $@ head.S
+
+microwatt.hex: microwatt.elf
+	$(POWERPC_CROSS_COMPILE)objcopy -O verilog $< $@
+	# to fix flash base address
+	sed -i 's/@F000/@0000/g' $@
+
+clean:
+	rm -f *.vvp *.vcd *.elf *.bin *.o *.vvp *.vcd *.log *.hex
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/microwatt/minimal/head.S b/verilog/dv/caravel/microwatt/minimal/head.S
new file mode 100644
index 0000000..4d1e0c2
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/minimal/head.S
@@ -0,0 +1,34 @@
+/* Copyright 2013-2014 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * 	http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#define LA_REG	0xc8020000
+
+/* Load an immediate 64-bit value into a register */
+#define LOAD_IMM64(r, e)			\
+	lis	r,(e)@highest;			\
+	ori	r,r,(e)@higher;			\
+	rldicr	r,r, 32, 31;			\
+	oris	r,r, (e)@h;			\
+	ori	r,r, (e)@l;
+
+	.section ".head","ax"
+	.global _start
+_start:
+	LOAD_IMM64(%r3, LA_REG)
+	LOAD_IMM64(%r4, 0xbadc0ffe)
+	stwcix %r4,0,%r3
+
+1:	b 1b
diff --git a/verilog/dv/caravel/microwatt/minimal/mgmt_engine.c b/verilog/dv/caravel/microwatt/minimal/mgmt_engine.c
new file mode 100644
index 0000000..75fd72f
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/minimal/mgmt_engine.c
@@ -0,0 +1,22 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../include/microwatt_util.h"
+#include "../include/mgmt_engine_util.h"
+
+void main(void)
+{
+	mgmt_engine_io_setup(false, true);
+
+	// Take microwatt out of reset
+	reg_la2_data &= ~0x00000002;
+
+	while (reg_la0_data != LA_MICROWATT_START)
+		/* Do Nothing */ ;
+
+	// Signal success to the tb
+	reg_mprj_datal = GPIO1_SUCCESS;
+
+	while (1)
+		/* Do Nothing */;
+}
diff --git a/verilog/dv/caravel/microwatt/minimal/minimal_tb.v b/verilog/dv/caravel/microwatt/minimal/minimal_tb.v
new file mode 100644
index 0000000..7287d46
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/minimal/minimal_tb.v
@@ -0,0 +1,160 @@
+`default_nettype none
+/*
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *  Copyright (C) 2020  Anton Blanchard <anton@linux.ibm.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module minimal;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+	reg power1, power2;
+
+	wire gpio;
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire [37:0] mprj_io;
+	wire [1:0] checkbits;
+	wire user_flash_csb;
+	wire user_flash_clk;
+	inout user_flash_io0;
+	inout user_flash_io1;
+
+	assign user_flash_csb = mprj_io[8];
+	assign user_flash_clk = mprj_io[9];
+	assign user_flash_io0 = mprj_io[10];
+	assign mprj_io[11] = user_flash_io1;
+
+	assign checkbits = mprj_io[17:16];
+
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	// 50 MHz clock
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("minimal.vcd");
+		$dumpvars(0, minimal);
+
+		$display("Microwatt minimal test");
+
+		// Set the timeout at around 10x what the test should finish
+		// in
+		repeat (200000) begin
+			@(posedge clock);
+		end
+
+		$display("Timeout, test failed");
+		$fatal;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#1000;
+		RSTB <= 1'b1;		// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+	initial begin
+		wait(checkbits == 2'h1);
+		$display("Management engine started");
+
+		wait(checkbits == 2'h3);
+		$display("Microwatt alive!");
+
+		$finish;
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("mgmt_engine.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+	spiflash #(
+		.FILENAME("microwatt.hex")
+	) spiflash_microwatt (
+		.csb(user_flash_csb),
+		.clk(user_flash_clk),
+		.io0(user_flash_io0),
+		.io1(user_flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/microwatt/spi_flash/Makefile b/verilog/dv/caravel/microwatt/spi_flash/Makefile
new file mode 100644
index 0000000..379ed04
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/spi_flash/Makefile
@@ -0,0 +1,63 @@
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+PDK_PATH?=/ef/tech/SW/sky130A
+
+RISCV_CROSS_COMPILE?=riscv64-linux-gnu-
+RISCV_CFLAGS=-static -Os -g -Wall -march=rv32imc -mabi=ilp32 -ffreestanding -nostdlib
+
+POWERPC_CROSS_COMPILE?=powerpc64le-linux-gnu-
+POWERPC_CFLAGS=-static -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -ffreestanding -fdata-sections -ffunction-sections -nostdlib -I../include
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = spi_flash
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v mgmt_engine.hex microwatt.hex
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+else
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+gen_hash: gen_hash.c
+	$(CC) -O2 -o $@ $<
+
+# Management engine code
+
+mgmt_engine.elf: mgmt_engine.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	$(RISCV_CROSS_COMPILE)gcc $(RISCV_CFLAGS) -Wl,-T,$(FIRMWARE_PATH)/sections.lds -o $@ $(FIRMWARE_PATH)/start.s $<
+
+mgmt_engine.hex: mgmt_engine.elf
+	$(RISCV_CROSS_COMPILE)objcopy -O verilog $< $@
+	# to fix flash base address
+	sed -i 's/@1000/@0000/g' $@
+
+# Microwatt code
+microwatt.elf: microwatt.c ../lib/console.c ../lib/head.S ../microwatt.lds lfsr32.c
+	$(POWERPC_CROSS_COMPILE)gcc $(POWERPC_CFLAGS) -Wl,-T,../microwatt.lds -o $@ microwatt.c ../lib/console.c ../lib/head.S lfsr32.c
+
+microwatt.hex: microwatt.elf gen_hash
+	$(POWERPC_CROSS_COMPILE)objcopy -O verilog $< $@
+	# to fix flash base address
+	sed -i 's/@F000/@0000/g' $@
+	./gen_hash >> $@
+
+clean:
+	rm -f *.vvp *.vcd *.elf *.bin *.o *.vvp *.vcd *.log *.hex gen_hash
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/microwatt/spi_flash/gen_hash.c b/verilog/dv/caravel/microwatt/spi_flash/gen_hash.c
new file mode 100644
index 0000000..34aab46
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/spi_flash/gen_hash.c
@@ -0,0 +1,22 @@
+#include <stdint.h>
+#include <stdio.h>
+#include "hash.h"
+
+#define START_OFFSET 0x2000UL
+#define END_OFFSET (16UL*1024*1024)
+
+int main(void)
+{
+	printf("@%lx\n", START_OFFSET);
+
+	for (uint64_t i = START_OFFSET; i < END_OFFSET; i += 8) {
+		uint64_t val = hash_64(i, 64);
+
+		for (unsigned long j = 0; j < 8; j++) {
+			printf("%02X ", (val >> (j*8) & 0xff));
+		}
+
+		if (i & 0xf)
+			printf("\n");
+	}
+}
diff --git a/verilog/dv/caravel/microwatt/spi_flash/hash.h b/verilog/dv/caravel/microwatt/spi_flash/hash.h
new file mode 100644
index 0000000..88c3d98
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/spi_flash/hash.h
@@ -0,0 +1,10 @@
+#ifndef __HASH_H
+#define __HASH_H
+
+#define GOLDEN_RATIO_64 0x61C8864680B583EBull
+
+static inline uint64_t hash_64(uint64_t val, uint32_t bits)
+{
+	return val * GOLDEN_RATIO_64 >> (64 - bits);
+}
+#endif
diff --git a/verilog/dv/caravel/microwatt/spi_flash/lfsr32.c b/verilog/dv/caravel/microwatt/spi_flash/lfsr32.c
new file mode 100644
index 0000000..5f78425
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/spi_flash/lfsr32.c
@@ -0,0 +1,15 @@
+#include "lfsr32.h"
+#include <stdint.h>
+
+#define LFSR_32 ((1 << (32-1)) | (1 << (22-1)) | (1 << (2-1)) | (1 << (1-1)))
+
+uint32_t lfsr32(uint32_t prev)
+{
+	uint32_t lsb = prev & 1;
+
+	prev >>= 1;
+	if (lsb == 1)
+		prev ^= LFSR_32;
+
+	return prev;
+}
diff --git a/verilog/dv/caravel/microwatt/spi_flash/lfsr32.h b/verilog/dv/caravel/microwatt/spi_flash/lfsr32.h
new file mode 100644
index 0000000..2679a78
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/spi_flash/lfsr32.h
@@ -0,0 +1,10 @@
+#ifndef __LFSR32_H
+#define __LFSR32_H
+
+#include <stdint.h>
+
+#define LFSR32_INIT 0x73983355
+
+uint32_t lfsr32(uint32_t prev);
+
+#endif
diff --git a/verilog/dv/caravel/microwatt/spi_flash/mgmt_engine.c b/verilog/dv/caravel/microwatt/spi_flash/mgmt_engine.c
new file mode 100644
index 0000000..ec3f375
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/spi_flash/mgmt_engine.c
@@ -0,0 +1,37 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../include/microwatt_util.h"
+#include "../include/mgmt_engine_util.h"
+
+void main(void)
+{
+	mgmt_engine_io_setup(false, true);
+
+	// Take microwatt out of reset
+	reg_la2_data &= ~0x00000002;
+
+	while (reg_la0_data != LA_MICROWATT_START)
+		/* Do Nothing */ ;
+
+	// Signal to TB that microwatt is alive
+	reg_mprj_datal = GPIO1_MICROWATT_START;
+
+	while (1) {
+		if (reg_la0_data == LA_MICROWATT_SUCCESS) {
+			// Signal success to the TB
+			reg_mprj_datal = GPIO1_SUCCESS;
+			goto out;
+		}
+
+		if (reg_la0_data == LA_MICROWATT_FAILURE) {
+			// Signal failure to the TB
+			reg_mprj_datal = GPIO1_FAILURE;
+			goto out;
+		}
+	}
+
+out:
+	while (1)
+		/* Do Nothing */ ;
+}
diff --git a/verilog/dv/caravel/microwatt/spi_flash/microwatt.c b/verilog/dv/caravel/microwatt/spi_flash/microwatt.c
new file mode 100644
index 0000000..ad2944b
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/spi_flash/microwatt.c
@@ -0,0 +1,67 @@
+#include <stdint.h>
+
+#include "microwatt_util.h"
+#include "console.h"
+#include "lfsr32.h"
+#include "hash.h"
+
+#define LA_OFFSET 0xc8020000
+
+#define FLASH_BASE 0xf0000000UL
+
+#define FLASH_OFFSET 0x2000
+#define FLASH_SIZE (16L*1024*1024)
+
+static void print_hex(unsigned long val)
+{
+	int i, x;
+
+	for (i = 60; i >= 0; i -= 4) {
+		x = (val >> i) & 0xf;
+		if (x >= 10)
+			putchar(x + 'a' - 10);
+		else
+			putchar(x + '0');
+	}
+}
+
+int main(void)
+{
+	uint32_t lfsr = LFSR32_INIT;
+
+	console_init();
+	microwatt_alive();
+
+	for (unsigned long i = 0; i < 16; i++) {
+		uint32_t o;
+		uint64_t exp;
+		uint64_t got;
+
+		o = lfsr % FLASH_SIZE;
+		// 16B align for now
+		o &= ~15UL;
+		if (o < FLASH_OFFSET)
+			o += FLASH_OFFSET;
+		lfsr = lfsr32(lfsr);
+
+		exp = hash_64(o, 64);
+
+		got = *(uint64_t *)(FLASH_BASE+o);
+		if (exp != got) {
+			print_hex(exp);
+			putchar(' ');
+			print_hex(got);
+			putchar('\n');
+			/* Signal success to management engine */
+			microwatt_failure();
+			goto out;
+		}
+	}
+
+	/* Signal success to management engine */
+	microwatt_success();
+
+out:
+	while (1)
+		/* Do Nothing */ ;
+}
diff --git a/verilog/dv/caravel/microwatt/spi_flash/spi_flash_tb.v b/verilog/dv/caravel/microwatt/spi_flash/spi_flash_tb.v
new file mode 100644
index 0000000..0861c93
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/spi_flash/spi_flash_tb.v
@@ -0,0 +1,185 @@
+`default_nettype none
+/*
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *  Copyright (C) 2020  Anton Blanchard <anton@linux.ibm.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart_modified.v"
+
+module spi_flash;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+	reg power1, power2;
+
+	wire gpio;
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire [37:0] mprj_io;
+	wire [1:0] checkbits;
+	wire uart_tx;
+	wire user_flash_csb;
+	wire user_flash_clk;
+	inout user_flash_io0;
+	inout user_flash_io1;
+	inout user_flash_io2;
+	inout user_flash_io3;
+
+	assign user_flash_csb = mprj_io[8];
+	assign user_flash_clk = mprj_io[9];
+
+	// Without output enables, how can we hook up bidirectional pins?
+	assign user_flash_io0 = mprj_io[10];
+	assign mprj_io[11] = user_flash_io1;
+	assign user_flash_io2 = mprj_io[12];
+	assign user_flash_io3 = mprj_io[13];
+
+	assign checkbits = mprj_io[17:16];
+
+	assign uart_tx = mprj_io[6];
+	assign mprj_io[5] = 1'b1;
+
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	// 50 MHz clock
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("spi_flash.vcd");
+		$dumpvars(0, spi_flash);
+
+		$display("Microwatt SPI flash test");
+
+		repeat (1000000) @(posedge clock);
+		$display("Timeout");
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#1000;
+		RSTB <= 1'b1;		// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+	always @(checkbits) begin
+                wait(checkbits == 2'h1);
+                $display("Management engine started");
+
+                wait(checkbits == 2'h2);
+                $display("Microwatt alive!");
+
+		wait(checkbits != 2'h2);
+
+		if(checkbits == 2'h0) begin
+			$display("Fail");
+			$finish;
+		end
+
+		if(checkbits == 2'h3) begin
+			$display("Success");
+			$finish;
+		end
+
+		$display("Unknown Failure %x", checkbits);
+		$finish;
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("mgmt_engine.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+	spiflash #(
+		.FILENAME("microwatt.hex")
+	) spiflash_microwatt (
+		.csb(user_flash_csb),
+		.clk(user_flash_clk),
+		.io0(user_flash_io0),
+		.io1(user_flash_io1),
+		.io2(user_flash_io2),
+		.io3(user_flash_io3)
+	);
+
+	tbuart_modified #(
+		.baud_rate(115200)
+	) tbuart (
+		.ser_rx(uart_tx)
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/microwatt/spi_flash/tbuart_modified.v b/verilog/dv/caravel/microwatt/spi_flash/tbuart_modified.v
new file mode 100644
index 0000000..ad9b8f9
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/spi_flash/tbuart_modified.v
@@ -0,0 +1,83 @@
+`default_nettype none
+/*
+ *  PicoSoC - A simple example SoC using PicoRV32
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+/* tbuart --- mimic an external UART display, operating at 9600 baud	*/
+/* and accepting ASCII characters for display.				*/
+
+/* To do:  Match a known UART 3.3V 16x2 LCD display.  However, it	*/
+/* should be possible on a testing system to interface to the UART	*/
+/* pins on a Raspberry Pi, also running at 3.3V.			*/
+
+module tbuart_modified # (
+	parameter baud_rate = 115200
+) (
+	input  ser_rx
+);
+	reg [3:0] recv_state;
+	reg [2:0] recv_divcnt;
+	reg [7:0] recv_pattern;
+
+	reg clk;
+
+	initial begin
+		clk <= 1'b0;
+		recv_state <= 0;
+		recv_divcnt <= 0;
+		recv_pattern <= 0;
+	end
+
+	// Our simulation is in nanosecond steps and we want 5 clocks per bit,
+	// ie 10 clock transitions
+	always #(1000000000/baud_rate/10) clk <= (clk === 1'b0);
+
+	always @(posedge clk) begin
+		recv_divcnt <= recv_divcnt + 1;
+		case (recv_state)
+			0: begin
+				if (!ser_rx)
+					recv_state <= 1;
+				recv_divcnt <= 0;
+			end
+			1: begin
+				if (2*recv_divcnt > 3'd3) begin
+					recv_state <= 2;
+					recv_divcnt <= 0;
+				end
+			end
+			10: begin
+				if (recv_divcnt > 3'd3) begin
+					recv_state <= 0;
+					$write("%c", recv_pattern);
+					$fflush();
+				end
+			end
+			default: begin
+				if (recv_divcnt > 3'd3) begin
+					recv_pattern <= {ser_rx, recv_pattern[7:1]};
+					recv_state <= recv_state + 1;
+					recv_divcnt <= 0;
+				end
+			end
+		endcase
+	end
+
+endmodule
diff --git a/verilog/dv/caravel/microwatt/uart/Makefile b/verilog/dv/caravel/microwatt/uart/Makefile
new file mode 100644
index 0000000..3aee23a
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/uart/Makefile
@@ -0,0 +1,59 @@
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+PDK_PATH?=/ef/tech/SW/sky130A
+
+RISCV_CROSS_COMPILE?=riscv64-linux-gnu-
+RISCV_CFLAGS=-static -Os -g -Wall -march=rv32imc -mabi=ilp32 -ffreestanding -nostdlib
+
+POWERPC_CROSS_COMPILE?=powerpc64le-linux-gnu-
+POWERPC_CFLAGS=-static -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -ffreestanding -fdata-sections -ffunction-sections -nostdlib -I../include
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = uart
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v mgmt_engine.hex microwatt.hex
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+else
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+# Management engine code
+
+mgmt_engine.elf: mgmt_engine.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	$(RISCV_CROSS_COMPILE)gcc $(RISCV_CFLAGS) -Wl,-T,$(FIRMWARE_PATH)/sections.lds -o $@ $(FIRMWARE_PATH)/start.s $<
+
+mgmt_engine.hex: mgmt_engine.elf
+	$(RISCV_CROSS_COMPILE)objcopy -O verilog $< $@
+	# to fix flash base address
+	sed -i 's/@1000/@0000/g' $@
+
+# Microwatt code
+microwatt.elf: microwatt.c ../lib/console.c ../lib/head.S ../microwatt.lds
+	$(POWERPC_CROSS_COMPILE)gcc $(POWERPC_CFLAGS) -Wl,-T,../microwatt.lds -o $@ microwatt.c ../lib/console.c ../lib/head.S
+
+microwatt.hex: microwatt.elf
+	$(POWERPC_CROSS_COMPILE)objcopy -O verilog $< $@
+	# to fix flash base address
+	sed -i 's/@F000/@0000/g' $@
+
+clean:
+	rm -f *.vvp *.vcd *.elf *.bin *.o *.vvp *.vcd *.log *.hex
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/microwatt/uart/mgmt_engine.c b/verilog/dv/caravel/microwatt/uart/mgmt_engine.c
new file mode 100644
index 0000000..dcc4596
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/uart/mgmt_engine.c
@@ -0,0 +1,22 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../include/microwatt_util.h"
+#include "../include/mgmt_engine_util.h"
+
+void main(void)
+{
+	mgmt_engine_io_setup(false, true);
+
+	// Take microwatt out of reset
+	reg_la2_data &= ~0x00000002;
+
+	while (reg_la0_data != LA_MICROWATT_START)
+		/* Do Nothing */ ;
+
+	// Signal to TB that microwatt is alive
+	reg_mprj_datal = GPIO1_MICROWATT_START;
+
+	while (1)
+		/* Do Nothing */;
+}
diff --git a/verilog/dv/caravel/microwatt/uart/microwatt.c b/verilog/dv/caravel/microwatt/uart/microwatt.c
new file mode 100644
index 0000000..81ad8be
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/uart/microwatt.c
@@ -0,0 +1,19 @@
+#include <stdint.h>
+
+#include "console.h"
+#include "microwatt_util.h"
+
+int main(void)
+{
+	console_init();
+
+	microwatt_alive();
+
+	/* Echo everything we receive back */
+	while (1) {
+		unsigned char c = getchar();
+		putchar(c);
+		if (c == 13) // if CR send LF
+			putchar(10);
+	}
+}
diff --git a/verilog/dv/caravel/microwatt/uart/uart_tb.v b/verilog/dv/caravel/microwatt/uart/uart_tb.v
new file mode 100644
index 0000000..309324a
--- /dev/null
+++ b/verilog/dv/caravel/microwatt/uart/uart_tb.v
@@ -0,0 +1,249 @@
+`default_nettype none
+/*
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *  Copyright (C) 2020  Anton Blanchard <anton@linux.ibm.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module tbuart_expect_seven # (
+	parameter baud_rate = 115200
+) (
+	input ser_rx
+);
+	reg [3:0] recv_state;
+	reg [2:0] recv_divcnt;
+	reg [7:0] recv_pattern;
+
+	reg clk;
+
+	initial begin
+		clk <= 1'b0;
+		recv_state <= 0;
+		recv_divcnt <= 0;
+		recv_pattern <= 0;
+	end
+
+	// Our simulation is in nanosecond steps and we want 5 clocks per bit,
+	// ie 10 clock transitions
+	always #(1000000000/baud_rate/10) clk <= (clk === 1'b0);
+
+	always @(posedge clk) begin
+		recv_divcnt <= recv_divcnt + 1;
+		case (recv_state)
+			0: begin
+				if (!ser_rx)
+					recv_state <= 1;
+				recv_divcnt <= 0;
+			end
+			1: begin
+				if (2*recv_divcnt > 3'd3) begin
+					recv_state <= 2;
+					recv_divcnt <= 0;
+				end
+			end
+			10: begin
+				if (recv_divcnt > 3'd3) begin
+					recv_state <= 0;
+					$display("Got %c from Microwatt", recv_pattern);
+					// Expecting 7 back
+					if (recv_pattern == 55) begin
+						$finish;
+					end else begin
+						$fatal;
+					end
+				end
+			end
+			default: begin
+				if (recv_divcnt > 3'd3) begin
+					recv_pattern <= {ser_rx, recv_pattern[7:1]};
+					recv_state <= recv_state + 1;
+					recv_divcnt <= 0;
+				end
+			end
+		endcase
+	end
+endmodule
+
+module uart_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+	reg power1, power2;
+	reg uart_rx;
+
+	wire gpio;
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire [37:0] mprj_io;
+	wire [1:0] checkbits;
+	wire uart_tx;
+	wire user_flash_csb;
+	wire user_flash_clk;
+	inout user_flash_io0;
+	inout user_flash_io1;
+
+	assign user_flash_csb = mprj_io[8];
+	assign user_flash_clk = mprj_io[9];
+	assign user_flash_io0 = mprj_io[10];
+	assign mprj_io[11] = user_flash_io1;
+
+	assign checkbits = mprj_io[17:16];
+	assign uart_tx = mprj_io[6];
+	assign mprj_io[5] = uart_rx;
+
+	// 50 MHz clock
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("uart.vcd");
+		$dumpvars(0, uart_tb);
+
+		$display("Microwatt UART rx -> tx test");
+
+		repeat (150) begin
+			repeat (10000) @(posedge clock);
+			// Diagnostic. . . interrupts output pattern.
+		end
+		$finish;
+	end
+
+	initial begin
+                RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#1000;
+		RSTB <= 1'b1;		// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+	initial begin
+		uart_rx <= 1'b1;
+
+		wait(checkbits == 2'h1);
+		$display("Management engine started");
+
+		wait(checkbits == 2'h2);
+		$display("Microwatt alive!");
+
+		// 115200 = 8680 ns per bit
+		$display("Writing 7 to Microwatt uart");
+		uart_rx <= 1'b0;
+		#8680
+		uart_rx <= 1'b1;
+		#8680
+		uart_rx <= 1'b1;
+		#8680
+		uart_rx <= 1'b1;
+		#8680
+		uart_rx <= 1'b0;
+		#8680
+		uart_rx <= 1'b1;
+		#8680
+		uart_rx <= 1'b1;
+		#8680
+		uart_rx <= 1'b0;
+		#8680
+		uart_rx <= 1'b0;
+		#8680
+		$display("Done. Waiting for Microwatt to send 7 back");
+		uart_rx <= 1'b1;
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("mgmt_engine.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+	spiflash #(
+		.FILENAME("microwatt.hex")
+	) spiflash_microwatt (
+		.csb(user_flash_csb),
+		.clk(user_flash_clk),
+		.io0(user_flash_io0),
+		.io1(user_flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+	tbuart_expect_seven #(
+		.baud_rate(115200)
+	) tbuart (
+		.ser_rx(uart_tx)
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/caravel/spiflash.v b/verilog/dv/caravel/spiflash.v
index 29dde43..76969fb 100644
--- a/verilog/dv/caravel/spiflash.v
+++ b/verilog/dv/caravel/spiflash.v
@@ -107,6 +107,7 @@
 	initial begin
 		$display("Reading %s",  FILENAME);
 		$readmemh(FILENAME, memory);
+		$display("%s loaded into memory", FILENAME);
 	end
 
 	task spi_action;
diff --git a/verilog/rtl/RAM_512x64.v b/verilog/rtl/RAM_512x64.v
index e019739..6a58b7c 100644
--- a/verilog/rtl/RAM_512x64.v
+++ b/verilog/rtl/RAM_512x64.v
@@ -1,13 +1,7 @@
 module RAM_512x64 (
 `ifdef USE_POWER_PINS
-    inout vdda1,	// User area 1 3.3V supply
-    inout vdda2,	// User area 2 3.3V supply
-    inout vssa1,	// User area 1 analog ground
-    inout vssa2,	// User area 2 analog ground
     inout vccd1,	// User area 1 1.8V supply
-    inout vccd2,	// User area 2 1.8v supply
     inout vssd1,	// User area 1 digital ground
-    inout vssd2,	// User area 2 digital ground
 `endif
     input           CLK,
     input   [7:0]   WE,
diff --git a/verilog/rtl/caravel_netlists.v b/verilog/rtl/caravel_netlists.v
index 66e6207..478263b 100644
--- a/verilog/rtl/caravel_netlists.v
+++ b/verilog/rtl/caravel_netlists.v
@@ -48,6 +48,13 @@
     `include "gl/mgmt_protect_hv.v"
 	`include "gl/gpio_control_block.v"
 	`include "gl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
+
+`default_nettype wire
+	`include "gl/icache.v"
+	`include "gl/dcache.v"
+	`include "gl/register_file.v"
+	`include "gl/multiply_4.v"
+	`include "gl/RAM_512x64.v"
 	`include "gl/user_project_wrapper.v"
     `include "gl/caravel.v"
 `else
@@ -70,6 +77,12 @@
     `include "mgmt_protect_hv.v"
 	`include "gpio_control_block.v"
     `include "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
+	`include "icache.v"
+	`include "dcache.v"
+	`include "register_file.v"
+	`include "multiply_4.v"
+	`include "RAM_512x64.v"
+	`include "microwatt.v"
 	`include "user_project_wrapper.v"
     `include "caravel.v"
 `endif
@@ -77,11 +90,6 @@
 `include "simple_por.v"
 `include "sram_1rw1r_32_256_8_sky130.v"
 
-/*------------------------------*/
-/* Include user project here	*/
-/*------------------------------*/
-`include "user_proj_example.v"
-
 // `ifdef USE_OPENRAM
 //     `include "sram_1rw1r_32_256_8_sky130.v"
 // `endif
diff --git a/verilog/rtl/dcache.v b/verilog/rtl/dcache.v
new file mode 100644
index 0000000..09d6f52
--- /dev/null
+++ b/verilog/rtl/dcache.v
@@ -0,0 +1,2299 @@
+/* Generated by Yosys 0.9+3743 (git sha1 UNKNOWN, clang 7.0.1-8+deb10u2 -fPIC -Os) */
+
+module plru_2(clk, rst, acc, acc_en, lru);
+  wire _0_;
+  wire _1_;
+  wire _2_;
+  wire _3_;
+  input acc;
+  input acc_en;
+  input clk;
+  output lru;
+  input rst;
+  reg [1:0] tree;
+  assign _0_ = ~ acc;
+  assign _1_ = acc_en ? _0_ : tree[1];
+  assign _2_ = rst ? 1'h0 : tree[0];
+  assign _3_ = rst ? 1'h0 : _1_;
+  always @(posedge clk)
+    tree <= { _3_, _2_ };
+  assign lru = tree[1];
+endmodule
+
+module cache_ram_4_64_3f29546453678b855931c174a97d6c0894b8f546(clk, rd_en, rd_addr, wr_sel, wr_addr, wr_data, rd_data);
+  reg [63:0] _00_;
+  wire [127:0] _01_;
+  wire [7:0] _02_;
+  wire [127:0] _03_;
+  wire [7:0] _04_;
+  wire [127:0] _05_;
+  wire [7:0] _06_;
+  wire [127:0] _07_;
+  wire [7:0] _08_;
+  wire [127:0] _09_;
+  wire [7:0] _10_;
+  wire [127:0] _11_;
+  wire [7:0] _12_;
+  wire [127:0] _13_;
+  wire [7:0] _14_;
+  wire [127:0] _15_;
+  wire [7:0] _16_;
+  input clk;
+  input [3:0] rd_addr;
+  output [63:0] rd_data;
+  input rd_en;
+  input [3:0] wr_addr;
+  input [63:0] wr_data;
+  input [7:0] wr_sel;
+  reg [7:0] \$mem$\25511  [15:0];
+  reg [7:0] \$mem$\25512  [15:0];
+  reg [7:0] \$mem$\25513  [15:0];
+  reg [7:0] \$mem$\25514  [15:0];
+  reg [7:0] \$mem$\25515  [15:0];
+  reg [7:0] \$mem$\25516  [15:0];
+  reg [7:0] \$mem$\25517  [15:0];
+  reg [7:0] \$mem$\25518  [15:0];
+  (* ram_style = "block" *)
+  reg [7:0] \25511  [15:0];
+  reg [7:0] _17_;
+  always @(posedge clk) begin
+    if (rd_en) _17_ <= \25511 [rd_addr];
+    if (wr_sel[0]) \25511 [wr_addr] <= wr_data[7:0];
+  end
+  assign _02_ = _17_;
+  (* ram_style = "block" *)
+  reg [7:0] \25512  [15:0];
+  reg [7:0] _18_;
+  always @(posedge clk) begin
+    if (rd_en) _18_ <= \25512 [rd_addr];
+    if (wr_sel[1]) \25512 [wr_addr] <= wr_data[15:8];
+  end
+  assign _04_ = _18_;
+  (* ram_style = "block" *)
+  reg [7:0] \25513  [15:0];
+  reg [7:0] _19_;
+  always @(posedge clk) begin
+    if (rd_en) _19_ <= \25513 [rd_addr];
+    if (wr_sel[2]) \25513 [wr_addr] <= wr_data[23:16];
+  end
+  assign _06_ = _19_;
+  (* ram_style = "block" *)
+  reg [7:0] \25514  [15:0];
+  reg [7:0] _20_;
+  always @(posedge clk) begin
+    if (rd_en) _20_ <= \25514 [rd_addr];
+    if (wr_sel[3]) \25514 [wr_addr] <= wr_data[31:24];
+  end
+  assign _08_ = _20_;
+  (* ram_style = "block" *)
+  reg [7:0] \25515  [15:0];
+  reg [7:0] _21_;
+  always @(posedge clk) begin
+    if (rd_en) _21_ <= \25515 [rd_addr];
+    if (wr_sel[4]) \25515 [wr_addr] <= wr_data[39:32];
+  end
+  assign _10_ = _21_;
+  (* ram_style = "block" *)
+  reg [7:0] \25516  [15:0];
+  reg [7:0] _22_;
+  always @(posedge clk) begin
+    if (rd_en) _22_ <= \25516 [rd_addr];
+    if (wr_sel[5]) \25516 [wr_addr] <= wr_data[47:40];
+  end
+  assign _12_ = _22_;
+  (* ram_style = "block" *)
+  reg [7:0] \25517  [15:0];
+  reg [7:0] _23_;
+  always @(posedge clk) begin
+    if (rd_en) _23_ <= \25517 [rd_addr];
+    if (wr_sel[6]) \25517 [wr_addr] <= wr_data[55:48];
+  end
+  assign _14_ = _23_;
+  (* ram_style = "block" *)
+  reg [7:0] \25518  [15:0];
+  reg [7:0] _24_;
+  always @(posedge clk) begin
+    if (rd_en) _24_ <= \25518 [rd_addr];
+    if (wr_sel[7]) \25518 [wr_addr] <= wr_data[63:56];
+  end
+  assign _16_ = _24_;
+  always @(posedge clk)
+    _00_ <= { _16_, _14_, _12_, _10_, _08_, _06_, _04_, _02_ };
+  assign rd_data = _00_;
+endmodule
+
+module dcache(
+`ifdef USE_POWER_PINS
+	vccd1, vssd1,
+`endif
+	clk, rst, d_in, m_in, wishbone_in, d_out, m_out, stall_out, wishbone_out);
+`ifdef USE_POWER_PINS
+  inout vccd1;
+  inout vssd1;
+`endif
+  wire _000_;
+  wire _001_;
+  wire [146:0] _002_;
+  wire _003_;
+  wire _004_;
+  wire _005_;
+  wire [146:0] _006_;
+  wire _007_;
+  wire [146:0] _008_;
+  wire _009_;
+  wire _010_;
+  wire _011_;
+  wire _012_;
+  wire _013_;
+  wire [1:0] _014_;
+  wire _015_;
+  wire _016_;
+  wire _017_;
+  wire _018_;
+  wire _019_;
+  wire _020_;
+  wire _021_;
+  wire _022_;
+  wire _023_;
+  wire _024_;
+  wire _025_;
+  wire _026_;
+  wire _027_;
+  wire _028_;
+  wire _029_;
+  wire _030_;
+  wire [3:0] _031_;
+  wire _032_;
+  wire _033_;
+  wire _034_;
+  wire [3:0] _035_;
+  wire [3:0] _036_;
+  wire [3:0] _037_;
+  wire _038_;
+  wire _039_;
+  wire _040_;
+  wire _041_;
+  wire _042_;
+  wire _043_;
+  wire _044_;
+  wire _045_;
+  wire _046_;
+  wire _047_;
+  wire _048_;
+  wire _049_;
+  wire _050_;
+  wire _051_;
+  wire _052_;
+  wire _053_;
+  wire _054_;
+  wire _055_;
+  wire _056_;
+  wire _057_;
+  wire _058_;
+  wire _059_;
+  wire _060_;
+  wire _061_;
+  wire _062_;
+  wire _063_;
+  wire _064_;
+  wire _065_;
+  wire _066_;
+  wire _067_;
+  wire _068_;
+  wire _069_;
+  wire _070_;
+  wire _071_;
+  wire _072_;
+  wire _073_;
+  wire _074_;
+  wire _075_;
+  wire _076_;
+  wire _077_;
+  wire _078_;
+  wire _079_;
+  wire _080_;
+  wire _081_;
+  wire _082_;
+  wire _083_;
+  wire _084_;
+  wire _085_;
+  wire _086_;
+  wire _087_;
+  wire _088_;
+  wire _089_;
+  wire _090_;
+  wire _091_;
+  wire _092_;
+  wire _093_;
+  wire _094_;
+  wire _095_;
+  wire _096_;
+  wire _097_;
+  wire _098_;
+  wire _099_;
+  wire _100_;
+  wire _101_;
+  wire _102_;
+  wire _103_;
+  wire _104_;
+  wire _105_;
+  wire _106_;
+  wire _107_;
+  wire _108_;
+  wire _109_;
+  wire [2:0] _110_;
+  wire _111_;
+  wire _112_;
+  wire _113_;
+  wire _114_;
+  wire _115_;
+  wire _116_;
+  wire _117_;
+  wire _118_;
+  wire _119_;
+  wire _120_;
+  wire _121_;
+  wire _122_;
+  wire _123_;
+  wire _124_;
+  wire _125_;
+  wire _126_;
+  wire _127_;
+  wire _128_;
+  wire _129_;
+  wire _130_;
+  wire _131_;
+  wire _132_;
+  wire _133_;
+  wire _134_;
+  wire _135_;
+  wire _136_;
+  wire [2:0] _137_;
+  wire [2:0] _138_;
+  wire [2:0] _139_;
+  wire _140_;
+  wire [3:0] _141_;
+  wire _142_;
+  wire _143_;
+  wire _144_;
+  wire _145_;
+  wire _146_;
+  wire _147_;
+  wire _148_;
+  wire _149_;
+  wire _150_;
+  wire [58:0] _151_;
+  wire _152_;
+  wire [57:0] _153_;
+  wire [58:0] _154_;
+  wire _155_;
+  wire [57:0] _156_;
+  wire [63:0] _157_;
+  wire _158_;
+  wire [7:0] _159_;
+  wire [7:0] _160_;
+  wire [7:0] _161_;
+  wire [7:0] _162_;
+  wire [7:0] _163_;
+  wire [7:0] _164_;
+  wire [7:0] _165_;
+  wire [7:0] _166_;
+  wire _167_;
+  wire _168_;
+  wire _169_;
+  wire [63:0] _170_;
+  wire _171_;
+  wire _172_;
+  wire _173_;
+  wire _174_;
+  wire _175_;
+  wire _176_;
+  wire _177_;
+  wire [63:0] _178_;
+  wire _179_;
+  wire _180_;
+  wire _181_;
+  wire _182_;
+  wire _183_;
+  wire _184_;
+  wire _185_;
+  wire _186_;
+  wire _187_;
+  wire _188_;
+  wire _189_;
+  wire _190_;
+  wire _191_;
+  wire _192_;
+  wire [1:0] _193_;
+  wire _194_;
+  wire _195_;
+  wire _196_;
+  reg _197_;
+  reg [6:0] _198_;
+  reg _199_;
+  reg [2:0] _200_;
+  wire [7:0] _201_;
+  wire [7:0] _202_;
+  wire [63:0] _203_;
+  wire [63:0] _204_;
+  wire _205_;
+  wire _206_;
+  wire _207_;
+  wire _208_;
+  wire _209_;
+  wire _210_;
+  wire _211_;
+  wire _212_;
+  wire _213_;
+  wire _214_;
+  wire _215_;
+  wire _216_;
+  wire _217_;
+  wire _218_;
+  wire _219_;
+  wire [63:0] _220_;
+  wire _221_;
+  wire _222_;
+  wire _223_;
+  wire [7:0] _224_;
+  wire _225_;
+  wire _226_;
+  wire _227_;
+  wire _228_;
+  wire _229_;
+  wire _230_;
+  wire _231_;
+  wire _232_;
+  wire _233_;
+  wire [135:0] _234_;
+  wire [2:0] _235_;
+  wire _236_;
+  wire _237_;
+  wire _238_;
+  wire _239_;
+  wire _240_;
+  wire _241_;
+  wire _242_;
+  wire _243_;
+  wire _244_;
+  wire _245_;
+  wire _246_;
+  wire _247_;
+  wire _248_;
+  wire _249_;
+  wire [1:0] _250_;
+  wire _251_;
+  wire _252_;
+  wire _253_;
+  wire [2:0] _254_;
+  wire _255_;
+  wire _256_;
+  wire _257_;
+  wire _258_;
+  wire _259_;
+  wire _260_;
+  wire _261_;
+  wire _262_;
+  wire _263_;
+  wire [1:0] _264_;
+  wire _265_;
+  wire _266_;
+  wire _267_;
+  wire _268_;
+  wire _269_;
+  wire _270_;
+  wire [2:0] _271_;
+  wire _272_;
+  wire _273_;
+  wire _274_;
+  wire _275_;
+  wire _276_;
+  wire _277_;
+  wire _278_;
+  wire _279_;
+  wire _280_;
+  wire _281_;
+  wire [2:0] _282_;
+  wire [31:0] _283_;
+  wire _284_;
+  wire _285_;
+  wire [2:0] _286_;
+  wire _287_;
+  wire _288_;
+  wire _289_;
+  wire _290_;
+  wire _291_;
+  wire _292_;
+  wire _293_;
+  wire _294_;
+  wire _295_;
+  wire _296_;
+  wire _297_;
+  wire _298_;
+  wire _299_;
+  wire [8:0] _300_;
+  wire _301_;
+  wire _302_;
+  wire _303_;
+  wire _304_;
+  wire _305_;
+  wire _306_;
+  wire [3:0] _307_;
+  wire [1:0] _308_;
+  wire _309_;
+  wire [2:0] _310_;
+  wire _311_;
+  wire _312_;
+  wire [10:0] _313_;
+  wire _314_;
+  wire _315_;
+  wire [3:0] _316_;
+  wire [7:0] _317_;
+  wire _318_;
+  wire _319_;
+  wire _320_;
+  wire _321_;
+  wire _322_;
+  wire [2:0] _323_;
+  wire [2:0] _324_;
+  wire [2:0] _325_;
+  wire [2:0] _326_;
+  wire _327_;
+  wire [6:0] _328_;
+  wire [71:0] _329_;
+  wire _330_;
+  wire _331_;
+  wire _332_;
+  wire _333_;
+  wire _334_;
+  wire _335_;
+  wire _336_;
+  wire _337_;
+  wire _338_;
+  wire _339_;
+  wire _340_;
+  wire _341_;
+  wire _342_;
+  wire _343_;
+  wire _344_;
+  wire _345_;
+  wire _346_;
+  wire [7:0] _347_;
+  wire _348_;
+  wire _349_;
+  wire _350_;
+  wire _351_;
+  wire _352_;
+  wire _353_;
+  wire _354_;
+  wire [1:0] _355_;
+  wire [1:0] _356_;
+  wire _357_;
+  wire [1:0] _358_;
+  wire _359_;
+  wire _360_;
+  wire _361_;
+  wire _362_;
+  wire _363_;
+  wire _364_;
+  wire _365_;
+  wire _366_;
+  wire [10:0] _367_;
+  wire _368_;
+  wire [1:0] _369_;
+  wire _370_;
+  wire _371_;
+  wire _372_;
+  wire [3:0] _373_;
+  wire _374_;
+  wire _375_;
+  wire _376_;
+  wire _377_;
+  wire _378_;
+  wire _379_;
+  wire [8:0] _380_;
+  wire [1:0] _381_;
+  wire _382_;
+  wire _383_;
+  wire _384_;
+  wire _385_;
+  wire [6:0] _386_;
+  wire [24:0] _387_;
+  wire [63:0] _388_;
+  wire [7:0] _389_;
+  wire _390_;
+  wire _391_;
+  wire _392_;
+  wire [48:0] _393_;
+  wire _394_;
+  wire [3:0] _395_;
+  wire _396_;
+  wire [2:0] _397_;
+  wire _398_;
+  wire _399_;
+  wire _400_;
+  wire _401_;
+  wire _402_;
+  wire _403_;
+  wire _404_;
+  wire _405_;
+  wire [2:0] _406_;
+  wire _407_;
+  wire _408_;
+  wire _409_;
+  wire _410_;
+  wire _411_;
+  wire _412_;
+  wire [133:0] _413_;
+  wire [133:0] _414_;
+  wire [3:0] _415_;
+  wire _416_;
+  wire [135:0] _417_;
+  wire _418_;
+  wire _419_;
+  wire [8:0] _420_;
+  wire [1:0] _421_;
+  wire [2:0] _422_;
+  wire [32:0] _423_;
+  wire [71:0] _424_;
+  wire [1:0] _425_;
+  wire [71:0] _426_;
+  wire _427_;
+  wire _428_;
+  wire [4:0] _429_;
+  wire [7:0] _430_;
+  wire _431_;
+  wire _432_;
+  wire _433_;
+  wire _434_;
+  reg _435_;
+  reg [135:0] _436_;
+  reg [335:0] _437_;
+  reg _438_;
+  wire [203:0] _439_;
+  wire [255:0] _440_;
+  wire [111:0] _441_;
+  wire [55:0] _442_;
+  wire [111:0] _443_;
+  wire [55:0] _444_;
+  wire [1:0] _445_;
+  wire [63:0] _446_;
+  wire _447_;
+  wire _448_;
+  wire _449_;
+  wire _450_;
+  wire _451_;
+  wire _452_;
+  wire _453_;
+  wire _454_;
+  wire _455_;
+  wire _456_;
+  wire _457_;
+  wire _458_;
+  wire [50:0] _459_;
+  wire [50:0] _460_;
+  wire _461_;
+  wire [63:0] _462_;
+  wire [63:0] _463_;
+  wire _464_;
+  wire _465_;
+  wire _466_;
+  wire _467_;
+  wire _468_;
+  wire _469_;
+  wire _470_;
+  wire _471_;
+  wire _472_;
+  wire _473_;
+  wire _474_;
+  wire _475_;
+  wire _476_;
+  wire _477_;
+  wire _478_;
+  wire _479_;
+  wire _480_;
+  wire _481_;
+  wire _482_;
+  wire _483_;
+  wire _484_;
+  wire _485_;
+  wire _486_;
+  wire [63:0] _487_;
+  wire _488_;
+  wire _489_;
+  wire _490_;
+  wire _491_;
+  wire _492_;
+  wire _493_;
+  wire _494_;
+  wire _495_;
+  wire _496_;
+  wire _497_;
+  wire _498_;
+  wire _499_;
+  wire _500_;
+  wire _501_;
+  wire _502_;
+  wire _503_;
+  wire _504_;
+  wire _505_;
+  wire _506_;
+  wire _507_;
+  wire _508_;
+  wire _509_;
+  wire _510_;
+  wire _511_;
+  wire _512_;
+  wire _513_;
+  wire _514_;
+  wire _515_;
+  wire _516_;
+  wire _517_;
+  wire _518_;
+  wire _519_;
+  wire _520_;
+  wire _521_;
+  wire _522_;
+  wire _523_;
+  wire _524_;
+  wire access_ok;
+  reg [3:0] cache_valids;
+  wire cancel_store;
+  wire clear_rsrv;
+  input clk;
+  input [142:0] d_in;
+  output [67:0] d_out;
+  reg [3:0] dtlb_valids;
+  wire [3:0] early_req_row;
+  input [131:0] m_in;
+  output [66:0] m_out;
+  wire \maybe_plrus.plrus:0.plru_acc_en ;
+  wire \maybe_plrus.plrus:0.plru_out ;
+  wire \maybe_plrus.plrus:1.plru_acc_en ;
+  wire \maybe_plrus.plrus:1.plru_out ;
+  wire \maybe_tlb_plrus.tlb_plrus:0.tlb_plru_acc_en ;
+  wire \maybe_tlb_plrus.tlb_plrus:0.tlb_plru_out ;
+  wire \maybe_tlb_plrus.tlb_plrus:1.tlb_plru_acc_en ;
+  wire \maybe_tlb_plrus.tlb_plrus:1.tlb_plru_out ;
+  wire [5:0] perm_attr;
+  wire perm_ok;
+  wire [63:0] pte;
+  reg [146:0] r0;
+  reg r0_full;
+  wire r0_stall;
+  wire r0_valid;
+  wire [55:0] ra;
+  wire \rams:0.do_write ;
+  wire [63:0] \rams:0.dout ;
+  wire [3:0] \rams:0.wr_addr ;
+  wire [63:0] \rams:0.wr_data ;
+  wire [7:0] \rams:0.wr_sel ;
+  wire [7:0] \rams:0.wr_sel_m ;
+  wire \rams:1.do_write ;
+  wire [63:0] \rams:1.dout ;
+  wire [3:0] \rams:1.wr_addr ;
+  wire [63:0] \rams:1.wr_data ;
+  wire [7:0] \rams:1.wr_sel ;
+  wire [7:0] \rams:1.wr_sel_m ;
+  wire rc_ok;
+  wire replace_way;
+  wire req_go;
+  wire req_hit_way;
+  wire [2:0] req_op;
+  wire req_same_tag;
+  reg [58:0] reservation;
+  input rst;
+  wire set_rsrv;
+  output stall_out;
+  wire tlb_hit;
+  wire tlb_hit_way;
+  wire [127:0] tlb_pte_way;
+  wire [101:0] tlb_tag_way;
+  reg [1:0] tlb_valid_way;
+  wire use_forward1_next;
+  wire use_forward2_next;
+  wire valid_ra;
+  input [65:0] wishbone_in;
+  output [106:0] wishbone_out;
+  reg [101:0] \$mem$\19357  [1:0];
+  reg [127:0] \$mem$\19360  [1:0];
+  reg [55:0] \$mem$\19363  [1:0];
+  reg [55:0] \$mem$\19364  [1:0];
+  (* ram_style = "distributed" *)
+  reg [101:0] \19357  [1:0];
+  reg [101:0] _531_;
+  always @(posedge clk) begin
+    if (_012_) _531_ <= \19357 [_011_];
+    if (_041_) \19357 [r0[19]] <= { _460_, _459_ };
+  end
+  assign tlb_tag_way = _531_;
+  (* ram_style = "distributed" *)
+  reg [127:0] \19360  [1:0];
+  reg [127:0] _532_;
+  always @(posedge clk) begin
+    if (_012_) _532_ <= \19360 [_011_];
+    if (_045_) \19360 [r0[19]] <= { _463_, _462_ };
+  end
+  assign tlb_pte_way = _532_;
+  (* ram_style = "distributed" *)
+  reg [55:0] \19363  [1:0];
+  reg [55:0] _533_;
+  always @(posedge clk) begin
+    _533_ <= \19363 [_049_];
+    if (_434_) \19363 [_437_[318]] <= { 7'h00, _437_[312:264] };
+  end
+  assign _442_ = _533_;
+  (* ram_style = "distributed" *)
+  reg [55:0] \19364  [1:0];
+  reg [55:0] _534_;
+  always @(posedge clk) begin
+    _534_ <= \19364 [_049_];
+    if (_433_) \19364 [_437_[318]] <= { 7'h00, _437_[312:264] };
+  end
+  assign _444_ = _534_;
+  assign _521_ = _110_[0] ? _437_[323] : _437_[322];
+  assign _522_ = _110_[0] ? _437_[327] : _437_[326];
+  assign _523_ = _110_[0] ? _437_[325] : _437_[324];
+  assign _524_ = _110_[0] ? _437_[329] : _437_[328];
+  assign _483_ = _110_[1] ? _523_ : _521_;
+  assign _484_ = _110_[1] ? _524_ : _522_;
+  assign _000_ = m_in[1] | m_in[3];
+  assign _001_ = ~ _000_;
+  assign _002_ = m_in[0] ? { 1'h1, m_in[3:1], 8'hff, m_in[131:4], 5'h10, _001_, 1'h1 } : { 4'h0, d_in };
+  assign _003_ = ~ _435_;
+  assign _004_ = ~ r0_full;
+  assign _005_ = _003_ | _004_;
+  assign _006_ = _005_ ? _002_ : r0;
+  assign _007_ = _005_ ? _002_[0] : r0_full;
+  assign _008_ = rst ? r0 : _006_;
+  assign _009_ = rst ? 1'h0 : _007_;
+  always @(posedge clk)
+    r0 <= _008_;
+  always @(posedge clk)
+    r0_full <= _009_;
+  assign r0_stall = r0_full & _435_;
+  assign _010_ = ~ _435_;
+  assign r0_valid = r0_full & _010_;
+  assign _011_ = m_in[0] ? m_in[16] : d_in[19];
+  assign _012_ = ~ r0_stall;
+  assign _013_ = 1'h1 - _011_;
+  assign _014_ = _012_ ? _445_ : tlb_valid_way;
+  always @(posedge clk)
+    tlb_valid_way <= _014_;
+  assign _015_ = { 31'h00000000, _198_[6] } == 32'd0;
+  assign \maybe_tlb_plrus.tlb_plrus:0.tlb_plru_acc_en  = _015_ ? _198_[4] : 1'h0;
+  assign _016_ = { 31'h00000000, _198_[6] } == 32'd1;
+  assign \maybe_tlb_plrus.tlb_plrus:1.tlb_plru_acc_en  = _016_ ? _198_[4] : 1'h0;
+  assign _017_ = tlb_tag_way[50:0] == r0[70:20];
+  assign _018_ = tlb_valid_way[0] & _017_;
+  assign _019_ = _018_ ? 1'h1 : 1'h0;
+  assign _020_ = tlb_tag_way[101:51] == r0[70:20];
+  assign _021_ = tlb_valid_way[1] & _020_;
+  assign tlb_hit_way = _021_ ? 1'h1 : 1'h0;
+  assign _022_ = _021_ ? 1'h1 : _019_;
+  assign _023_ = _022_ & r0_valid;
+  assign tlb_hit = _023_ & r0[5];
+  assign pte = tlb_hit ? _446_ : 64'h0000000000000000;
+  assign _024_ = ~ r0[5];
+  assign _025_ = r0_valid & _024_;
+  assign valid_ra = tlb_hit | _025_;
+  assign ra = tlb_hit ? { pte[55:12], r0[18:10], 3'h0 } : { r0[62:10], 3'h0 };
+  assign perm_attr = tlb_hit ? { pte[1], pte[2], pte[3], pte[5], pte[7], pte[8] } : 6'h3b;
+  assign _026_ = r0_valid & r0[143];
+  assign _027_ = r0_valid & r0[145];
+  assign _028_ = _026_ & r0[144];
+  assign _029_ = rst | _028_;
+  assign _030_ = 1'h1 - r0[19];
+  assign _031_ = tlb_hit ? { _456_, _455_, _454_, _453_ } : dtlb_valids;
+  assign _032_ = 1'h1 - r0[19];
+  assign _033_ = tlb_hit ? tlb_hit_way : _457_;
+  assign _034_ = 1'h1 - r0[19];
+  assign _035_ = _027_ ? { _473_, _472_, _471_, _470_ } : dtlb_valids;
+  assign _036_ = _026_ ? _031_ : _035_;
+  assign _037_ = _029_ ? 4'h0 : _036_;
+  always @(posedge clk)
+    dtlb_valids <= _037_;
+  assign _038_ = ~ _029_;
+  assign _039_ = ~ _026_;
+  assign _040_ = _038_ & _039_;
+  assign _041_ = _040_ & _027_;
+  assign _042_ = ~ _029_;
+  assign _043_ = ~ _026_;
+  assign _044_ = _042_ & _043_;
+  assign _045_ = _044_ & _027_;
+  assign _046_ = { 31'h00000000, _198_[2] } == 32'd0;
+  assign \maybe_plrus.plrus:0.plru_acc_en  = _046_ ? _198_[3] : 1'h0;
+  assign _047_ = { 31'h00000000, _198_[2] } == 32'd1;
+  assign \maybe_plrus.plrus:1.plru_acc_en  = _047_ ? _198_[3] : 1'h0;
+  assign _048_ = m_in[0] ? m_in[10] : d_in[13];
+  assign _049_ = r0_stall ? r0[13] : _048_;
+  assign _050_ = r0[143] | r0[145];
+  assign _051_ = ~ _050_;
+  assign _052_ = r0_valid & _051_;
+  assign _053_ = ~ _199_;
+  assign req_go = _052_ & _053_;
+  assign _054_ = 1'h1 - r0[13];
+  assign _055_ = req_go & _474_;
+  assign _056_ = _442_[48:0] == { tlb_pte_way[55:12], r0[18:14] };
+  assign _057_ = _055_ & _056_;
+  assign _058_ = _057_ & tlb_valid_way[0];
+  assign _059_ = _058_ ? 1'h1 : 1'h0;
+  assign _060_ = _058_ ? 1'h0 : 1'h0;
+  assign _061_ = 1'h1 - r0[13];
+  assign _062_ = req_go & _475_;
+  assign _063_ = _444_[48:0] == { tlb_pte_way[55:12], r0[18:14] };
+  assign _064_ = _062_ & _063_;
+  assign _065_ = _064_ & tlb_valid_way[0];
+  assign _066_ = _065_ ? 1'h1 : _059_;
+  assign _067_ = _065_ ? 1'h1 : _060_;
+  assign _068_ = { tlb_pte_way[55:12], r0[18:14] } == _437_[312:264];
+  assign _069_ = _068_ ? 1'h1 : 1'h0;
+  assign _070_ = 1'h1 - r0[13];
+  assign _071_ = req_go & _476_;
+  assign _072_ = _442_[48:0] == { tlb_pte_way[119:76], r0[18:14] };
+  assign _073_ = _071_ & _072_;
+  assign _074_ = _073_ & tlb_valid_way[1];
+  assign _075_ = _074_ ? 1'h1 : 1'h0;
+  assign _076_ = _074_ ? 1'h0 : 1'h0;
+  assign _077_ = 1'h1 - r0[13];
+  assign _078_ = req_go & _477_;
+  assign _079_ = _444_[48:0] == { tlb_pte_way[119:76], r0[18:14] };
+  assign _080_ = _078_ & _079_;
+  assign _081_ = _080_ & tlb_valid_way[1];
+  assign _082_ = _081_ ? 1'h1 : _075_;
+  assign _083_ = _081_ ? 1'h1 : _076_;
+  assign _084_ = { tlb_pte_way[119:76], r0[18:14] } == _437_[312:264];
+  assign _085_ = _084_ ? 1'h1 : 1'h0;
+  assign _086_ = 1'h1 - tlb_hit_way;
+  assign _087_ = tlb_hit ? _478_ : 1'h0;
+  assign _088_ = tlb_hit ? _479_ : 1'h0;
+  assign _089_ = tlb_hit ? _480_ : 1'h0;
+  assign _090_ = 1'h1 - r0[13];
+  assign _091_ = req_go & _481_;
+  assign _092_ = _442_[48:0] == r0[62:14];
+  assign _093_ = _091_ & _092_;
+  assign _094_ = _093_ ? 1'h1 : 1'h0;
+  assign _095_ = 1'h1 - r0[13];
+  assign _096_ = req_go & _482_;
+  assign _097_ = _444_[48:0] == r0[62:14];
+  assign _098_ = _096_ & _097_;
+  assign _099_ = _098_ ? 1'h1 : _094_;
+  assign _100_ = _098_ ? 1'h1 : 1'h0;
+  assign _101_ = r0[62:14] == _437_[312:264];
+  assign _102_ = _101_ ? 1'h1 : 1'h0;
+  assign _103_ = r0[5] ? _087_ : _099_;
+  assign _104_ = r0[5] ? _088_ : _100_;
+  assign req_same_tag = r0[5] ? _089_ : _102_;
+  assign _105_ = _437_[152:151] == 2'h1;
+  assign _106_ = { 31'h00000000, r0[13] } == { 31'h00000000, _437_[318] };
+  assign _107_ = _105_ & _106_;
+  assign _108_ = _107_ & req_same_tag;
+  assign _109_ = ~ r0[1];
+  assign _110_ = 3'h7 - r0[12:10];
+  assign _111_ = _109_ | _485_;
+  assign _112_ = _108_ ? _111_ : _103_;
+  assign req_hit_way = _108_ ? replace_way : _104_;
+  assign _113_ = { 28'h0000000, _436_[11:8] } == { 28'h0000000, r0[13:10] };
+  assign _114_ = { 31'h00000000, _436_[133] } == { 31'h00000000, req_hit_way };
+  assign _115_ = _113_ & _114_;
+  assign use_forward1_next = _115_ ? _437_[154] : 1'h0;
+  assign _116_ = { 28'h0000000, _437_[141:138] } == { 28'h0000000, r0[13:10] };
+  assign _117_ = { 31'h00000000, _437_[137] } == { 31'h00000000, req_hit_way };
+  assign _118_ = _116_ & _117_;
+  assign use_forward2_next = _118_ ? _437_[136] : 1'h0;
+  assign _119_ = 1'h1 - _437_[318];
+  assign replace_way = _437_[155] ? _486_ : _437_[313];
+  assign _120_ = r0[1] | perm_attr[1];
+  assign rc_ok = perm_attr[0] & _120_;
+  assign _121_ = r0[6] & r0[0];
+  assign _122_ = ~ perm_attr[3];
+  assign _123_ = _121_ | _122_;
+  assign _124_ = r0[1] & perm_attr[4];
+  assign _125_ = perm_attr[5] | _124_;
+  assign perm_ok = _123_ & _125_;
+  assign _126_ = valid_ra & perm_ok;
+  assign access_ok = _126_ & rc_ok;
+  assign _127_ = r0[3] | perm_attr[2];
+  assign _128_ = ~ access_ok;
+  assign _129_ = { r0[1], _127_, _112_ } == 3'h5;
+  assign _130_ = { r0[1], _127_, _112_ } == 3'h4;
+  assign _131_ = { r0[1], _127_, _112_ } == 3'h6;
+  assign _132_ = { r0[1], _127_, _112_ } == 3'h1;
+  assign _133_ = { r0[1], _127_, _112_ } == 3'h0;
+  assign _134_ = { r0[1], _127_, _112_ } == 3'h2;
+  assign _135_ = { r0[1], _127_, _112_ } == 3'h3;
+  assign _136_ = { r0[1], _127_, _112_ } == 3'h7;
+  function [2:0] \18202 ;
+    input [2:0] a;
+    input [23:0] b;
+    input [7:0] s;
+    (* parallel_case *)
+    casez (s)
+      8'b???????1:
+        \18202  = b[2:0];
+      8'b??????1?:
+        \18202  = b[5:3];
+      8'b?????1??:
+        \18202  = b[8:6];
+      8'b????1???:
+        \18202  = b[11:9];
+      8'b???1????:
+        \18202  = b[14:12];
+      8'b??1?????:
+        \18202  = b[17:15];
+      8'b?1??????:
+        \18202  = b[20:18];
+      8'b1???????:
+        \18202  = b[23:21];
+      default:
+        \18202  = a;
+    endcase
+  endfunction
+  assign _137_ = \18202 (3'h0, 24'h27fd63, { _136_, _135_, _134_, _133_, _132_, _131_, _130_, _129_ });
+  assign _138_ = cancel_store ? 3'h2 : _137_;
+  assign _139_ = _128_ ? 3'h1 : _138_;
+  assign req_op = req_go ? _139_ : 3'h0;
+  assign _140_ = ~ r0_stall;
+  assign _141_ = m_in[0] ? m_in[10:7] : d_in[13:10];
+  assign early_req_row = _140_ ? _141_ : r0[13:10];
+  assign _142_ = r0_valid & r0[4];
+  assign _143_ = ~ reservation[0];
+  assign _144_ = r0[70:13] != reservation[58:1];
+  assign _145_ = _143_ | _144_;
+  assign _146_ = _145_ ? 1'h1 : 1'h0;
+  assign _147_ = r0[1] ? 1'h0 : _146_;
+  assign _148_ = r0[1] ? 1'h1 : 1'h0;
+  assign _149_ = r0[1] ? 1'h0 : 1'h1;
+  assign cancel_store = _142_ ? _147_ : 1'h0;
+  assign set_rsrv = _142_ ? _148_ : 1'h0;
+  assign clear_rsrv = _142_ ? _149_ : 1'h0;
+  assign _150_ = r0_valid & access_ok;
+  assign _151_ = set_rsrv ? { r0[70:13], 1'h1 } : reservation;
+  assign _152_ = clear_rsrv ? 1'h0 : _151_[0];
+  assign _153_ = clear_rsrv ? reservation[58:1] : _151_[58:1];
+  assign _154_ = _150_ ? { _153_, _152_ } : reservation;
+  assign _155_ = rst ? 1'h0 : _154_[0];
+  assign _156_ = rst ? reservation[58:1] : _154_[58:1];
+  always @(posedge clk)
+    reservation <= { _156_, _155_ };
+  assign _157_ = _437_[142] ? _437_[63:0] : _437_[127:64];
+  assign _158_ = 1'h1 - _198_[0];
+  assign _159_ = _437_[143] ? _157_[7:0] : _487_[7:0];
+  assign _160_ = _437_[144] ? _157_[15:8] : _487_[15:8];
+  assign _161_ = _437_[145] ? _157_[23:16] : _487_[23:16];
+  assign _162_ = _437_[146] ? _157_[31:24] : _487_[31:24];
+  assign _163_ = _437_[147] ? _157_[39:32] : _487_[39:32];
+  assign _164_ = _437_[148] ? _157_[47:40] : _487_[47:40];
+  assign _165_ = _437_[149] ? _157_[55:48] : _487_[55:48];
+  assign _166_ = _437_[150] ? _157_[63:56] : _487_[63:56];
+  assign _167_ = ~ _200_[2];
+  assign _168_ = 32'd0 == { 31'h00000000, _436_[133] };
+  assign _169_ = _168_ ? 1'h1 : 1'h0;
+  assign _170_ = _437_[153] ? 64'h0000000000000000 : wishbone_in[63:0];
+  assign _171_ = _437_[152:151] == 2'h1;
+  assign _172_ = _171_ & wishbone_in[64];
+  assign _173_ = { 31'h00000000, replace_way } == 32'd0;
+  assign _174_ = _172_ & _173_;
+  assign _175_ = _174_ ? 1'h1 : 1'h0;
+  assign \rams:0.do_write  = _437_[154] ? _169_ : _175_;
+  assign \rams:0.wr_addr  = _437_[154] ? _436_[11:8] : _437_[317:314];
+  assign \rams:0.wr_data  = _437_[154] ? _436_[124:61] : _170_;
+  assign \rams:0.wr_sel  = _437_[154] ? _436_[132:125] : 8'hff;
+  assign \rams:0.wr_sel_m  = \rams:0.do_write  ? \rams:0.wr_sel  : 8'h00;
+  assign _176_ = 32'd1 == { 31'h00000000, _436_[133] };
+  assign _177_ = _176_ ? 1'h1 : 1'h0;
+  assign _178_ = _437_[153] ? 64'h0000000000000000 : wishbone_in[63:0];
+  assign _179_ = _437_[152:151] == 2'h1;
+  assign _180_ = _179_ & wishbone_in[64];
+  assign _181_ = { 31'h00000000, replace_way } == 32'd1;
+  assign _182_ = _180_ & _181_;
+  assign _183_ = _182_ ? 1'h1 : 1'h0;
+  assign \rams:1.do_write  = _437_[154] ? _177_ : _183_;
+  assign \rams:1.wr_addr  = _437_[154] ? _436_[11:8] : _437_[317:314];
+  assign \rams:1.wr_data  = _437_[154] ? _436_[124:61] : _178_;
+  assign \rams:1.wr_sel  = _437_[154] ? _436_[132:125] : 8'hff;
+  assign \rams:1.wr_sel_m  = \rams:1.do_write  ? \rams:1.wr_sel  : 8'h00;
+  assign _184_ = req_op == 3'h3;
+  assign _185_ = _184_ ? 1'h1 : 1'h0;
+  assign _186_ = req_op == 3'h3;
+  assign _187_ = req_op == 3'h6;
+  assign _188_ = _186_ | _187_;
+  assign _189_ = _188_ ? 1'h1 : 1'h0;
+  assign _190_ = req_op == 3'h1;
+  assign _191_ = ~ r0[146];
+  assign _192_ = _190_ ? _191_ : 1'h0;
+  assign _193_ = _190_ ? { access_ok, r0[146] } : 2'h0;
+  assign _194_ = req_op == 3'h2;
+  assign _195_ = _194_ ? 1'h1 : 1'h0;
+  assign _196_ = r0_valid ? r0[146] : _197_;
+  always @(posedge clk)
+    _197_ <= _196_;
+  always @(posedge clk)
+    _198_ <= { r0[19], tlb_hit_way, tlb_hit, _189_, r0[13], _185_, req_hit_way };
+  always @(posedge clk)
+    _199_ <= _192_;
+  always @(posedge clk)
+    _200_ <= { _195_, _193_ };
+  assign _201_ = use_forward2_next ? _437_[135:128] : 8'h00;
+  assign _202_ = use_forward1_next ? _436_[132:125] : _201_;
+  assign _203_ = _437_[153] ? 64'h0000000000000000 : wishbone_in[63:0];
+  assign _204_ = _437_[154] ? _436_[124:61] : _203_;
+  assign _205_ = r0[143] | r0[145];
+  assign _206_ = r0_valid & _205_;
+  assign _207_ = req_op == 3'h3;
+  assign _208_ = req_op == 3'h2;
+  assign _209_ = _207_ | _208_;
+  assign _210_ = ~ r0[146];
+  assign _211_ = _213_ ? 1'h1 : 1'h0;
+  assign _212_ = _210_ ? _206_ : 1'h1;
+  assign _213_ = _209_ & _210_;
+  assign _214_ = _209_ ? _212_ : _206_;
+  assign _215_ = 32'd0 == { 31'h00000000, replace_way };
+  assign _216_ = 32'd1 == { 31'h00000000, replace_way };
+  assign _217_ = _437_[155] ? 1'h0 : _437_[155];
+  assign _218_ = _437_[155] ? replace_way : _437_[313];
+  assign _219_ = ~ r0[2];
+  assign _220_ = _219_ ? r0[134:71] : 64'h0000000000000000;
+  assign _221_ = ~ r0[3];
+  assign _222_ = r0[1] & _221_;
+  assign _223_ = r0[2] | _222_;
+  assign _224_ = _223_ ? 8'hff : r0[142:135];
+  assign _225_ = req_op == 3'h4;
+  assign _226_ = req_op == 3'h5;
+  assign _227_ = _225_ | _226_;
+  assign _228_ = req_op == 3'h7;
+  assign _229_ = _227_ | _228_;
+  assign _230_ = req_op == 3'h6;
+  assign _231_ = _229_ | _230_;
+  assign _232_ = _231_ ? 1'h1 : _435_;
+  assign _233_ = _435_ ? _435_ : _232_;
+  assign _234_ = _435_ ? _436_ : { r0[146], req_same_tag, req_hit_way, _224_, _220_, ra, r0[2], req_go, req_op };
+  assign _235_ = _234_[10:8] - 3'h1;
+  assign _236_ = _234_[2:0] == 3'h6;
+  assign _237_ = _236_ ? _234_[133] : _218_;
+  assign _238_ = _234_[2:0] == 3'h3;
+  assign _239_ = _234_[2:0] == 3'h4;
+  assign _240_ = _234_[2:0] == 3'h5;
+  assign _241_ = ~ _234_[4];
+  assign _242_ = ~ _234_[135];
+  assign _243_ = _255_ ? 1'h1 : _211_;
+  assign _244_ = _242_ ? _214_ : 1'h1;
+  assign _245_ = _234_[2:0] == 3'h6;
+  assign _246_ = _251_ ? 1'h1 : 1'h0;
+  assign _247_ = _234_[2:0] == 3'h7;
+  assign _248_ = _247_ ? 1'h1 : _217_;
+  assign _249_ = _241_ ? 1'h0 : _233_;
+  assign _250_ = _241_ ? 2'h2 : 2'h1;
+  assign _251_ = _241_ & _245_;
+  assign _252_ = _241_ ? _217_ : _248_;
+  assign _253_ = _241_ ? 1'h1 : 1'h0;
+  assign _254_ = _241_ ? 3'h1 : _437_[332:330];
+  assign _255_ = _241_ & _242_;
+  assign _256_ = _241_ ? _244_ : _214_;
+  assign _257_ = _234_[2:0] == 3'h6;
+  assign _258_ = _234_[2:0] == 3'h7;
+  assign _259_ = _257_ | _258_;
+  assign _260_ = _234_[2:0] == 3'h0;
+  assign _261_ = _234_[2:0] == 3'h1;
+  assign _262_ = _234_[2:0] == 3'h2;
+  function [0:0] \18809 ;
+    input [0:0] a;
+    input [6:0] b;
+    input [6:0] s;
+    (* parallel_case *)
+    casez (s)
+      7'b??????1:
+        \18809  = b[0:0];
+      7'b?????1?:
+        \18809  = b[1:1];
+      7'b????1??:
+        \18809  = b[2:2];
+      7'b???1???:
+        \18809  = b[3:3];
+      7'b??1????:
+        \18809  = b[4:4];
+      7'b?1?????:
+        \18809  = b[5:5];
+      7'b1??????:
+        \18809  = b[6:6];
+      default:
+        \18809  = a;
+    endcase
+  endfunction
+  assign _263_ = \18809 (1'hx, { _233_, _233_, _233_, _249_, _233_, _233_, _233_ }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+  function [1:0] \18812 ;
+    input [1:0] a;
+    input [13:0] b;
+    input [6:0] s;
+    (* parallel_case *)
+    casez (s)
+      7'b??????1:
+        \18812  = b[1:0];
+      7'b?????1?:
+        \18812  = b[3:2];
+      7'b????1??:
+        \18812  = b[5:4];
+      7'b???1???:
+        \18812  = b[7:6];
+      7'b??1????:
+        \18812  = b[9:8];
+      7'b?1?????:
+        \18812  = b[11:10];
+      7'b1??????:
+        \18812  = b[13:12];
+      default:
+        \18812  = a;
+    endcase
+  endfunction
+  assign _264_ = \18812 (2'hx, { _437_[152:151], _437_[152:151], _437_[152:151], _250_, 4'hd, _437_[152:151] }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+  function [0:0] \18814 ;
+    input [0:0] a;
+    input [6:0] b;
+    input [6:0] s;
+    (* parallel_case *)
+    casez (s)
+      7'b??????1:
+        \18814  = b[0:0];
+      7'b?????1?:
+        \18814  = b[1:1];
+      7'b????1??:
+        \18814  = b[2:2];
+      7'b???1???:
+        \18814  = b[3:3];
+      7'b??1????:
+        \18814  = b[4:4];
+      7'b?1?????:
+        \18814  = b[5:5];
+      7'b1??????:
+        \18814  = b[6:6];
+      default:
+        \18814  = a;
+    endcase
+  endfunction
+  assign _265_ = \18814 (1'hx, { 3'h0, _246_, 3'h0 }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+  function [0:0] \18816 ;
+    input [0:0] a;
+    input [6:0] b;
+    input [6:0] s;
+    (* parallel_case *)
+    casez (s)
+      7'b??????1:
+        \18816  = b[0:0];
+      7'b?????1?:
+        \18816  = b[1:1];
+      7'b????1??:
+        \18816  = b[2:2];
+      7'b???1???:
+        \18816  = b[3:3];
+      7'b??1????:
+        \18816  = b[4:4];
+      7'b?1?????:
+        \18816  = b[5:5];
+      7'b1??????:
+        \18816  = b[6:6];
+      default:
+        \18816  = a;
+    endcase
+  endfunction
+  assign _266_ = \18816 (1'hx, { _217_, _217_, _217_, _252_, _217_, 1'h1, _217_ }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+  function [0:0] \18818 ;
+    input [0:0] a;
+    input [6:0] b;
+    input [6:0] s;
+    (* parallel_case *)
+    casez (s)
+      7'b??????1:
+        \18818  = b[0:0];
+      7'b?????1?:
+        \18818  = b[1:1];
+      7'b????1??:
+        \18818  = b[2:2];
+      7'b???1???:
+        \18818  = b[3:3];
+      7'b??1????:
+        \18818  = b[4:4];
+      7'b?1?????:
+        \18818  = b[5:5];
+      7'b1??????:
+        \18818  = b[6:6];
+      default:
+        \18818  = a;
+    endcase
+  endfunction
+  assign _267_ = \18818 (1'hx, { 3'h0, _253_, 3'h0 }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+  function [0:0] \18821 ;
+    input [0:0] a;
+    input [6:0] b;
+    input [6:0] s;
+    (* parallel_case *)
+    casez (s)
+      7'b??????1:
+        \18821  = b[0:0];
+      7'b?????1?:
+        \18821  = b[1:1];
+      7'b????1??:
+        \18821  = b[2:2];
+      7'b???1???:
+        \18821  = b[3:3];
+      7'b??1????:
+        \18821  = b[4:4];
+      7'b?1?????:
+        \18821  = b[5:5];
+      7'b1??????:
+        \18821  = b[6:6];
+      default:
+        \18821  = a;
+    endcase
+  endfunction
+  assign _268_ = \18821 (1'hx, { _437_[261], _437_[261], _437_[261], 3'h7, _437_[261] }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+  function [0:0] \18824 ;
+    input [0:0] a;
+    input [6:0] b;
+    input [6:0] s;
+    (* parallel_case *)
+    casez (s)
+      7'b??????1:
+        \18824  = b[0:0];
+      7'b?????1?:
+        \18824  = b[1:1];
+      7'b????1??:
+        \18824  = b[2:2];
+      7'b???1???:
+        \18824  = b[3:3];
+      7'b??1????:
+        \18824  = b[4:4];
+      7'b?1?????:
+        \18824  = b[5:5];
+      7'b1??????:
+        \18824  = b[6:6];
+      default:
+        \18824  = a;
+    endcase
+  endfunction
+  assign _269_ = \18824 (1'hx, { _437_[262], _437_[262], _437_[262], 3'h7, _437_[262] }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+  function [0:0] \18827 ;
+    input [0:0] a;
+    input [6:0] b;
+    input [6:0] s;
+    (* parallel_case *)
+    casez (s)
+      7'b??????1:
+        \18827  = b[0:0];
+      7'b?????1?:
+        \18827  = b[1:1];
+      7'b????1??:
+        \18827  = b[2:2];
+      7'b???1???:
+        \18827  = b[3:3];
+      7'b??1????:
+        \18827  = b[4:4];
+      7'b?1?????:
+        \18827  = b[5:5];
+      7'b1??????:
+        \18827  = b[6:6];
+      default:
+        \18827  = a;
+    endcase
+  endfunction
+  assign _270_ = \18827 (1'hx, { _437_[263], _437_[263], _437_[263], 3'h4, _437_[263] }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+  function [2:0] \18830 ;
+    input [2:0] a;
+    input [20:0] b;
+    input [6:0] s;
+    (* parallel_case *)
+    casez (s)
+      7'b??????1:
+        \18830  = b[2:0];
+      7'b?????1?:
+        \18830  = b[5:3];
+      7'b????1??:
+        \18830  = b[8:6];
+      7'b???1???:
+        \18830  = b[11:9];
+      7'b??1????:
+        \18830  = b[14:12];
+      7'b?1?????:
+        \18830  = b[17:15];
+      7'b1??????:
+        \18830  = b[20:18];
+      default:
+        \18830  = a;
+    endcase
+  endfunction
+  assign _271_ = \18830 (3'hx, { _437_[332:330], _437_[332:330], _437_[332:330], _254_, _437_[332:330], _437_[332:330], _437_[332:330] }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+  function [0:0] \18832 ;
+    input [0:0] a;
+    input [6:0] b;
+    input [6:0] s;
+    (* parallel_case *)
+    casez (s)
+      7'b??????1:
+        \18832  = b[0:0];
+      7'b?????1?:
+        \18832  = b[1:1];
+      7'b????1??:
+        \18832  = b[2:2];
+      7'b???1???:
+        \18832  = b[3:3];
+      7'b??1????:
+        \18832  = b[4:4];
+      7'b?1?????:
+        \18832  = b[5:5];
+      7'b1??????:
+        \18832  = b[6:6];
+      default:
+        \18832  = a;
+    endcase
+  endfunction
+  assign _272_ = \18832 (1'hx, { _211_, _211_, _211_, _243_, _211_, _211_, _211_ }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+  function [0:0] \18834 ;
+    input [0:0] a;
+    input [6:0] b;
+    input [6:0] s;
+    (* parallel_case *)
+    casez (s)
+      7'b??????1:
+        \18834  = b[0:0];
+      7'b?????1?:
+        \18834  = b[1:1];
+      7'b????1??:
+        \18834  = b[2:2];
+      7'b???1???:
+        \18834  = b[3:3];
+      7'b??1????:
+        \18834  = b[4:4];
+      7'b?1?????:
+        \18834  = b[5:5];
+      7'b1??????:
+        \18834  = b[6:6];
+      default:
+        \18834  = a;
+    endcase
+  endfunction
+  assign _273_ = \18834 (1'hx, { _214_, _214_, _214_, _256_, _214_, _214_, _214_ }, { _262_, _261_, _260_, _259_, _240_, _239_, _238_ });
+  assign _274_ = _437_[152:151] == 2'h0;
+  assign _275_ = ~ _437_[262];
+  assign _276_ = ~ wishbone_in[65];
+  assign _277_ = ~ _275_;
+  assign _278_ = _276_ & _277_;
+  assign _279_ = _437_[162:160] == _437_[321:319];
+  assign _280_ = _284_ ? 1'h0 : _437_[262];
+  assign _281_ = _285_ ? 1'h1 : _275_;
+  assign _282_ = _437_[162:160] + 3'h1;
+  assign _283_ = _278_ ? { _437_[188:163], _282_, _437_[159:157] } : _437_[188:157];
+  assign _284_ = _278_ & _279_;
+  assign _285_ = _278_ & _279_;
+  assign _286_ = 3'h7 - _437_[316:314];
+  assign _287_ = _435_ & _436_[134];
+  assign _288_ = _437_[153] & _436_[4];
+  assign _289_ = ~ _437_[153];
+  assign _290_ = _436_[2:0] == 3'h4;
+  assign _291_ = _289_ & _290_;
+  assign _292_ = _288_ | _291_;
+  assign _293_ = _287_ & _292_;
+  assign _294_ = { 28'h0000000, _437_[317:314] } == { 28'h0000000, _436_[11:8] };
+  assign _295_ = _293_ & _294_;
+  assign _296_ = ~ _197_;
+  assign _297_ = _318_ ? 1'h1 : _211_;
+  assign _298_ = _296_ ? _214_ : 1'h1;
+  assign _299_ = _312_ ? 1'h0 : _233_;
+  assign _300_ = _295_ ? 9'h1ff : { _202_, use_forward1_next };
+  assign _301_ = _314_ ? 1'h1 : 1'h0;
+  assign _302_ = _295_ & _296_;
+  assign _303_ = _319_ ? _298_ : _214_;
+  assign _304_ = _437_[316:314] == _437_[321:319];
+  assign _305_ = _281_ & _304_;
+  assign _306_ = 1'h1 - _437_[318];
+  assign _307_ = _311_ ? { _520_, _519_, _518_, _517_ } : cache_valids;
+  assign _308_ = _305_ ? 2'h0 : _437_[152:151];
+  assign _309_ = _315_ ? 1'h0 : _437_[261];
+  assign _310_ = _437_[316:314] + 3'h1;
+  assign _311_ = wishbone_in[64] & _305_;
+  assign _312_ = wishbone_in[64] & _295_;
+  assign _313_ = wishbone_in[64] ? { _308_, _300_ } : { _437_[152:151], _202_, use_forward1_next };
+  assign _314_ = wishbone_in[64] & _295_;
+  assign _315_ = wishbone_in[64] & _305_;
+  assign _316_ = wishbone_in[64] ? { _437_[317], _310_ } : _437_[317:314];
+  assign _317_ = wishbone_in[64] ? { _510_, _509_, _508_, _507_, _506_, _505_, _504_, _503_ } : _437_[329:322];
+  assign _318_ = wishbone_in[64] & _302_;
+  assign _319_ = wishbone_in[64] & _295_;
+  assign _320_ = _437_[152:151] == 2'h1;
+  assign _321_ = ~ _437_[262];
+  assign _322_ = _437_[333] != _437_[334];
+  assign _323_ = _437_[332:330] + 3'h1;
+  assign _324_ = _437_[332:330] - 3'h1;
+  assign _325_ = _437_[333] ? _323_ : _324_;
+  assign _326_ = _322_ ? _325_ : _437_[332:330];
+  assign _327_ = ~ wishbone_in[65];
+  assign _328_ = _234_[3] ? _234_[11:5] : _437_[163:157];
+  assign _329_ = _348_ ? _234_[132:61] : _437_[260:189];
+  assign _330_ = _326_ < 3'h7;
+  assign _331_ = _330_ & _234_[134];
+  assign _332_ = _234_[2:0] == 3'h7;
+  assign _333_ = _234_[2:0] == 3'h6;
+  assign _334_ = _332_ | _333_;
+  assign _335_ = _331_ & _334_;
+  assign _336_ = _234_[2:0] == 3'h6;
+  assign _337_ = _346_ ? 1'h1 : 1'h0;
+  assign _338_ = _345_ ? 1'h0 : _233_;
+  assign _339_ = _335_ & _336_;
+  assign _340_ = _335_ ? 1'h1 : 1'h0;
+  assign _341_ = _335_ ? 1'h1 : 1'h0;
+  assign _342_ = _350_ ? 1'h1 : 1'h0;
+  assign _343_ = _351_ ? 1'h1 : _211_;
+  assign _344_ = _335_ ? 1'h0 : 1'h1;
+  assign _345_ = _327_ & _335_;
+  assign _346_ = _327_ & _339_;
+  assign _347_ = _327_ ? { _328_, _340_ } : { _437_[163:157], 1'h0 };
+  assign _348_ = _327_ & _234_[3];
+  assign _349_ = _327_ ? _341_ : _437_[262];
+  assign _350_ = _327_ & _335_;
+  assign _351_ = _327_ & _335_;
+  assign _352_ = _327_ ? _344_ : _321_;
+  assign _353_ = _326_ == 3'h1;
+  assign _354_ = _352_ & _353_;
+  assign _355_ = _357_ ? 2'h0 : _437_[152:151];
+  assign _356_ = _354_ ? 2'h0 : { _349_, _437_[261] };
+  assign _357_ = wishbone_in[64] & _354_;
+  assign _358_ = wishbone_in[64] ? _356_ : { _349_, _437_[261] };
+  assign _359_ = wishbone_in[64] ? 1'h1 : 1'h0;
+  assign _360_ = _437_[152:151] == 2'h2;
+  assign _361_ = ~ wishbone_in[65];
+  assign _362_ = _361_ ? 1'h0 : _437_[262];
+  assign _363_ = ~ _197_;
+  assign _364_ = _370_ ? 1'h1 : _211_;
+  assign _365_ = _363_ ? _214_ : 1'h1;
+  assign _366_ = wishbone_in[64] ? 1'h0 : _233_;
+  assign _367_ = wishbone_in[64] ? 11'h1ff : { _437_[152:151], _202_, use_forward1_next };
+  assign _368_ = wishbone_in[64] ? 1'h1 : 1'h0;
+  assign _369_ = wishbone_in[64] ? 2'h0 : { _362_, _437_[261] };
+  assign _370_ = wishbone_in[64] & _363_;
+  assign _371_ = wishbone_in[64] ? _365_ : _214_;
+  assign _372_ = _437_[152:151] == 2'h3;
+  function [3:0] \19137 ;
+    input [3:0] a;
+    input [15:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19137  = b[3:0];
+      4'b??1?:
+        \19137  = b[7:4];
+      4'b?1??:
+        \19137  = b[11:8];
+      4'b1???:
+        \19137  = b[15:12];
+      default:
+        \19137  = a;
+    endcase
+  endfunction
+  assign _373_ = \19137 (4'hx, { cache_valids, cache_valids, _307_, cache_valids }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19139 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19139  = b[0:0];
+      4'b??1?:
+        \19139  = b[1:1];
+      4'b?1??:
+        \19139  = b[2:2];
+      4'b1???:
+        \19139  = b[3:3];
+      default:
+        \19139  = a;
+    endcase
+  endfunction
+  assign _374_ = \19139 (1'hx, { _366_, _338_, _299_, _263_ }, { _372_, _360_, _320_, _274_ });
+  assign _375_ = _231_ ? req_same_tag : _436_[134];
+  assign _376_ = _435_ ? _436_[134] : _375_;
+  function [0:0] \19146 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19146  = b[0:0];
+      4'b??1?:
+        \19146  = b[1:1];
+      4'b?1??:
+        \19146  = b[2:2];
+      4'b1???:
+        \19146  = b[3:3];
+      default:
+        \19146  = a;
+    endcase
+  endfunction
+  assign _377_ = \19146 (1'hx, { _376_, _376_, _376_, 1'h1 }, { _372_, _360_, _320_, _274_ });
+  assign _378_ = _437_[154] ? 1'h1 : 1'h0;
+  function [0:0] \19151 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19151  = b[0:0];
+      4'b??1?:
+        \19151  = b[1:1];
+      4'b?1??:
+        \19151  = b[2:2];
+      4'b1???:
+        \19151  = b[3:3];
+      default:
+        \19151  = a;
+    endcase
+  endfunction
+  assign _379_ = \19151 (1'hx, { _378_, _378_, wishbone_in[64], _378_ }, { _372_, _360_, _320_, _274_ });
+  function [8:0] \19156 ;
+    input [8:0] a;
+    input [35:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19156  = b[8:0];
+      4'b??1?:
+        \19156  = b[17:9];
+      4'b?1??:
+        \19156  = b[26:18];
+      4'b1???:
+        \19156  = b[35:27];
+      default:
+        \19156  = a;
+    endcase
+  endfunction
+  assign _380_ = \19156 (9'hxxx, { _367_[8:0], _202_, use_forward1_next, _313_[8:0], _202_, use_forward1_next }, { _372_, _360_, _320_, _274_ });
+  function [1:0] \19160 ;
+    input [1:0] a;
+    input [7:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19160  = b[1:0];
+      4'b??1?:
+        \19160  = b[3:2];
+      4'b?1??:
+        \19160  = b[5:4];
+      4'b1???:
+        \19160  = b[7:6];
+      default:
+        \19160  = a;
+    endcase
+  endfunction
+  assign _381_ = \19160 (2'hx, { _367_[10:9], _355_, _313_[10:9], _264_ }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19163 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19163  = b[0:0];
+      4'b??1?:
+        \19163  = b[1:1];
+      4'b?1??:
+        \19163  = b[2:2];
+      4'b1???:
+        \19163  = b[3:3];
+      default:
+        \19163  = a;
+    endcase
+  endfunction
+  assign _382_ = \19163 (1'hx, { _437_[153], _437_[153], _437_[153], _234_[4] }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19165 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19165  = b[0:0];
+      4'b??1?:
+        \19165  = b[1:1];
+      4'b?1??:
+        \19165  = b[2:2];
+      4'b1???:
+        \19165  = b[3:3];
+      default:
+        \19165  = a;
+    endcase
+  endfunction
+  assign _383_ = \19165 (1'hx, { 1'h0, _337_, 1'h0, _265_ }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19167 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19167  = b[0:0];
+      4'b??1?:
+        \19167  = b[1:1];
+      4'b?1??:
+        \19167  = b[2:2];
+      4'b1???:
+        \19167  = b[3:3];
+      default:
+        \19167  = a;
+    endcase
+  endfunction
+  assign _384_ = \19167 (1'hx, { _217_, _217_, _217_, _266_ }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19170 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19170  = b[0:0];
+      4'b??1?:
+        \19170  = b[1:1];
+      4'b?1??:
+        \19170  = b[2:2];
+      4'b1???:
+        \19170  = b[3:3];
+      default:
+        \19170  = a;
+    endcase
+  endfunction
+  assign _385_ = \19170 (1'hx, { _368_, _347_[0], _301_, _267_ }, { _372_, _360_, _320_, _274_ });
+  function [6:0] \19176 ;
+    input [6:0] a;
+    input [27:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19176  = b[6:0];
+      4'b??1?:
+        \19176  = b[13:7];
+      4'b?1??:
+        \19176  = b[20:14];
+      4'b1???:
+        \19176  = b[27:21];
+      default:
+        \19176  = a;
+    endcase
+  endfunction
+  assign _386_ = \19176 (7'hxx, { _437_[163:157], _347_[7:1], _283_[6:0], _234_[11:5] }, { _372_, _360_, _320_, _274_ });
+  function [24:0] \19181 ;
+    input [24:0] a;
+    input [99:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19181  = b[24:0];
+      4'b??1?:
+        \19181  = b[49:25];
+      4'b?1??:
+        \19181  = b[74:50];
+      4'b1???:
+        \19181  = b[99:75];
+      default:
+        \19181  = a;
+    endcase
+  endfunction
+  assign _387_ = \19181 (25'hxxxxxxx, { _437_[188:164], _437_[188:164], _283_[31:7], _234_[36:12] }, { _372_, _360_, _320_, _274_ });
+  function [63:0] \19185 ;
+    input [63:0] a;
+    input [255:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19185  = b[63:0];
+      4'b??1?:
+        \19185  = b[127:64];
+      4'b?1??:
+        \19185  = b[191:128];
+      4'b1???:
+        \19185  = b[255:192];
+      default:
+        \19185  = a;
+    endcase
+  endfunction
+  assign _388_ = \19185 (64'hxxxxxxxxxxxxxxxx, { _437_[252:189], _329_[63:0], _437_[252:189], _234_[124:61] }, { _372_, _360_, _320_, _274_ });
+  function [7:0] \19189 ;
+    input [7:0] a;
+    input [31:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19189  = b[7:0];
+      4'b??1?:
+        \19189  = b[15:8];
+      4'b?1??:
+        \19189  = b[23:16];
+      4'b1???:
+        \19189  = b[31:24];
+      default:
+        \19189  = a;
+    endcase
+  endfunction
+  assign _389_ = \19189 (8'hxx, { _437_[260:253], _329_[71:64], _437_[260:253], _234_[132:125] }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19193 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19193  = b[0:0];
+      4'b??1?:
+        \19193  = b[1:1];
+      4'b?1??:
+        \19193  = b[2:2];
+      4'b1???:
+        \19193  = b[3:3];
+      default:
+        \19193  = a;
+    endcase
+  endfunction
+  assign _390_ = \19193 (1'hx, { _369_[0], _358_[0], _309_, _268_ }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19197 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19197  = b[0:0];
+      4'b??1?:
+        \19197  = b[1:1];
+      4'b?1??:
+        \19197  = b[2:2];
+      4'b1???:
+        \19197  = b[3:3];
+      default:
+        \19197  = a;
+    endcase
+  endfunction
+  assign _391_ = \19197 (1'hx, { _369_[1], _358_[1], _280_, _269_ }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19200 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19200  = b[0:0];
+      4'b??1?:
+        \19200  = b[1:1];
+      4'b?1??:
+        \19200  = b[2:2];
+      4'b1???:
+        \19200  = b[3:3];
+      default:
+        \19200  = a;
+    endcase
+  endfunction
+  assign _392_ = \19200 (1'hx, { _437_[263], _437_[263], _437_[263], _270_ }, { _372_, _360_, _320_, _274_ });
+  function [48:0] \19203 ;
+    input [48:0] a;
+    input [195:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19203  = b[48:0];
+      4'b??1?:
+        \19203  = b[97:49];
+      4'b?1??:
+        \19203  = b[146:98];
+      4'b1???:
+        \19203  = b[195:147];
+      default:
+        \19203  = a;
+    endcase
+  endfunction
+  assign _393_ = \19203 (49'hxxxxxxxxxxxxx, { _437_[312:264], _437_[312:264], _437_[312:264], _234_[60:12] }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19205 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19205  = b[0:0];
+      4'b??1?:
+        \19205  = b[1:1];
+      4'b?1??:
+        \19205  = b[2:2];
+      4'b1???:
+        \19205  = b[3:3];
+      default:
+        \19205  = a;
+    endcase
+  endfunction
+  assign _394_ = \19205 (1'hx, { _218_, _218_, _218_, _237_ }, { _372_, _360_, _320_, _274_ });
+  function [3:0] \19208 ;
+    input [3:0] a;
+    input [15:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19208  = b[3:0];
+      4'b??1?:
+        \19208  = b[7:4];
+      4'b?1??:
+        \19208  = b[11:8];
+      4'b1???:
+        \19208  = b[15:12];
+      default:
+        \19208  = a;
+    endcase
+  endfunction
+  assign _395_ = \19208 (4'hx, { _437_[317:314], _437_[317:314], _316_, _234_[11:8] }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19211 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19211  = b[0:0];
+      4'b??1?:
+        \19211  = b[1:1];
+      4'b?1??:
+        \19211  = b[2:2];
+      4'b1???:
+        \19211  = b[3:3];
+      default:
+        \19211  = a;
+    endcase
+  endfunction
+  assign _396_ = \19211 (1'hx, { _437_[318], _437_[318], _437_[318], _234_[11] }, { _372_, _360_, _320_, _274_ });
+  function [2:0] \19214 ;
+    input [2:0] a;
+    input [11:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19214  = b[2:0];
+      4'b??1?:
+        \19214  = b[5:3];
+      4'b?1??:
+        \19214  = b[8:6];
+      4'b1???:
+        \19214  = b[11:9];
+      default:
+        \19214  = a;
+    endcase
+  endfunction
+  assign _397_ = \19214 (3'hx, { _437_[321:319], _437_[321:319], _437_[321:319], _235_ }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19218 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19218  = b[0:0];
+      4'b??1?:
+        \19218  = b[1:1];
+      4'b?1??:
+        \19218  = b[2:2];
+      4'b1???:
+        \19218  = b[3:3];
+      default:
+        \19218  = a;
+    endcase
+  endfunction
+  assign _398_ = \19218 (1'hx, { _437_[322], _437_[322], _317_[0], 1'h0 }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19222 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19222  = b[0:0];
+      4'b??1?:
+        \19222  = b[1:1];
+      4'b?1??:
+        \19222  = b[2:2];
+      4'b1???:
+        \19222  = b[3:3];
+      default:
+        \19222  = a;
+    endcase
+  endfunction
+  assign _399_ = \19222 (1'hx, { _437_[323], _437_[323], _317_[1], 1'h0 }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19226 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19226  = b[0:0];
+      4'b??1?:
+        \19226  = b[1:1];
+      4'b?1??:
+        \19226  = b[2:2];
+      4'b1???:
+        \19226  = b[3:3];
+      default:
+        \19226  = a;
+    endcase
+  endfunction
+  assign _400_ = \19226 (1'hx, { _437_[324], _437_[324], _317_[2], 1'h0 }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19230 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19230  = b[0:0];
+      4'b??1?:
+        \19230  = b[1:1];
+      4'b?1??:
+        \19230  = b[2:2];
+      4'b1???:
+        \19230  = b[3:3];
+      default:
+        \19230  = a;
+    endcase
+  endfunction
+  assign _401_ = \19230 (1'hx, { _437_[325], _437_[325], _317_[3], 1'h0 }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19234 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19234  = b[0:0];
+      4'b??1?:
+        \19234  = b[1:1];
+      4'b?1??:
+        \19234  = b[2:2];
+      4'b1???:
+        \19234  = b[3:3];
+      default:
+        \19234  = a;
+    endcase
+  endfunction
+  assign _402_ = \19234 (1'hx, { _437_[326], _437_[326], _317_[4], 1'h0 }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19238 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19238  = b[0:0];
+      4'b??1?:
+        \19238  = b[1:1];
+      4'b?1??:
+        \19238  = b[2:2];
+      4'b1???:
+        \19238  = b[3:3];
+      default:
+        \19238  = a;
+    endcase
+  endfunction
+  assign _403_ = \19238 (1'hx, { _437_[327], _437_[327], _317_[5], 1'h0 }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19242 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19242  = b[0:0];
+      4'b??1?:
+        \19242  = b[1:1];
+      4'b?1??:
+        \19242  = b[2:2];
+      4'b1???:
+        \19242  = b[3:3];
+      default:
+        \19242  = a;
+    endcase
+  endfunction
+  assign _404_ = \19242 (1'hx, { _437_[328], _437_[328], _317_[6], 1'h0 }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19246 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19246  = b[0:0];
+      4'b??1?:
+        \19246  = b[1:1];
+      4'b?1??:
+        \19246  = b[2:2];
+      4'b1???:
+        \19246  = b[3:3];
+      default:
+        \19246  = a;
+    endcase
+  endfunction
+  assign _405_ = \19246 (1'hx, { _437_[329], _437_[329], _317_[7], 1'h0 }, { _372_, _360_, _320_, _274_ });
+  function [2:0] \19249 ;
+    input [2:0] a;
+    input [11:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19249  = b[2:0];
+      4'b??1?:
+        \19249  = b[5:3];
+      4'b?1??:
+        \19249  = b[8:6];
+      4'b1???:
+        \19249  = b[11:9];
+      default:
+        \19249  = a;
+    endcase
+  endfunction
+  assign _406_ = \19249 (3'hx, { _437_[332:330], _326_, _437_[332:330], _271_ }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19251 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19251  = b[0:0];
+      4'b??1?:
+        \19251  = b[1:1];
+      4'b?1??:
+        \19251  = b[2:2];
+      4'b1???:
+        \19251  = b[3:3];
+      default:
+        \19251  = a;
+    endcase
+  endfunction
+  assign _407_ = \19251 (1'hx, { 1'h0, _342_, 2'h0 }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19253 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19253  = b[0:0];
+      4'b??1?:
+        \19253  = b[1:1];
+      4'b?1??:
+        \19253  = b[2:2];
+      4'b1???:
+        \19253  = b[3:3];
+      default:
+        \19253  = a;
+    endcase
+  endfunction
+  assign _408_ = \19253 (1'hx, { 1'h0, _359_, 2'h0 }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19255 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19255  = b[0:0];
+      4'b??1?:
+        \19255  = b[1:1];
+      4'b?1??:
+        \19255  = b[2:2];
+      4'b1???:
+        \19255  = b[3:3];
+      default:
+        \19255  = a;
+    endcase
+  endfunction
+  assign _409_ = \19255 (1'hx, { _364_, _343_, _297_, _272_ }, { _372_, _360_, _320_, _274_ });
+  function [0:0] \19257 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \19257  = b[0:0];
+      4'b??1?:
+        \19257  = b[1:1];
+      4'b?1??:
+        \19257  = b[2:2];
+      4'b1???:
+        \19257  = b[3:3];
+      default:
+        \19257  = a;
+    endcase
+  endfunction
+  assign _410_ = \19257 (1'hx, { _371_, _214_, _303_, _273_ }, { _372_, _360_, _320_, _274_ });
+  assign _411_ = _231_ ? r0[146] : _436_[135];
+  assign _412_ = _435_ ? _436_[135] : _411_;
+  assign _413_ = _231_ ? { req_hit_way, _224_, _220_, ra, r0[2], req_go, req_op } : _436_[133:0];
+  assign _414_ = _435_ ? _436_[133:0] : _413_;
+  assign _415_ = rst ? 4'h0 : _373_;
+  assign _416_ = rst ? 1'h0 : _374_;
+  assign _417_ = rst ? _436_ : { _412_, _377_, _414_ };
+  assign _418_ = _437_[154] ? 1'h1 : 1'h0;
+  assign _419_ = rst ? _418_ : _379_;
+  assign _420_ = rst ? { _202_, use_forward1_next } : _380_;
+  assign _421_ = rst ? 2'h0 : _381_;
+  assign _422_ = rst ? _437_[155:153] : { _384_, _383_, _382_ };
+  assign _423_ = rst ? 33'h000000000 : { _387_, _386_, _385_ };
+  assign _424_ = rst ? _437_[260:189] : { _389_, _388_ };
+  assign _425_ = rst ? 2'h0 : { _391_, _390_ };
+  assign _426_ = rst ? _437_[334:263] : { _408_, _407_, _406_, _405_, _404_, _403_, _402_, _401_, _400_, _399_, _398_, _397_, _396_, _395_, _394_, _393_, _392_ };
+  assign _427_ = rst ? 1'h0 : _409_;
+  assign _428_ = rst ? 1'h0 : _410_;
+  assign _429_ = _437_[154] ? { _436_[11:8], _436_[133] } : { _437_[317:314], replace_way };
+  assign _430_ = _437_[154] ? _436_[132:125] : 8'hff;
+  assign _431_ = ~ rst;
+  assign _432_ = _431_ & _437_[155];
+  assign _433_ = _432_ & _216_;
+  assign _434_ = _432_ & _215_;
+  always @(posedge clk)
+    cache_valids <= _415_;
+  always @(posedge clk)
+    _435_ <= _416_;
+  always @(posedge clk)
+    _436_ <= _417_;
+  always @(posedge clk)
+    _437_ <= { _427_, _426_, _425_, _424_, _423_, _422_, _421_, _420_, _429_, _419_, _430_, _437_[63:0], _204_ };
+  always @(posedge clk)
+    _438_ <= _428_;
+  assign _445_ = _013_ ? dtlb_valids[3:2] : dtlb_valids[1:0];
+  assign _446_ = tlb_hit_way ? tlb_pte_way[127:64] : tlb_pte_way[63:0];
+  assign _447_ = ~ _030_;
+  assign _448_ = ~ tlb_hit_way;
+  assign _449_ = _447_ & _448_;
+  assign _450_ = _447_ & tlb_hit_way;
+  assign _451_ = _030_ & _448_;
+  assign _452_ = _030_ & tlb_hit_way;
+  assign _453_ = _449_ ? 1'h0 : dtlb_valids[0];
+  assign _454_ = _450_ ? 1'h0 : dtlb_valids[1];
+  assign _455_ = _451_ ? 1'h0 : dtlb_valids[2];
+  assign _456_ = _452_ ? 1'h0 : dtlb_valids[3];
+  assign _457_ = _032_ ? \maybe_tlb_plrus.tlb_plrus:0.tlb_plru_out  : \maybe_tlb_plrus.tlb_plrus:1.tlb_plru_out ;
+  assign _458_ = ~ _033_;
+  assign _459_ = _458_ ? r0[70:20] : tlb_tag_way[50:0];
+  assign _460_ = _033_ ? r0[70:20] : tlb_tag_way[101:51];
+  assign _461_ = ~ _033_;
+  assign _462_ = _461_ ? r0[134:71] : tlb_pte_way[63:0];
+  assign _463_ = _033_ ? r0[134:71] : tlb_pte_way[127:64];
+  assign _464_ = ~ _034_;
+  assign _465_ = ~ _033_;
+  assign _466_ = _464_ & _465_;
+  assign _467_ = _464_ & _033_;
+  assign _468_ = _034_ & _465_;
+  assign _469_ = _034_ & _033_;
+  assign _470_ = _466_ ? 1'h1 : dtlb_valids[0];
+  assign _471_ = _467_ ? 1'h1 : dtlb_valids[1];
+  assign _472_ = _468_ ? 1'h1 : dtlb_valids[2];
+  assign _473_ = _469_ ? 1'h1 : dtlb_valids[3];
+  assign _474_ = _054_ ? cache_valids[2] : cache_valids[0];
+  assign _475_ = _061_ ? cache_valids[3] : cache_valids[1];
+  assign _476_ = _070_ ? cache_valids[2] : cache_valids[0];
+  assign _477_ = _077_ ? cache_valids[3] : cache_valids[1];
+  assign _478_ = tlb_hit_way ? _082_ : _066_;
+  assign _479_ = _086_ ? _067_ : _083_;
+  assign _480_ = tlb_hit_way ? _085_ : _069_;
+  assign _481_ = _090_ ? cache_valids[2] : cache_valids[0];
+  assign _482_ = _095_ ? cache_valids[3] : cache_valids[1];
+  assign _485_ = _110_[2] ? _484_ : _483_;
+  assign _486_ = _119_ ? \maybe_plrus.plrus:0.plru_out  : \maybe_plrus.plrus:1.plru_out ;
+  assign _487_ = _158_ ? \rams:0.dout  : \rams:1.dout ;
+  assign _488_ = ~ _286_[2];
+  assign _489_ = ~ _286_[1];
+  assign _490_ = _488_ & _489_;
+  assign _491_ = _488_ & _286_[1];
+  assign _492_ = _286_[2] & _489_;
+  assign _493_ = _286_[2] & _286_[1];
+  assign _494_ = ~ _286_[0];
+  assign _495_ = _490_ & _494_;
+  assign _496_ = _490_ & _286_[0];
+  assign _497_ = _491_ & _494_;
+  assign _498_ = _491_ & _286_[0];
+  assign _499_ = _492_ & _494_;
+  assign _500_ = _492_ & _286_[0];
+  assign _501_ = _493_ & _494_;
+  assign _502_ = _493_ & _286_[0];
+  assign _503_ = _495_ ? 1'h1 : _437_[322];
+  assign _504_ = _496_ ? 1'h1 : _437_[323];
+  assign _505_ = _497_ ? 1'h1 : _437_[324];
+  assign _506_ = _498_ ? 1'h1 : _437_[325];
+  assign _507_ = _499_ ? 1'h1 : _437_[326];
+  assign _508_ = _500_ ? 1'h1 : _437_[327];
+  assign _509_ = _501_ ? 1'h1 : _437_[328];
+  assign _510_ = _502_ ? 1'h1 : _437_[329];
+  assign _511_ = ~ _306_;
+  assign _512_ = ~ _437_[313];
+  assign _513_ = _511_ & _512_;
+  assign _514_ = _511_ & _437_[313];
+  assign _515_ = _306_ & _512_;
+  assign _516_ = _306_ & _437_[313];
+  assign _517_ = _513_ ? 1'h1 : cache_valids[0];
+  assign _518_ = _514_ ? 1'h1 : cache_valids[1];
+  assign _519_ = _515_ ? 1'h1 : cache_valids[2];
+  assign _520_ = _516_ ? 1'h1 : cache_valids[3];
+  plru_2 \maybe_plrus.plrus:0.plru  (
+    .acc(_198_[0]),
+    .acc_en(\maybe_plrus.plrus:0.plru_acc_en ),
+    .clk(clk),
+    .lru(\maybe_plrus.plrus:0.plru_out ),
+    .rst(rst)
+  );
+  plru_2 \maybe_plrus.plrus:1.plru  (
+    .acc(_198_[0]),
+    .acc_en(\maybe_plrus.plrus:1.plru_acc_en ),
+    .clk(clk),
+    .lru(\maybe_plrus.plrus:1.plru_out ),
+    .rst(rst)
+  );
+  plru_2 \maybe_tlb_plrus.tlb_plrus:0.tlb_plru  (
+    .acc(_198_[5]),
+    .acc_en(\maybe_tlb_plrus.tlb_plrus:0.tlb_plru_acc_en ),
+    .clk(clk),
+    .lru(\maybe_tlb_plrus.tlb_plrus:0.tlb_plru_out ),
+    .rst(rst)
+  );
+  plru_2 \maybe_tlb_plrus.tlb_plrus:1.tlb_plru  (
+    .acc(_198_[5]),
+    .acc_en(\maybe_tlb_plrus.tlb_plrus:1.tlb_plru_acc_en ),
+    .clk(clk),
+    .lru(\maybe_tlb_plrus.tlb_plrus:1.tlb_plru_out ),
+    .rst(rst)
+  );
+  cache_ram_4_64_3f29546453678b855931c174a97d6c0894b8f546 \rams:0.way  (
+    .clk(clk),
+    .rd_addr(early_req_row),
+    .rd_data(\rams:0.dout ),
+    .rd_en(1'h1),
+    .wr_addr(\rams:0.wr_addr ),
+    .wr_data(\rams:0.wr_data ),
+    .wr_sel(\rams:0.wr_sel_m )
+  );
+  cache_ram_4_64_3f29546453678b855931c174a97d6c0894b8f546 \rams:1.way  (
+    .clk(clk),
+    .rd_addr(early_req_row),
+    .rd_data(\rams:1.dout ),
+    .rd_en(1'h1),
+    .wr_addr(\rams:1.wr_addr ),
+    .wr_data(\rams:1.wr_data ),
+    .wr_sel(\rams:1.wr_sel_m )
+  );
+  assign d_out = { _200_[1], _199_, _167_, _166_, _165_, _164_, _163_, _162_, _161_, _160_, _159_, _437_[335] };
+  assign m_out = { _166_, _165_, _164_, _163_, _162_, _161_, _160_, _159_, _200_[0], _438_, 1'h0 };
+  assign stall_out = r0_stall;
+  assign wishbone_out = _437_[263:157];
+endmodule
diff --git a/verilog/rtl/icache.v b/verilog/rtl/icache.v
new file mode 100644
index 0000000..bef804f
--- /dev/null
+++ b/verilog/rtl/icache.v
@@ -0,0 +1,1027 @@
+/* Generated by Yosys 0.9+3743 (git sha1 UNKNOWN, clang 7.0.1-8+deb10u2 -fPIC -Os) */
+
+module plru_1(clk, rst, acc, acc_en, lru);
+  wire _0_;
+  wire _1_;
+  wire _2_;
+  wire _3_;
+  input acc;
+  input acc_en;
+  input clk;
+  output lru;
+  input rst;
+  reg [1:0] tree;
+  assign _0_ = ~ acc;
+  assign _1_ = acc_en ? _0_ : tree[1];
+  assign _2_ = rst ? 1'h0 : tree[0];
+  assign _3_ = rst ? 1'h0 : _1_;
+  always @(posedge clk)
+    tree <= { _3_, _2_ };
+  assign lru = tree[1];
+endmodule
+
+module cache_ram_4_64_1489f923c4dca729178b3e3233458550d8dddf29(clk, rd_en, rd_addr, wr_sel, wr_addr, wr_data, rd_data);
+  wire [127:0] _00_;
+  wire [7:0] _01_;
+  wire [127:0] _02_;
+  wire [7:0] _03_;
+  wire [127:0] _04_;
+  wire [7:0] _05_;
+  wire [127:0] _06_;
+  wire [7:0] _07_;
+  wire [127:0] _08_;
+  wire [7:0] _09_;
+  wire [127:0] _10_;
+  wire [7:0] _11_;
+  wire [127:0] _12_;
+  wire [7:0] _13_;
+  wire [127:0] _14_;
+  wire [7:0] _15_;
+  input clk;
+  input [3:0] rd_addr;
+  output [63:0] rd_data;
+  input rd_en;
+  input [3:0] wr_addr;
+  input [63:0] wr_data;
+  input [7:0] wr_sel;
+  reg [7:0] \$mem$\20409  [15:0];
+  reg [7:0] \$mem$\20410  [15:0];
+  reg [7:0] \$mem$\20411  [15:0];
+  reg [7:0] \$mem$\20412  [15:0];
+  reg [7:0] \$mem$\20413  [15:0];
+  reg [7:0] \$mem$\20414  [15:0];
+  reg [7:0] \$mem$\20415  [15:0];
+  reg [7:0] \$mem$\20416  [15:0];
+  (* ram_style = "block" *)
+  reg [7:0] \20409  [15:0];
+  reg [7:0] _16_;
+  always @(posedge clk) begin
+    if (rd_en) _16_ <= \20409 [rd_addr];
+    if (wr_sel[0]) \20409 [wr_addr] <= wr_data[7:0];
+  end
+  assign _01_ = _16_;
+  (* ram_style = "block" *)
+  reg [7:0] \20410  [15:0];
+  reg [7:0] _17_;
+  always @(posedge clk) begin
+    if (rd_en) _17_ <= \20410 [rd_addr];
+    if (wr_sel[1]) \20410 [wr_addr] <= wr_data[15:8];
+  end
+  assign _03_ = _17_;
+  (* ram_style = "block" *)
+  reg [7:0] \20411  [15:0];
+  reg [7:0] _18_;
+  always @(posedge clk) begin
+    if (rd_en) _18_ <= \20411 [rd_addr];
+    if (wr_sel[2]) \20411 [wr_addr] <= wr_data[23:16];
+  end
+  assign _05_ = _18_;
+  (* ram_style = "block" *)
+  reg [7:0] \20412  [15:0];
+  reg [7:0] _19_;
+  always @(posedge clk) begin
+    if (rd_en) _19_ <= \20412 [rd_addr];
+    if (wr_sel[3]) \20412 [wr_addr] <= wr_data[31:24];
+  end
+  assign _07_ = _19_;
+  (* ram_style = "block" *)
+  reg [7:0] \20413  [15:0];
+  reg [7:0] _20_;
+  always @(posedge clk) begin
+    if (rd_en) _20_ <= \20413 [rd_addr];
+    if (wr_sel[4]) \20413 [wr_addr] <= wr_data[39:32];
+  end
+  assign _09_ = _20_;
+  (* ram_style = "block" *)
+  reg [7:0] \20414  [15:0];
+  reg [7:0] _21_;
+  always @(posedge clk) begin
+    if (rd_en) _21_ <= \20414 [rd_addr];
+    if (wr_sel[5]) \20414 [wr_addr] <= wr_data[47:40];
+  end
+  assign _11_ = _21_;
+  (* ram_style = "block" *)
+  reg [7:0] \20415  [15:0];
+  reg [7:0] _22_;
+  always @(posedge clk) begin
+    if (rd_en) _22_ <= \20415 [rd_addr];
+    if (wr_sel[6]) \20415 [wr_addr] <= wr_data[55:48];
+  end
+  assign _13_ = _22_;
+  (* ram_style = "block" *)
+  reg [7:0] \20416  [15:0];
+  reg [7:0] _23_;
+  always @(posedge clk) begin
+    if (rd_en) _23_ <= \20416 [rd_addr];
+    if (wr_sel[7]) \20416 [wr_addr] <= wr_data[63:56];
+  end
+  assign _15_ = _23_;
+  assign rd_data = { _15_, _13_, _11_, _09_, _07_, _05_, _03_, _01_ };
+endmodule
+
+module icache(
+`ifdef USE_POWER_PINS
+	vccd1, vssd1,
+`endif
+	clk, rst, i_in, m_in, stall_in, flush_in, inval_in, wishbone_in, i_out, stall_out, wishbone_out);
+`ifdef USE_POWER_PINS
+  inout vccd1;
+  inout vssd1;
+`endif
+
+  wire _000_;
+  wire _001_;
+  wire _002_;
+  wire _003_;
+  wire _004_;
+  wire _005_;
+  wire _006_;
+  wire _007_;
+  wire _008_;
+  wire _009_;
+  wire [1:0] _010_;
+  wire _011_;
+  wire [1:0] _012_;
+  wire _013_;
+  wire _014_;
+  wire _015_;
+  wire [1:0] _016_;
+  wire [1:0] _017_;
+  wire _018_;
+  wire _019_;
+  wire [1:0] _020_;
+  wire [1:0] _021_;
+  wire [3:0] _022_;
+  wire [3:0] _023_;
+  wire [3:0] _024_;
+  wire _025_;
+  wire _026_;
+  wire _027_;
+  wire _028_;
+  wire _029_;
+  wire _030_;
+  wire _031_;
+  wire _032_;
+  wire _033_;
+  wire _034_;
+  wire _035_;
+  wire _036_;
+  wire _037_;
+  wire _038_;
+  wire _039_;
+  wire _040_;
+  wire [2:0] _041_;
+  wire _042_;
+  wire _043_;
+  wire _044_;
+  wire _045_;
+  wire _046_;
+  wire _047_;
+  wire _048_;
+  wire _049_;
+  wire _050_;
+  wire _051_;
+  wire _052_;
+  wire _053_;
+  wire _054_;
+  wire [2:0] _055_;
+  wire _056_;
+  wire _057_;
+  wire _058_;
+  wire _059_;
+  wire _060_;
+  wire _061_;
+  wire _062_;
+  wire _063_;
+  wire _064_;
+  wire _065_;
+  wire _066_;
+  wire _067_;
+  wire _068_;
+  wire _069_;
+  wire _070_;
+  wire _071_;
+  wire _072_;
+  wire _073_;
+  wire _074_;
+  wire _075_;
+  wire _076_;
+  wire _077_;
+  wire _078_;
+  wire _079_;
+  wire _080_;
+  wire _081_;
+  wire [64:0] _082_;
+  reg [66:0] _083_;
+  wire [3:0] _084_;
+  wire _085_;
+  wire [2:0] _086_;
+  wire [33:0] _087_;
+  wire [1:0] _088_;
+  wire [58:0] _089_;
+  wire _090_;
+  wire _091_;
+  wire _092_;
+  wire _093_;
+  wire _094_;
+  wire _095_;
+  wire [199:0] _096_;
+  wire _097_;
+  wire _098_;
+  wire _099_;
+  wire [199:0] _100_;
+  wire [199:0] _101_;
+  wire [3:0] _102_;
+  wire [1:0] _103_;
+  wire _104_;
+  wire _105_;
+  wire _106_;
+  wire _107_;
+  wire _108_;
+  wire _109_;
+  wire _110_;
+  wire _111_;
+  wire [2:0] _112_;
+  wire [31:0] _113_;
+  wire _114_;
+  wire _115_;
+  wire [2:0] _116_;
+  wire _117_;
+  wire _118_;
+  wire _119_;
+  wire _120_;
+  wire _121_;
+  wire [3:0] _122_;
+  wire [1:0] _123_;
+  wire _124_;
+  wire [2:0] _125_;
+  wire _126_;
+  wire _127_;
+  wire _128_;
+  wire [3:0] _129_;
+  wire [7:0] _130_;
+  wire _131_;
+  wire _132_;
+  wire _133_;
+  wire [199:0] _134_;
+  wire [3:0] _135_;
+  wire [1:0] _136_;
+  wire [31:0] _137_;
+  wire _138_;
+  wire _139_;
+  wire _140_;
+  wire _141_;
+  wire [3:0] _142_;
+  wire [53:0] _143_;
+  wire _144_;
+  wire _145_;
+  wire _146_;
+  wire _147_;
+  wire _148_;
+  wire _149_;
+  wire _150_;
+  wire _151_;
+  wire [199:0] _152_;
+  wire [3:0] _153_;
+  wire [33:0] _154_;
+  wire [71:0] _155_;
+  wire [1:0] _156_;
+  wire _157_;
+  wire [67:0] _158_;
+  wire _159_;
+  wire _160_;
+  wire _161_;
+  wire _162_;
+  wire _163_;
+  wire _164_;
+  wire _165_;
+  wire _166_;
+  reg [177:0] _167_;
+  wire [255:0] _168_;
+  wire [63:0] _169_;
+  wire [199:0] _170_;
+  wire [49:0] _171_;
+  wire _172_;
+  wire _173_;
+  wire _174_;
+  wire _175_;
+  wire _176_;
+  wire _177_;
+  wire _178_;
+  wire _179_;
+  wire _180_;
+  wire _181_;
+  wire _182_;
+  wire _183_;
+  wire _184_;
+  wire _185_;
+  wire _186_;
+  wire _187_;
+  wire _188_;
+  wire _189_;
+  wire _190_;
+  wire _191_;
+  wire _192_;
+  wire _193_;
+  wire _194_;
+  wire _195_;
+  wire _196_;
+  wire [99:0] _197_;
+  wire _198_;
+  wire _199_;
+  wire _200_;
+  wire _201_;
+  wire [99:0] _202_;
+  wire _203_;
+  wire [63:0] _204_;
+  wire [31:0] _205_;
+  wire _206_;
+  wire _207_;
+  wire _208_;
+  wire _209_;
+  wire _210_;
+  wire _211_;
+  wire _212_;
+  wire _213_;
+  wire _214_;
+  wire _215_;
+  wire [99:0] _216_;
+  wire _217_;
+  wire [99:0] _218_;
+  wire [99:0] _219_;
+  wire [99:0] _220_;
+  wire _221_;
+  wire [99:0] _222_;
+  wire [99:0] _223_;
+  wire _224_;
+  wire _225_;
+  wire _226_;
+  wire _227_;
+  wire _228_;
+  wire _229_;
+  wire _230_;
+  wire _231_;
+  wire _232_;
+  wire _233_;
+  wire _234_;
+  wire _235_;
+  wire _236_;
+  wire _237_;
+  wire _238_;
+  wire _239_;
+  wire _240_;
+  wire _241_;
+  wire _242_;
+  wire _243_;
+  wire _244_;
+  wire _245_;
+  wire _246_;
+  wire _247_;
+  wire _248_;
+  wire _249_;
+  wire _250_;
+  wire _251_;
+  wire _252_;
+  wire _253_;
+  wire _254_;
+  wire _255_;
+  wire _256_;
+  wire _257_;
+  wire _258_;
+  wire _259_;
+  wire _260_;
+  wire _261_;
+  wire _262_;
+  wire _263_;
+  wire _264_;
+  wire _265_;
+  wire _266_;
+  wire access_ok;
+  reg [199:0] cache_tags;
+  reg [3:0] cache_valids;
+  input clk;
+  wire eaa_priv;
+  input flush_in;
+  input [69:0] i_in;
+  output [98:0] i_out;
+  input inval_in;
+  reg [3:0] itlb_valids;
+  input [130:0] m_in;
+  wire \maybe_plrus.plrus:0.plru_acc_en ;
+  wire \maybe_plrus.plrus:0.plru_out ;
+  wire \maybe_plrus.plrus:1.plru_acc_en ;
+  wire \maybe_plrus.plrus:1.plru_out ;
+  wire priv_fault;
+  wire ra_valid;
+  wire \rams:0.do_read ;
+  wire \rams:0.do_write ;
+  wire [63:0] \rams:0.dout ;
+  wire [63:0] \rams:0.wr_dat ;
+  wire \rams:1.do_read ;
+  wire \rams:1.do_write ;
+  wire [63:0] \rams:1.dout ;
+  wire [63:0] \rams:1.wr_dat ;
+  wire [55:0] real_addr;
+  wire replace_way;
+  wire req_hit_way;
+  wire req_is_hit;
+  wire req_is_miss;
+  input rst;
+  input stall_in;
+  output stall_out;
+  wire [1:0] tlb_req_index;
+  wire use_previous;
+  input [65:0] wishbone_in;
+  output [106:0] wishbone_out;
+  reg [63:0] \$mem$\8207  [3:0];
+  reg [49:0] \$mem$\8210  [3:0];
+  (* ram_style = "distributed" *)
+  reg [63:0] \8207  [3:0];
+  always @(posedge clk) begin
+    if (_032_) \8207 [_017_] <= m_in[130:67];
+  end
+  assign _169_ = \8207 [tlb_req_index];
+  (* ram_style = "distributed" *)
+  reg [49:0] \8210  [3:0];
+  always @(posedge clk) begin
+    if (_028_) \8210 [_017_] <= m_in[66:17];
+  end
+  assign _171_ = \8210 [tlb_req_index];
+  assign _257_ = _012_[0] ? itlb_valids[1] : itlb_valids[0];
+  assign _258_ = _041_[0] ? _167_[170] : _167_[169];
+  assign _259_ = _041_[0] ? _167_[174] : _167_[173];
+  assign _260_ = _055_[0] ? _167_[170] : _167_[169];
+  assign _261_ = _055_[0] ? _167_[174] : _167_[173];
+  assign _262_ = _012_[0] ? itlb_valids[3] : itlb_valids[2];
+  assign _263_ = _041_[0] ? _167_[172] : _167_[171];
+  assign _264_ = _041_[0] ? _167_[176] : _167_[175];
+  assign _265_ = _055_[0] ? _167_[172] : _167_[171];
+  assign _266_ = _055_[0] ? _167_[176] : _167_[175];
+  assign _172_ = _012_[1] ? _262_ : _257_;
+  assign _194_ = _041_[1] ? _263_ : _258_;
+  assign _195_ = _041_[1] ? _264_ : _259_;
+  assign _199_ = _055_[1] ? _265_ : _260_;
+  assign _200_ = _055_[1] ? _266_ : _261_;
+  assign _000_ = ~ _167_[164];
+  assign \rams:0.wr_dat  = _000_ ? wishbone_in[63:0] : { wishbone_in[39:32], wishbone_in[47:40], wishbone_in[55:48], wishbone_in[63:56], wishbone_in[7:0], wishbone_in[15:8], wishbone_in[23:16], wishbone_in[31:24] };
+  assign _001_ = stall_in | use_previous;
+  assign \rams:0.do_read  = ~ _001_;
+  assign _002_ = { 31'h00000000, replace_way } == 32'd0;
+  assign _003_ = wishbone_in[64] & _002_;
+  assign \rams:0.do_write  = _003_ ? 1'h1 : 1'h0;
+  assign _004_ = ~ _167_[164];
+  assign \rams:1.wr_dat  = _004_ ? wishbone_in[63:0] : { wishbone_in[39:32], wishbone_in[47:40], wishbone_in[55:48], wishbone_in[63:56], wishbone_in[7:0], wishbone_in[15:8], wishbone_in[23:16], wishbone_in[31:24] };
+  assign _005_ = stall_in | use_previous;
+  assign \rams:1.do_read  = ~ _005_;
+  assign _006_ = { 31'h00000000, replace_way } == 32'd1;
+  assign _007_ = wishbone_in[64] & _006_;
+  assign \rams:1.do_write  = _007_ ? 1'h1 : 1'h0;
+  assign _008_ = { 31'h00000000, _083_[7] } == 32'd0;
+  assign \maybe_plrus.plrus:0.plru_acc_en  = _008_ ? _083_[66] : 1'h0;
+  assign _009_ = { 31'h00000000, _083_[7] } == 32'd1;
+  assign \maybe_plrus.plrus:1.plru_acc_en  = _009_ ? _083_[66] : 1'h0;
+  assign _010_ = i_in[19:18] ^ i_in[21:20];
+  assign tlb_req_index = _010_ ^ i_in[23:22];
+  assign _011_ = _171_ == i_in[69:20];
+  assign _012_ = 2'h3 - tlb_req_index;
+  assign _013_ = _011_ ? _172_ : 1'h0;
+  assign eaa_priv = i_in[1] ? _169_[3] : 1'h1;
+  assign real_addr = i_in[1] ? { _169_[55:12], i_in[17:6] } : i_in[61:6];
+  assign ra_valid = i_in[1] ? _013_ : 1'h1;
+  assign _014_ = ~ i_in[2];
+  assign priv_fault = eaa_priv & _014_;
+  assign _015_ = ~ priv_fault;
+  assign access_ok = ra_valid & _015_;
+  assign _016_ = m_in[16:15] ^ m_in[18:17];
+  assign _017_ = _016_ ^ m_in[20:19];
+  assign _018_ = m_in[1] & m_in[2];
+  assign _019_ = rst | _018_;
+  assign _020_ = 2'h3 - _017_;
+  assign _021_ = 2'h3 - _017_;
+  assign _022_ = m_in[0] ? { _192_, _191_, _190_, _189_ } : itlb_valids;
+  assign _023_ = m_in[1] ? { _182_, _181_, _180_, _179_ } : _022_;
+  assign _024_ = _019_ ? 4'h0 : _023_;
+  always @(posedge clk)
+    itlb_valids <= _024_;
+  assign _025_ = ~ _019_;
+  assign _026_ = ~ m_in[1];
+  assign _027_ = _025_ & _026_;
+  assign _028_ = _027_ & m_in[0];
+  assign _029_ = ~ _019_;
+  assign _030_ = ~ m_in[1];
+  assign _031_ = _029_ & _030_;
+  assign _032_ = _031_ & m_in[0];
+  assign _033_ = i_in[8] != 1'h0;
+  assign _034_ = i_in[5] & _083_[66];
+  assign use_previous = _033_ ? _034_ : 1'h0;
+  assign _035_ = 1'h1 - i_in[12];
+  assign _036_ = _167_[1:0] == 2'h2;
+  assign _037_ = { 31'h00000000, i_in[12] } == { 31'h00000000, _167_[110] };
+  assign _038_ = _036_ & _037_;
+  assign _039_ = 32'd0 == { 31'h00000000, _167_[109] };
+  assign _040_ = _038_ & _039_;
+  assign _041_ = 3'h7 - i_in[11:9];
+  assign _042_ = _040_ & _196_;
+  assign _043_ = _193_ | _042_;
+  assign _044_ = i_in[0] & _043_;
+  assign _045_ = 1'h1 - i_in[12];
+  assign _046_ = _197_[49:0] == { i_in[3], real_addr[55:7] };
+  assign _047_ = _046_ ? 1'h1 : 1'h0;
+  assign _048_ = _044_ ? _047_ : 1'h0;
+  assign _049_ = 1'h1 - i_in[12];
+  assign _050_ = _167_[1:0] == 2'h2;
+  assign _051_ = { 31'h00000000, i_in[12] } == { 31'h00000000, _167_[110] };
+  assign _052_ = _050_ & _051_;
+  assign _053_ = 32'd1 == { 31'h00000000, _167_[109] };
+  assign _054_ = _052_ & _053_;
+  assign _055_ = 3'h7 - i_in[11:9];
+  assign _056_ = _054_ & _201_;
+  assign _057_ = _198_ | _056_;
+  assign _058_ = i_in[0] & _057_;
+  assign _059_ = 1'h1 - i_in[12];
+  assign _060_ = _202_[99:50] == { i_in[3], real_addr[55:7] };
+  assign _061_ = _063_ ? 1'h1 : _048_;
+  assign _062_ = _060_ ? 1'h1 : 1'h0;
+  assign _063_ = _058_ & _060_;
+  assign req_hit_way = _058_ ? _062_ : 1'h0;
+  assign _064_ = i_in[0] & access_ok;
+  assign _065_ = ~ flush_in;
+  assign _066_ = _064_ & _065_;
+  assign _067_ = ~ rst;
+  assign _068_ = _066_ & _067_;
+  assign _069_ = ~ _061_;
+  assign req_is_hit = _068_ ? _061_ : 1'h0;
+  assign req_is_miss = _068_ ? _069_ : 1'h0;
+  assign _070_ = _167_[1:0] == 2'h1;
+  assign _071_ = 1'h1 - _167_[110];
+  assign replace_way = _070_ ? _203_ : _167_[109];
+  assign _072_ = 1'h1 - _083_[0];
+  assign _073_ = _061_ & access_ok;
+  assign _074_ = ~ _073_;
+  assign _075_ = stall_in | use_previous;
+  assign _076_ = rst | flush_in;
+  assign _077_ = _076_ ? 1'h0 : _083_[66];
+  assign _078_ = req_is_hit ? req_hit_way : _083_[0];
+  assign _079_ = _075_ ? _083_[0] : _078_;
+  assign _080_ = _075_ ? _077_ : req_is_hit;
+  assign _081_ = ~ stall_in;
+  assign _082_ = _081_ ? { i_in[4], i_in[69:6] } : _083_[65:1];
+  always @(posedge clk)
+    _083_ <= { _080_, _082_, _079_ };
+  assign _084_ = inval_in ? 4'h0 : cache_valids;
+  assign _085_ = inval_in ? 1'h0 : _167_[165];
+  assign _086_ = real_addr[5:3] - 3'h1;
+  assign _087_ = req_is_miss ? { real_addr[31:3], 5'h01 } : _167_[33:0];
+  assign _088_ = req_is_miss ? 2'h3 : _167_[107:106];
+  assign _089_ = req_is_miss ? { _086_, 1'h1, i_in[3], real_addr[55:3], i_in[12] } : { _167_[168:166], _085_, _167_[164:110] };
+  assign _090_ = _167_[1:0] == 2'h0;
+  assign _091_ = _167_[1:0] == 2'h1;
+  assign _092_ = 1'h1 - i_in[12];
+  assign _093_ = 32'd0 == { 31'h00000000, replace_way };
+  assign _094_ = 1'h1 - _167_[110];
+  assign _095_ = 1'h1 - _167_[110];
+  assign _096_ = _093_ ? { _219_, _218_ } : cache_tags;
+  assign _097_ = 32'd1 == { 31'h00000000, replace_way };
+  assign _098_ = 1'h1 - _167_[110];
+  assign _099_ = 1'h1 - _167_[110];
+  assign _100_ = _097_ ? { _223_, _222_ } : _096_;
+  assign _101_ = _091_ ? _100_ : cache_tags;
+  assign _102_ = _091_ ? { _215_, _214_, _213_, _212_ } : _084_;
+  assign _103_ = _091_ ? 2'h2 : _167_[1:0];
+  assign _104_ = _091_ ? replace_way : _167_[109];
+  assign _105_ = ~ _167_[107];
+  assign _106_ = ~ wishbone_in[65];
+  assign _107_ = ~ _105_;
+  assign _108_ = _106_ & _107_;
+  assign _109_ = _167_[7:5] == _167_[168:166];
+  assign _110_ = _114_ ? 1'h0 : _167_[107];
+  assign _111_ = _115_ ? 1'h1 : _105_;
+  assign _112_ = _167_[7:5] + 3'h1;
+  assign _113_ = _108_ ? { _167_[33:8], _112_, _167_[4:2] } : _167_[33:2];
+  assign _114_ = _108_ & _109_;
+  assign _115_ = _108_ & _109_;
+  assign _116_ = 3'h7 - _167_[113:111];
+  assign _117_ = _167_[113:111] == _167_[168:166];
+  assign _118_ = _111_ & _117_;
+  assign _119_ = 1'h1 - _167_[110];
+  assign _120_ = ~ inval_in;
+  assign _121_ = _167_[165] & _120_;
+  assign _122_ = _126_ ? { _256_, _255_, _254_, _253_ } : _102_;
+  assign _123_ = _127_ ? 2'h0 : _103_;
+  assign _124_ = _128_ ? 1'h0 : _167_[106];
+  assign _125_ = _167_[113:111] + 3'h1;
+  assign _126_ = wishbone_in[64] & _118_;
+  assign _127_ = wishbone_in[64] & _118_;
+  assign _128_ = wishbone_in[64] & _118_;
+  assign _129_ = wishbone_in[64] ? { _167_[114], _125_ } : _167_[114:111];
+  assign _130_ = wishbone_in[64] ? { _246_, _245_, _244_, _243_, _242_, _241_, _240_, _239_ } : _167_[176:169];
+  assign _131_ = _167_[1:0] == 2'h1;
+  assign _132_ = _167_[1:0] == 2'h2;
+  assign _133_ = _131_ | _132_;
+  function [199:0] \8094 ;
+    input [199:0] a;
+    input [399:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \8094  = b[199:0];
+      2'b1?:
+        \8094  = b[399:200];
+      default:
+        \8094  = a;
+    endcase
+  endfunction
+  assign _134_ = \8094 (200'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { _101_, cache_tags }, { _133_, _090_ });
+  function [3:0] \8096 ;
+    input [3:0] a;
+    input [7:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \8096  = b[3:0];
+      2'b1?:
+        \8096  = b[7:4];
+      default:
+        \8096  = a;
+    endcase
+  endfunction
+  assign _135_ = \8096 (4'hx, { _122_, _084_ }, { _133_, _090_ });
+  function [1:0] \8099 ;
+    input [1:0] a;
+    input [3:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \8099  = b[1:0];
+      2'b1?:
+        \8099  = b[3:2];
+      default:
+        \8099  = a;
+    endcase
+  endfunction
+  assign _136_ = \8099 (2'hx, { _123_, _087_[1:0] }, { _133_, _090_ });
+  function [31:0] \8102 ;
+    input [31:0] a;
+    input [63:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \8102  = b[31:0];
+      2'b1?:
+        \8102  = b[63:32];
+      default:
+        \8102  = a;
+    endcase
+  endfunction
+  assign _137_ = \8102 (32'hxxxxxxxx, { _113_, _087_[33:2] }, { _133_, _090_ });
+  function [0:0] \8105 ;
+    input [0:0] a;
+    input [1:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \8105  = b[0:0];
+      2'b1?:
+        \8105  = b[1:1];
+      default:
+        \8105  = a;
+    endcase
+  endfunction
+  assign _138_ = \8105 (1'hx, { _124_, _088_[0] }, { _133_, _090_ });
+  function [0:0] \8108 ;
+    input [0:0] a;
+    input [1:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \8108  = b[0:0];
+      2'b1?:
+        \8108  = b[1:1];
+      default:
+        \8108  = a;
+    endcase
+  endfunction
+  assign _139_ = \8108 (1'hx, { _110_, _088_[1] }, { _133_, _090_ });
+  function [0:0] \8111 ;
+    input [0:0] a;
+    input [1:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \8111  = b[0:0];
+      2'b1?:
+        \8111  = b[1:1];
+      default:
+        \8111  = a;
+    endcase
+  endfunction
+  assign _140_ = \8111 (1'hx, { _104_, _167_[109] }, { _133_, _090_ });
+  function [0:0] \8115 ;
+    input [0:0] a;
+    input [1:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \8115  = b[0:0];
+      2'b1?:
+        \8115  = b[1:1];
+      default:
+        \8115  = a;
+    endcase
+  endfunction
+  assign _141_ = \8115 (1'hx, { _167_[110], _089_[0] }, { _133_, _090_ });
+  function [3:0] \8118 ;
+    input [3:0] a;
+    input [7:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \8118  = b[3:0];
+      2'b1?:
+        \8118  = b[7:4];
+      default:
+        \8118  = a;
+    endcase
+  endfunction
+  assign _142_ = \8118 (4'hx, { _129_, _089_[4:1] }, { _133_, _090_ });
+  function [53:0] \8124 ;
+    input [53:0] a;
+    input [107:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \8124  = b[53:0];
+      2'b1?:
+        \8124  = b[107:54];
+      default:
+        \8124  = a;
+    endcase
+  endfunction
+  assign _143_ = \8124 (54'hxxxxxxxxxxxxxx, { _167_[168:166], _085_, _167_[164:115], _089_[58:5] }, { _133_, _090_ });
+  function [0:0] \8127 ;
+    input [0:0] a;
+    input [1:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \8127  = b[0:0];
+      2'b1?:
+        \8127  = b[1:1];
+      default:
+        \8127  = a;
+    endcase
+  endfunction
+  assign _144_ = \8127 (1'hx, { _130_[0], 1'h0 }, { _133_, _090_ });
+  function [0:0] \8130 ;
+    input [0:0] a;
+    input [1:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \8130  = b[0:0];
+      2'b1?:
+        \8130  = b[1:1];
+      default:
+        \8130  = a;
+    endcase
+  endfunction
+  assign _145_ = \8130 (1'hx, { _130_[1], 1'h0 }, { _133_, _090_ });
+  function [0:0] \8133 ;
+    input [0:0] a;
+    input [1:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \8133  = b[0:0];
+      2'b1?:
+        \8133  = b[1:1];
+      default:
+        \8133  = a;
+    endcase
+  endfunction
+  assign _146_ = \8133 (1'hx, { _130_[2], 1'h0 }, { _133_, _090_ });
+  function [0:0] \8136 ;
+    input [0:0] a;
+    input [1:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \8136  = b[0:0];
+      2'b1?:
+        \8136  = b[1:1];
+      default:
+        \8136  = a;
+    endcase
+  endfunction
+  assign _147_ = \8136 (1'hx, { _130_[3], 1'h0 }, { _133_, _090_ });
+  function [0:0] \8139 ;
+    input [0:0] a;
+    input [1:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \8139  = b[0:0];
+      2'b1?:
+        \8139  = b[1:1];
+      default:
+        \8139  = a;
+    endcase
+  endfunction
+  assign _148_ = \8139 (1'hx, { _130_[4], 1'h0 }, { _133_, _090_ });
+  function [0:0] \8142 ;
+    input [0:0] a;
+    input [1:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \8142  = b[0:0];
+      2'b1?:
+        \8142  = b[1:1];
+      default:
+        \8142  = a;
+    endcase
+  endfunction
+  assign _149_ = \8142 (1'hx, { _130_[5], 1'h0 }, { _133_, _090_ });
+  function [0:0] \8145 ;
+    input [0:0] a;
+    input [1:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \8145  = b[0:0];
+      2'b1?:
+        \8145  = b[1:1];
+      default:
+        \8145  = a;
+    endcase
+  endfunction
+  assign _150_ = \8145 (1'hx, { _130_[6], 1'h0 }, { _133_, _090_ });
+  function [0:0] \8148 ;
+    input [0:0] a;
+    input [1:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \8148  = b[0:0];
+      2'b1?:
+        \8148  = b[1:1];
+      default:
+        \8148  = a;
+    endcase
+  endfunction
+  assign _151_ = \8148 (1'hx, { _130_[7], 1'h0 }, { _133_, _090_ });
+  assign _152_ = rst ? cache_tags : _134_;
+  assign _153_ = rst ? 4'h0 : _135_;
+  assign _154_ = rst ? 34'h000000000 : { _137_, _136_ };
+  assign _155_ = rst ? 72'hff0000000000000000 : _167_[105:34];
+  assign _156_ = rst ? 2'h0 : { _139_, _138_ };
+  assign _157_ = rst ? 1'h0 : _167_[108];
+  assign _158_ = rst ? _167_[176:109] : { _151_, _150_, _149_, _148_, _147_, _146_, _145_, _144_, _143_, _142_, _141_, _140_ };
+  assign _159_ = rst | flush_in;
+  assign _160_ = _159_ | m_in[0];
+  assign _161_ = ~ access_ok;
+  assign _162_ = i_in[0] & _161_;
+  assign _163_ = ~ stall_in;
+  assign _164_ = _162_ & _163_;
+  assign _165_ = _164_ ? 1'h1 : _167_[177];
+  assign _166_ = _160_ ? 1'h0 : _165_;
+  always @(posedge clk)
+    cache_tags <= _152_;
+  always @(posedge clk)
+    cache_valids <= _153_;
+  always @(posedge clk)
+    _167_ <= { _166_, _158_, _157_, _156_, _155_, _154_ };
+  assign _173_ = ~ _020_[1];
+  assign _174_ = ~ _020_[0];
+  assign _175_ = _173_ & _174_;
+  assign _176_ = _173_ & _020_[0];
+  assign _177_ = _020_[1] & _174_;
+  assign _178_ = _020_[1] & _020_[0];
+  assign _179_ = _175_ ? 1'h0 : itlb_valids[0];
+  assign _180_ = _176_ ? 1'h0 : itlb_valids[1];
+  assign _181_ = _177_ ? 1'h0 : itlb_valids[2];
+  assign _182_ = _178_ ? 1'h0 : itlb_valids[3];
+  assign _183_ = ~ _021_[1];
+  assign _184_ = ~ _021_[0];
+  assign _185_ = _183_ & _184_;
+  assign _186_ = _183_ & _021_[0];
+  assign _187_ = _021_[1] & _184_;
+  assign _188_ = _021_[1] & _021_[0];
+  assign _189_ = _185_ ? 1'h1 : itlb_valids[0];
+  assign _190_ = _186_ ? 1'h1 : itlb_valids[1];
+  assign _191_ = _187_ ? 1'h1 : itlb_valids[2];
+  assign _192_ = _188_ ? 1'h1 : itlb_valids[3];
+  assign _193_ = _035_ ? cache_valids[2] : cache_valids[0];
+  assign _196_ = _041_[2] ? _195_ : _194_;
+  assign _197_ = _045_ ? cache_tags[199:100] : cache_tags[99:0];
+  assign _198_ = _049_ ? cache_valids[3] : cache_valids[1];
+  assign _201_ = _055_[2] ? _200_ : _199_;
+  assign _202_ = _059_ ? cache_tags[199:100] : cache_tags[99:0];
+  assign _203_ = _071_ ? \maybe_plrus.plrus:0.plru_out  : \maybe_plrus.plrus:1.plru_out ;
+  assign _204_ = _072_ ? \rams:0.dout  : \rams:1.dout ;
+  assign _205_ = _083_[3] ? _204_[63:32] : _204_[31:0];
+  assign _206_ = ~ _092_;
+  assign _207_ = ~ replace_way;
+  assign _208_ = _206_ & _207_;
+  assign _209_ = _206_ & replace_way;
+  assign _210_ = _092_ & _207_;
+  assign _211_ = _092_ & replace_way;
+  assign _212_ = _208_ ? 1'h0 : _084_[0];
+  assign _213_ = _209_ ? 1'h0 : _084_[1];
+  assign _214_ = _210_ ? 1'h0 : _084_[2];
+  assign _215_ = _211_ ? 1'h0 : _084_[3];
+  assign _216_ = _094_ ? cache_tags[199:100] : cache_tags[99:0];
+  assign _217_ = ~ _095_;
+  assign _218_ = _217_ ? { _216_[99:50], _167_[164:115] } : cache_tags[99:0];
+  assign _219_ = _095_ ? { _216_[99:50], _167_[164:115] } : cache_tags[199:100];
+  assign _220_ = _098_ ? cache_tags[199:100] : cache_tags[99:0];
+  assign _221_ = ~ _099_;
+  assign _222_ = _221_ ? { _167_[164:115], _220_[49:0] } : _096_[99:0];
+  assign _223_ = _099_ ? { _167_[164:115], _220_[49:0] } : _096_[199:100];
+  assign _224_ = ~ _116_[2];
+  assign _225_ = ~ _116_[1];
+  assign _226_ = _224_ & _225_;
+  assign _227_ = _224_ & _116_[1];
+  assign _228_ = _116_[2] & _225_;
+  assign _229_ = _116_[2] & _116_[1];
+  assign _230_ = ~ _116_[0];
+  assign _231_ = _226_ & _230_;
+  assign _232_ = _226_ & _116_[0];
+  assign _233_ = _227_ & _230_;
+  assign _234_ = _227_ & _116_[0];
+  assign _235_ = _228_ & _230_;
+  assign _236_ = _228_ & _116_[0];
+  assign _237_ = _229_ & _230_;
+  assign _238_ = _229_ & _116_[0];
+  assign _239_ = _231_ ? 1'h1 : _167_[169];
+  assign _240_ = _232_ ? 1'h1 : _167_[170];
+  assign _241_ = _233_ ? 1'h1 : _167_[171];
+  assign _242_ = _234_ ? 1'h1 : _167_[172];
+  assign _243_ = _235_ ? 1'h1 : _167_[173];
+  assign _244_ = _236_ ? 1'h1 : _167_[174];
+  assign _245_ = _237_ ? 1'h1 : _167_[175];
+  assign _246_ = _238_ ? 1'h1 : _167_[176];
+  assign _247_ = ~ _119_;
+  assign _248_ = ~ replace_way;
+  assign _249_ = _247_ & _248_;
+  assign _250_ = _247_ & replace_way;
+  assign _251_ = _119_ & _248_;
+  assign _252_ = _119_ & replace_way;
+  assign _253_ = _249_ ? _121_ : _102_[0];
+  assign _254_ = _250_ ? _121_ : _102_[1];
+  assign _255_ = _251_ ? _121_ : _102_[2];
+  assign _256_ = _252_ ? _121_ : _102_[3];
+  plru_1 \maybe_plrus.plrus:0.plru  (
+    .acc(_083_[0]),
+    .acc_en(\maybe_plrus.plrus:0.plru_acc_en ),
+    .clk(clk),
+    .lru(\maybe_plrus.plrus:0.plru_out ),
+    .rst(rst)
+  );
+  plru_1 \maybe_plrus.plrus:1.plru  (
+    .acc(_083_[0]),
+    .acc_en(\maybe_plrus.plrus:1.plru_acc_en ),
+    .clk(clk),
+    .lru(\maybe_plrus.plrus:1.plru_out ),
+    .rst(rst)
+  );
+  cache_ram_4_64_1489f923c4dca729178b3e3233458550d8dddf29 \rams:0.way  (
+    .clk(clk),
+    .rd_addr(i_in[12:9]),
+    .rd_data(\rams:0.dout ),
+    .rd_en(\rams:0.do_read ),
+    .wr_addr(_167_[114:111]),
+    .wr_data(\rams:0.wr_dat ),
+    .wr_sel({ \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write , \rams:0.do_write  })
+  );
+  cache_ram_4_64_1489f923c4dca729178b3e3233458550d8dddf29 \rams:1.way  (
+    .clk(clk),
+    .rd_addr(i_in[12:9]),
+    .rd_data(\rams:1.dout ),
+    .rd_en(\rams:1.do_read ),
+    .wr_addr(_167_[114:111]),
+    .wr_data(\rams:1.wr_dat ),
+    .wr_sel({ \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write , \rams:1.do_write  })
+  );
+  assign i_out = { _205_, _083_[64:1], _167_[177], _083_[65], _083_[66] };
+  assign stall_out = _074_;
+  assign wishbone_out = _167_[108:2];
+endmodule
diff --git a/verilog/rtl/microwatt.v b/verilog/rtl/microwatt.v
new file mode 100644
index 0000000..e4df252
--- /dev/null
+++ b/verilog/rtl/microwatt.v
@@ -0,0 +1,30284 @@
+/* Generated by Yosys 0.9+3743 (git sha1 UNKNOWN, clang 7.0.1-8+deb10u2 -fPIC -Os) */
+
+/* JTAG */
+`include "tap_top.v"
+
+/* UART */
+`include "raminfr.v"
+`include "uart_receiver.v"
+`include "uart_rfifo.v"
+`include "uart_tfifo.v"
+`include "uart_transmitter.v"
+`include "uart_defines.v"
+`include "uart_regs.v"
+`include "uart_sync_flops.v"
+`include "uart_wb.v"
+`include "uart_top.v"
+
+
+
+module control_1(clk, rst, complete_in, valid_in, flush_in, busy_in, deferred, sgl_pipe_in, stop_mark_in, gpr_write_valid_in, gpr_write_in, gpr_bypassable, update_gpr_write_valid, update_gpr_write_reg, gpr_a_read_valid_in, gpr_a_read_in, gpr_b_read_valid_in, gpr_b_read_in, gpr_c_read_valid_in, gpr_c_read_in, cr_read_in, cr_write_in, cr_bypassable, valid_out, stall_out, stopped_out, gpr_bypass_a, gpr_bypass_b, gpr_bypass_c, cr_bypass);
+  wire _00_;
+  wire _01_;
+  wire _02_;
+  wire _03_;
+  wire _04_;
+  wire _05_;
+  wire [31:0] _06_;
+  wire [2:0] _07_;
+  wire [2:0] _08_;
+  wire [4:0] _09_;
+  wire _10_;
+  wire _11_;
+  wire _12_;
+  wire _13_;
+  wire _14_;
+  wire [1:0] _15_;
+  wire _16_;
+  wire _17_;
+  wire _18_;
+  wire _19_;
+  wire [1:0] _20_;
+  wire [1:0] _21_;
+  wire _22_;
+  wire [1:0] _23_;
+  wire [1:0] _24_;
+  wire _25_;
+  wire _26_;
+  wire _27_;
+  wire [1:0] _28_;
+  wire [1:0] _29_;
+  wire _30_;
+  wire _31_;
+  wire _32_;
+  wire [2:0] _33_;
+  wire _34_;
+  wire [1:0] _35_;
+  wire _36_;
+  wire _37_;
+  wire _38_;
+  wire _39_;
+  wire [1:0] _40_;
+  wire _41_;
+  wire _42_;
+  wire _43_;
+  wire [1:0] _44_;
+  wire [1:0] _45_;
+  wire _46_;
+  wire _47_;
+  wire [1:0] _48_;
+  wire [2:0] _49_;
+  wire _50_;
+  wire _51_;
+  wire _52_;
+  wire [31:0] _53_;
+  wire [2:0] _54_;
+  wire _55_;
+  wire _56_;
+  input busy_in;
+  input clk;
+  input complete_in;
+  output cr_bypass;
+  input cr_bypassable;
+  input cr_read_in;
+  wire cr_stall_out;
+  input cr_write_in;
+  wire cr_write_valid;
+  input deferred;
+  input flush_in;
+  input [6:0] gpr_a_read_in;
+  input gpr_a_read_valid_in;
+  input [6:0] gpr_b_read_in;
+  input gpr_b_read_valid_in;
+  output gpr_bypass_a;
+  output gpr_bypass_b;
+  output gpr_bypass_c;
+  input gpr_bypassable;
+  input [6:0] gpr_c_read_in;
+  input gpr_c_read_valid_in;
+  input [6:0] gpr_write_in;
+  wire gpr_write_valid;
+  input gpr_write_valid_in;
+  reg [4:0] r_int = 5'h00;
+  input rst;
+  input sgl_pipe_in;
+  wire stall_a_out;
+  wire stall_b_out;
+  wire stall_c_out;
+  output stall_out;
+  input stop_mark_in;
+  output stopped_out;
+  input [6:0] update_gpr_write_reg;
+  input update_gpr_write_valid;
+  input valid_in;
+  output valid_out;
+  always @(posedge clk)
+    r_int <= { _54_, _48_ };
+  assign _04_ = ~ flush_in;
+  assign _05_ = valid_in & _04_;
+  assign _06_ = { r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4:2] } - 32'd1;
+  assign _07_ = complete_in ? _06_[2:0] : r_int[4:2];
+  assign _08_ = flush_in ? 3'h1 : _07_;
+  assign _09_ = rst ? 5'h00 : { _08_, r_int[1:0] };
+  assign _10_ = rst ? 1'h0 : _05_;
+  assign _11_ = { _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4:2] } == 32'd0;
+  assign _12_ = stop_mark_in & _11_;
+  assign _13_ = _12_ ? 1'h1 : 1'h0;
+  assign _14_ = { _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4:2] } != 32'd0;
+  assign _15_ = _14_ ? 2'h1 : 2'h2;
+  assign _16_ = _14_ ? 1'h1 : 1'h0;
+  assign _17_ = stall_a_out | stall_b_out;
+  assign _18_ = _17_ | stall_c_out;
+  assign _19_ = _18_ | cr_stall_out;
+  assign _20_ = rst ? 2'h0 : r_int[1:0];
+  assign _21_ = sgl_pipe_in ? _15_ : _20_;
+  assign _22_ = sgl_pipe_in ? _16_ : _19_;
+  assign _23_ = rst ? 2'h0 : r_int[1:0];
+  assign _24_ = _10_ ? _21_ : _23_;
+  assign _25_ = _10_ ? _22_ : 1'h0;
+  assign _26_ = r_int[1:0] == 2'h0;
+  assign _27_ = { _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4:2] } == 32'd0;
+  assign _28_ = rst ? 2'h0 : r_int[1:0];
+  assign _29_ = _27_ ? 2'h2 : _28_;
+  assign _30_ = _27_ ? 1'h0 : 1'h1;
+  assign _31_ = r_int[1:0] == 2'h1;
+  assign _32_ = { _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4], _09_[4:2] } == 32'd0;
+  assign _33_ = rst ? 3'h0 : _08_;
+  assign _34_ = { _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_[2], _33_ } != 32'd0;
+  assign _35_ = _34_ ? 2'h1 : 2'h2;
+  assign _36_ = _34_ ? 1'h1 : 1'h0;
+  assign _37_ = stall_a_out | stall_b_out;
+  assign _38_ = _37_ | stall_c_out;
+  assign _39_ = _38_ | cr_stall_out;
+  assign _40_ = _42_ ? _35_ : 2'h0;
+  assign _41_ = sgl_pipe_in ? _36_ : _39_;
+  assign _42_ = _10_ & sgl_pipe_in;
+  assign _43_ = _10_ ? _41_ : 1'h0;
+  assign _44_ = rst ? 2'h0 : r_int[1:0];
+  assign _45_ = _32_ ? _40_ : _44_;
+  assign _46_ = _32_ ? _43_ : 1'h1;
+  assign _47_ = r_int[1:0] == 2'h2;
+  function [1:0] \20544 ;
+    input [1:0] a;
+    input [5:0] b;
+    input [2:0] s;
+    (* parallel_case *)
+    casez (s)
+      3'b??1:
+        \20544  = b[1:0];
+      3'b?1?:
+        \20544  = b[3:2];
+      3'b1??:
+        \20544  = b[5:4];
+      default:
+        \20544  = a;
+    endcase
+  endfunction
+  assign _48_ = \20544 (2'hx, { _45_, _29_, _24_ }, { _47_, _31_, _26_ });
+  assign _49_ = rst ? 3'h0 : _08_;
+  function [0:0] \20549 ;
+    input [0:0] a;
+    input [2:0] b;
+    input [2:0] s;
+    (* parallel_case *)
+    casez (s)
+      3'b??1:
+        \20549  = b[0:0];
+      3'b?1?:
+        \20549  = b[1:1];
+      3'b1??:
+        \20549  = b[2:2];
+      default:
+        \20549  = a;
+    endcase
+  endfunction
+  assign _50_ = \20549 (1'hx, { _46_, _30_, _25_ }, { _47_, _31_, _26_ });
+  assign _51_ = _50_ ? 1'h0 : _10_;
+  assign _52_ = ~ deferred;
+  assign _53_ = { _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_[2], _49_ } + 32'd1;
+  assign _54_ = _55_ ? _53_[2:0] : _49_;
+  assign gpr_write_valid = _51_ ? gpr_write_valid_in : 1'h0;
+  assign cr_write_valid = _51_ ? cr_write_in : 1'h0;
+  assign _55_ = _51_ & _52_;
+  assign _56_ = _50_ | deferred;
+  cr_hazard_1 cr_hazard0 (
+    .busy_in(busy_in),
+    .bypassable(cr_bypassable),
+    .clk(clk),
+    .complete_in(complete_in),
+    .cr_read_in(cr_read_in),
+    .cr_write_in(cr_write_valid),
+    .deferred(deferred),
+    .flush_in(flush_in),
+    .issuing(_51_),
+    .stall_out(cr_stall_out),
+    .use_bypass(_03_)
+  );
+  gpr_hazard_1 gpr_hazard0 (
+    .busy_in(busy_in),
+    .bypass_avail(gpr_bypassable),
+    .clk(clk),
+    .complete_in(complete_in),
+    .deferred(deferred),
+    .flush_in(flush_in),
+    .gpr_read_in(gpr_a_read_in),
+    .gpr_read_valid_in(gpr_a_read_valid_in),
+    .gpr_write_in(gpr_write_in),
+    .gpr_write_valid_in(gpr_write_valid),
+    .issuing(_51_),
+    .stall_out(stall_a_out),
+    .ugpr_write_reg(update_gpr_write_reg),
+    .ugpr_write_valid(update_gpr_write_valid),
+    .use_bypass(_00_)
+  );
+  gpr_hazard_1 gpr_hazard1 (
+    .busy_in(busy_in),
+    .bypass_avail(gpr_bypassable),
+    .clk(clk),
+    .complete_in(complete_in),
+    .deferred(deferred),
+    .flush_in(flush_in),
+    .gpr_read_in(gpr_b_read_in),
+    .gpr_read_valid_in(gpr_b_read_valid_in),
+    .gpr_write_in(gpr_write_in),
+    .gpr_write_valid_in(gpr_write_valid),
+    .issuing(_51_),
+    .stall_out(stall_b_out),
+    .ugpr_write_reg(update_gpr_write_reg),
+    .ugpr_write_valid(update_gpr_write_valid),
+    .use_bypass(_01_)
+  );
+  gpr_hazard_1 gpr_hazard2 (
+    .busy_in(busy_in),
+    .bypass_avail(gpr_bypassable),
+    .clk(clk),
+    .complete_in(complete_in),
+    .deferred(deferred),
+    .flush_in(flush_in),
+    .gpr_read_in(gpr_c_read_in),
+    .gpr_read_valid_in(gpr_c_read_valid_in),
+    .gpr_write_in(gpr_write_in),
+    .gpr_write_valid_in(gpr_write_valid),
+    .issuing(_51_),
+    .stall_out(stall_c_out),
+    .ugpr_write_reg(update_gpr_write_reg),
+    .ugpr_write_valid(update_gpr_write_valid),
+    .use_bypass(_02_)
+  );
+  assign valid_out = _51_;
+  assign stall_out = _56_;
+  assign stopped_out = _13_;
+  assign gpr_bypass_a = _00_;
+  assign gpr_bypass_b = _01_;
+  assign gpr_bypass_c = _02_;
+  assign cr_bypass = _03_;
+endmodule
+
+module core_0_602f7ae323a872754ff5ac989c2e00f60e206d8e(
+`ifdef USE_POWER_PINS
+        vccd1, vssd1,
+`endif
+ clk, rst, alt_reset, wishbone_insn_in, wishbone_data_in, dmi_addr, dmi_din, dmi_req, dmi_wr, ext_irq, wishbone_insn_out, wishbone_data_out, dmi_dout, dmi_ack, terminated_out);
+`ifdef USE_POWER_PINS
+  inout vccd1;        // User area 1 1.8V supply
+  inout vssd1;        // User area 1 digital ground
+`endif
+  wire [42:0] _00_;
+  wire [106:0] _01_;
+  wire [53:0] _02_;
+  wire _03_;
+  wire [12:0] _04_;
+  wire [9:0] _05_;
+  wire [71:0] _06_;
+  wire [12:0] _07_;
+  wire [306:0] _08_;
+  wire [14:0] _09_;
+  wire [9:0] _10_;
+  wire [106:0] _11_;
+  wire [19:0] _12_;
+  wire [63:0] _13_;
+  wire _14_;
+  wire _15_;
+  input alt_reset;
+  reg alt_reset_d;
+  input clk;
+  wire complete;
+  wire core_rst;
+  wire [36:0] cr_file_to_decode2;
+  wire dbg_core_is_stopped;
+  wire dbg_core_rst;
+  wire dbg_core_stop;
+  wire dbg_gpr_ack;
+  wire [6:0] dbg_gpr_addr;
+  wire [63:0] dbg_gpr_data;
+  wire dbg_gpr_req;
+  wire dbg_icache_rst;
+  wire dcache_stall_out;
+  wire [67:0] dcache_to_loadstore1;
+  wire [66:0] dcache_to_mmu;
+  wire decode1_busy;
+  wire decode1_flush;
+  wire [153:0] decode1_to_decode2;
+  wire [64:0] decode1_to_fetch1;
+  wire decode2_stall_out;
+  wire decode2_to_cr_file;
+  wire [379:0] decode2_to_execute1;
+  wire [23:0] decode2_to_register_file;
+  output dmi_ack;
+  input [3:0] dmi_addr;
+  input [63:0] dmi_din;
+  output [63:0] dmi_dout;
+  input dmi_req;
+  input dmi_wr;
+  wire ex1_busy_out;
+  wire ex1_icache_inval;
+  wire [68:0] execute1_to_fetch1;
+  wire [325:0] execute1_to_loadstore1;
+  wire [193:0] execute1_to_writeback;
+  input ext_irq;
+  wire fetch1_flush;
+  wire fetch1_stall_in;
+  wire [69:0] fetch1_to_icache;
+  wire flush;
+  wire icache_stall_out;
+  wire [98:0] icache_to_decode1;
+  wire [142:0] loadstore1_to_dcache;
+  wire [8:0] loadstore1_to_execute1;
+  wire [144:0] loadstore1_to_mmu;
+  wire [79:0] loadstore1_to_writeback;
+  wire [31:0] log_rd_addr;
+  wire [63:0] log_rd_data;
+  wire [31:0] log_wr_addr;
+  wire [131:0] mmu_to_dcache;
+  wire [130:0] mmu_to_icache;
+  wire [70:0] mmu_to_loadstore1;
+  wire [63:0] msr;
+  wire [191:0] register_file_to_decode2;
+  input rst;
+  reg rst_dbg = 1'h1;
+  reg rst_dcache = 1'h1;
+  reg rst_dec1 = 1'h1;
+  reg rst_dec2 = 1'h1;
+  reg rst_ex1 = 1'h1;
+  reg rst_fetch1 = 1'h1;
+  reg rst_icache = 1'h1;
+  reg rst_ls1 = 1'h1;
+  wire sim_cr_dump;
+  wire terminate;
+  output terminated_out;
+  input [65:0] wishbone_data_in;
+  output [106:0] wishbone_data_out;
+  input [65:0] wishbone_insn_in;
+  output [106:0] wishbone_insn_out;
+  wire [46:0] writeback_to_cr_file;
+  wire [71:0] writeback_to_register_file;
+  assign core_rst = dbg_core_rst | rst;
+  always @(posedge clk)
+    rst_fetch1 <= core_rst;
+  always @(posedge clk)
+    rst_icache <= core_rst;
+  always @(posedge clk)
+    rst_dcache <= core_rst;
+  always @(posedge clk)
+    rst_dec1 <= core_rst;
+  always @(posedge clk)
+    rst_dec2 <= core_rst;
+  always @(posedge clk)
+    rst_ex1 <= core_rst;
+  always @(posedge clk)
+    rst_ls1 <= core_rst;
+  always @(posedge clk)
+    rst_dbg <= rst;
+  always @(posedge clk)
+    alt_reset_d <= alt_reset;
+  assign fetch1_stall_in = icache_stall_out | decode1_busy;
+  assign fetch1_flush = flush | decode1_flush;
+  assign _03_ = dbg_icache_rst | ex1_icache_inval;
+  cr_file_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f cr_file_0 (
+    .clk(clk),
+    .d_in(decode2_to_cr_file),
+    .d_out(cr_file_to_decode2),
+    .log_out(_07_),
+    .sim_dump(sim_cr_dump),
+    .w_in(writeback_to_cr_file)
+  );
+  dcache dcache_0 (
+`ifdef USE_POWER_PINS
+    .vccd1(vccd1),  // User area 1 1.8V power
+    .vssd1(vssd1),  // User area 1 digital ground
+`endif
+    .clk(clk),
+    .d_in(loadstore1_to_dcache),
+    .d_out(dcache_to_loadstore1),
+    .m_in(mmu_to_dcache),
+    .m_out(dcache_to_mmu),
+    .rst(rst_dcache),
+    .stall_out(dcache_stall_out),
+    .wishbone_in(wishbone_data_in),
+    .wishbone_out(_11_)
+  );
+  core_debug_0 debug_0 (
+    .clk(clk),
+    .core_rst(dbg_core_rst),
+    .core_stop(dbg_core_stop),
+    .core_stopped(dbg_core_is_stopped),
+    .dbg_gpr_ack(dbg_gpr_ack),
+    .dbg_gpr_addr(dbg_gpr_addr),
+    .dbg_gpr_data(dbg_gpr_data),
+    .dbg_gpr_req(dbg_gpr_req),
+    .dmi_ack(_14_),
+    .dmi_addr(dmi_addr),
+    .dmi_din(dmi_din),
+    .dmi_dout(_13_),
+    .dmi_req(dmi_req),
+    .dmi_wr(dmi_wr),
+    .icache_rst(dbg_icache_rst),
+    .log_data({ _06_, _07_, _12_, 1'h0, _10_, 5'h00, _09_, _05_, _04_, _02_, _00_ }),
+    .log_read_addr(log_rd_addr),
+    .log_read_data(log_rd_data),
+    .log_write_addr(log_wr_addr),
+    .msr(msr),
+    .nia(fetch1_to_icache[69:6]),
+    .rst(rst_dbg),
+    .terminate(terminate),
+    .terminated_out(_15_)
+  );
+  decode1_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f decode1_0 (
+    .busy_out(decode1_busy),
+    .clk(clk),
+    .d_out(decode1_to_decode2),
+    .f_in(icache_to_decode1),
+    .f_out(decode1_to_fetch1),
+    .flush_in(flush),
+    .flush_out(decode1_flush),
+    .log_out(_04_),
+    .rst(rst_dec1),
+    .stall_in(decode2_stall_out)
+  );
+  decode2_0_0e356ba505631fbf715758bed27d503f8b260e3a decode2_0 (
+    .busy_in(ex1_busy_out),
+    .c_in(cr_file_to_decode2),
+    .c_out(decode2_to_cr_file),
+    .clk(clk),
+    .complete_in(complete),
+    .d_in(decode1_to_decode2),
+    .e_out(decode2_to_execute1),
+    .flush_in(flush),
+    .log_out(_05_),
+    .r_in(register_file_to_decode2),
+    .r_out(decode2_to_register_file),
+    .rst(rst_dec2),
+    .stall_out(decode2_stall_out),
+    .stopped_out(dbg_core_is_stopped)
+  );
+  execute1_0_0e356ba505631fbf715758bed27d503f8b260e3a execute1_0 (
+`ifdef USE_POWER_PINS
+    .vccd1(vccd1),  // User area 1 1.8V power
+    .vssd1(vssd1),  // User area 1 digital ground
+`endif
+    .busy_out(ex1_busy_out),
+    .clk(clk),
+    .dbg_msr_out(msr),
+    .e_in(decode2_to_execute1),
+    .e_out(execute1_to_writeback),
+    .ext_irq_in(ext_irq),
+    .f_out(execute1_to_fetch1),
+    .flush_out(flush),
+    .fp_in(4'h0),
+    .fp_out(_08_),
+    .icache_inval(ex1_icache_inval),
+    .l_in(loadstore1_to_execute1),
+    .l_out(execute1_to_loadstore1),
+    .log_out(_09_),
+    .log_rd_addr(log_rd_addr),
+    .log_rd_data(log_rd_data),
+    .log_wr_addr(log_wr_addr),
+    .rst(rst_ex1),
+    .terminate_out(terminate)
+  );
+  fetch1_05c2030ccbceb505e9c9c1e14c8b4fa317497e84 fetch1_0 (
+    .alt_reset_in(alt_reset_d),
+    .clk(clk),
+    .d_in(decode1_to_fetch1),
+    .e_in(execute1_to_fetch1),
+    .flush_in(fetch1_flush),
+    .i_out(fetch1_to_icache),
+    .log_out(_00_),
+    .rst(rst_fetch1),
+    .stall_in(fetch1_stall_in),
+    .stop_in(dbg_core_stop)
+  );
+  icache icache_0 (
+`ifdef USE_POWER_PINS
+    .vccd1(vccd1),  // User area 1 1.8V power
+    .vssd1(vssd1),  // User area 1 digital ground
+`endif
+    .clk(clk),
+    .flush_in(fetch1_flush),
+    .i_in(fetch1_to_icache),
+    .i_out(icache_to_decode1),
+    .inval_in(_03_),
+    .m_in(mmu_to_icache),
+    .rst(rst_icache),
+    .stall_in(decode1_busy),
+    .stall_out(icache_stall_out),
+    .wishbone_in(wishbone_insn_in),
+    .wishbone_out(_01_)
+  );
+  loadstore1_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f loadstore1_0 (
+    .clk(clk),
+    .d_in(dcache_to_loadstore1),
+    .d_out(loadstore1_to_dcache),
+    .dc_stall(dcache_stall_out),
+    .e_out(loadstore1_to_execute1),
+    .l_in(execute1_to_loadstore1),
+    .l_out(loadstore1_to_writeback),
+    .log_out(_10_),
+    .m_in(mmu_to_loadstore1),
+    .m_out(loadstore1_to_mmu),
+    .rst(rst_ls1)
+  );
+  mmu mmu_0 (
+    .clk(clk),
+    .d_in(dcache_to_mmu),
+    .d_out(mmu_to_dcache),
+    .i_out(mmu_to_icache),
+    .l_in(loadstore1_to_mmu),
+    .l_out(mmu_to_loadstore1),
+    .rst(core_rst)
+  );
+  register_file register_file_0 (
+`ifdef USE_POWER_PINS
+    .vccd1(vccd1),  // User area 1 1.8V power
+    .vssd1(vssd1),  // User area 1 digital ground
+`endif
+    .clk(clk),
+    .d_in(decode2_to_register_file),
+    .d_out(register_file_to_decode2),
+    .w_in(writeback_to_register_file)
+  );
+  writeback writeback_0 (
+    .c_out(writeback_to_cr_file),
+    .clk(clk),
+    .complete_out(complete),
+    .e_in(execute1_to_writeback),
+    .fp_in(114'h00000000000000000000000000000),
+    .l_in(loadstore1_to_writeback),
+    .w_out(writeback_to_register_file)
+  );
+  assign wishbone_insn_out = _01_;
+  assign wishbone_data_out = _11_;
+  assign dmi_dout = _13_;
+  assign dmi_ack = _14_;
+  assign terminated_out = _15_;
+endmodule
+
+module core_debug_0(clk, rst, dmi_addr, dmi_din, dmi_req, dmi_wr, terminate, core_stopped, nia, msr, dbg_gpr_ack, dbg_gpr_data, log_data, log_read_addr, dmi_dout, dmi_ack, core_stop, core_rst, icache_rst, dbg_gpr_req, dbg_gpr_addr, log_read_data, log_write_addr, terminated_out);
+  wire _00_;
+  wire _01_;
+  wire _02_;
+  wire _03_;
+  wire _04_;
+  wire _05_;
+  wire _06_;
+  wire _07_;
+  wire _08_;
+  wire _09_;
+  wire [63:0] _10_;
+  wire _11_;
+  wire _12_;
+  wire _13_;
+  wire _14_;
+  wire _15_;
+  wire _16_;
+  wire _17_;
+  wire _18_;
+  wire _19_;
+  wire _20_;
+  wire _21_;
+  wire _22_;
+  wire _23_;
+  wire [31:0] _24_;
+  wire [6:0] _25_;
+  wire [31:0] _26_;
+  wire _27_;
+  wire _28_;
+  wire _29_;
+  wire _30_;
+  wire _31_;
+  wire [6:0] _32_;
+  wire [31:0] _33_;
+  wire _34_;
+  wire _35_;
+  wire _36_;
+  wire _37_;
+  wire _38_;
+  wire [6:0] _39_;
+  wire [31:0] _40_;
+  wire _41_;
+  wire _42_;
+  wire [1:0] _43_;
+  wire [1:0] _44_;
+  wire _45_;
+  wire _46_;
+  wire _47_;
+  wire _48_;
+  wire _49_;
+  wire _50_;
+  wire [1:0] _51_;
+  wire [29:0] _52_;
+  wire _53_;
+  wire _54_;
+  wire _55_;
+  wire _56_;
+  wire _57_;
+  wire _58_;
+  wire _59_;
+  wire _60_;
+  wire _61_;
+  wire _62_;
+  wire _63_;
+  wire [6:0] _64_;
+  wire [31:0] _65_;
+  wire _66_;
+  wire _67_;
+  wire _68_;
+  wire _69_;
+  input clk;
+  output core_rst;
+  output core_stop;
+  input core_stopped;
+  input dbg_gpr_ack;
+  output [6:0] dbg_gpr_addr;
+  input [63:0] dbg_gpr_data;
+  output dbg_gpr_req;
+  output dmi_ack;
+  input [3:0] dmi_addr;
+  input [63:0] dmi_din;
+  output [63:0] dmi_dout;
+  reg dmi_read_log_data;
+  reg dmi_read_log_data_1;
+  input dmi_req;
+  reg dmi_req_1;
+  input dmi_wr;
+  reg do_icreset;
+  reg do_reset;
+  reg do_step;
+  reg [6:0] gspr_index;
+  output icache_rst;
+  input [255:0] log_data;
+  reg [31:0] log_dmi_addr = 32'd0;
+  input [31:0] log_read_addr;
+  output [63:0] log_read_data;
+  output [31:0] log_write_addr;
+  input [63:0] msr;
+  input [63:0] nia;
+  input rst;
+  reg stopping;
+  input terminate;
+  reg terminated;
+  output terminated_out;
+  assign _00_ = dmi_addr != 4'h5;
+  assign _01_ = _00_ ? dmi_req : dbg_gpr_ack;
+  assign _02_ = dmi_addr == 4'h5;
+  assign _03_ = _02_ ? dmi_req : 1'h0;
+  assign _04_ = dmi_addr == 4'h1;
+  assign _05_ = dmi_addr == 4'h2;
+  assign _06_ = dmi_addr == 4'h3;
+  assign _07_ = dmi_addr == 4'h5;
+  assign _08_ = dmi_addr == 4'h6;
+  assign _09_ = dmi_addr == 4'h7;
+  function [63:0] \19764 ;
+    input [63:0] a;
+    input [383:0] b;
+    input [5:0] s;
+    (* parallel_case *)
+    casez (s)
+      6'b?????1:
+        \19764  = b[63:0];
+      6'b????1?:
+        \19764  = b[127:64];
+      6'b???1??:
+        \19764  = b[191:128];
+      6'b??1???:
+        \19764  = b[255:192];
+      6'b?1????:
+        \19764  = b[319:256];
+      6'b1?????:
+        \19764  = b[383:320];
+      default:
+        \19764  = a;
+    endcase
+  endfunction
+  assign _10_ = \19764 (64'h0000000000000000, { 96'h000000000000000000000001, log_dmi_addr, dbg_gpr_data, msr, nia, 61'h0000000000000000, terminated, core_stopped, stopping }, { _09_, _08_, _07_, _06_, _05_, _04_ });
+  assign _11_ = ~ dmi_req_1;
+  assign _12_ = dmi_req & _11_;
+  assign _13_ = dmi_addr == 4'h0;
+  assign _14_ = dmi_din[1] ? 1'h1 : 1'h0;
+  assign _15_ = dmi_din[1] ? 1'h0 : terminated;
+  assign _16_ = dmi_din[0] ? 1'h1 : stopping;
+  assign _17_ = dmi_din[3] ? 1'h1 : 1'h0;
+  assign _18_ = dmi_din[3] ? 1'h0 : _15_;
+  assign _19_ = dmi_din[2] ? 1'h1 : 1'h0;
+  assign _20_ = dmi_din[4] ? 1'h0 : _16_;
+  assign _21_ = dmi_din[4] ? 1'h0 : _18_;
+  assign _22_ = dmi_addr == 4'h4;
+  assign _23_ = dmi_addr == 4'h6;
+  assign _24_ = _23_ ? dmi_din[31:0] : log_dmi_addr;
+  assign _25_ = _22_ ? dmi_din[6:0] : gspr_index;
+  assign _26_ = _22_ ? log_dmi_addr : _24_;
+  assign _27_ = _45_ ? _20_ : stopping;
+  assign _28_ = _13_ ? _17_ : 1'h0;
+  assign _29_ = _13_ ? _14_ : 1'h0;
+  assign _30_ = _13_ ? _19_ : 1'h0;
+  assign _31_ = _49_ ? _21_ : terminated;
+  assign _32_ = _13_ ? gspr_index : _25_;
+  assign _33_ = _13_ ? log_dmi_addr : _26_;
+  assign _34_ = dmi_wr & _13_;
+  assign _35_ = dmi_wr ? _28_ : 1'h0;
+  assign _36_ = dmi_wr ? _29_ : 1'h0;
+  assign _37_ = dmi_wr ? _30_ : 1'h0;
+  assign _38_ = dmi_wr & _13_;
+  assign _39_ = _50_ ? _32_ : gspr_index;
+  assign _40_ = dmi_wr ? _33_ : log_dmi_addr;
+  assign _41_ = ~ dmi_read_log_data;
+  assign _42_ = _41_ & dmi_read_log_data_1;
+  assign _43_ = log_dmi_addr[1:0] + 2'h1;
+  assign _44_ = _42_ ? _43_ : log_dmi_addr[1:0];
+  assign _45_ = _12_ & _34_;
+  assign _46_ = _12_ ? _35_ : 1'h0;
+  assign _47_ = _12_ ? _36_ : 1'h0;
+  assign _48_ = _12_ ? _37_ : 1'h0;
+  assign _49_ = _12_ & _38_;
+  assign _50_ = _12_ & dmi_wr;
+  assign _51_ = _12_ ? _40_[1:0] : _44_;
+  assign _52_ = _12_ ? _40_[31:2] : log_dmi_addr[31:2];
+  assign _53_ = dmi_addr == 4'h7;
+  assign _54_ = dmi_req & _53_;
+  assign _55_ = _54_ ? 1'h1 : 1'h0;
+  assign _56_ = terminate ? 1'h1 : _27_;
+  assign _57_ = terminate ? 1'h1 : _31_;
+  assign _58_ = rst ? dmi_req_1 : dmi_req;
+  assign _59_ = rst ? 1'h0 : _56_;
+  assign _60_ = rst ? 1'h0 : _46_;
+  assign _61_ = rst ? 1'h0 : _47_;
+  assign _62_ = rst ? 1'h0 : _48_;
+  assign _63_ = rst ? 1'h0 : _57_;
+  assign _64_ = rst ? gspr_index : _39_;
+  assign _65_ = rst ? log_dmi_addr : { _52_, _51_ };
+  assign _66_ = rst ? dmi_read_log_data : _55_;
+  assign _67_ = rst ? dmi_read_log_data_1 : dmi_read_log_data;
+  always @(posedge clk)
+    dmi_req_1 <= _58_;
+  always @(posedge clk)
+    stopping <= _59_;
+  always @(posedge clk)
+    do_step <= _60_;
+  always @(posedge clk)
+    do_reset <= _61_;
+  always @(posedge clk)
+    do_icreset <= _62_;
+  always @(posedge clk)
+    terminated <= _63_;
+  always @(posedge clk)
+    gspr_index <= _64_;
+  always @(posedge clk)
+    log_dmi_addr <= _65_;
+  always @(posedge clk)
+    dmi_read_log_data <= _66_;
+  always @(posedge clk)
+    dmi_read_log_data_1 <= _67_;
+  assign _68_ = ~ do_step;
+  assign _69_ = stopping & _68_;
+  assign dmi_dout = _10_;
+  assign dmi_ack = _01_;
+  assign core_stop = _69_;
+  assign core_rst = do_reset;
+  assign icache_rst = do_icreset;
+  assign dbg_gpr_req = _03_;
+  assign dbg_gpr_addr = gspr_index;
+  assign log_read_data = 64'h0000000000000000;
+  assign log_write_addr = 32'd1;
+  assign terminated_out = terminated;
+endmodule
+
+module cr_file_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, d_in, w_in, sim_dump, d_out, log_out);
+  wire [3:0] _0_;
+  wire [3:0] _1_;
+  wire [3:0] _2_;
+  wire [3:0] _3_;
+  wire [3:0] _4_;
+  wire [3:0] _5_;
+  wire [3:0] _6_;
+  wire [3:0] _7_;
+  wire [31:0] _8_;
+  wire [4:0] _9_;
+  input clk;
+  reg [31:0] crs = 32'd0;
+  input d_in;
+  output [36:0] d_out;
+  output [12:0] log_out;
+  input sim_dump;
+  input [46:0] w_in;
+  reg [4:0] xerc = 5'h00;
+  wire [4:0] xerc_updated;
+  assign _0_ = w_in[1] ? w_in[12:9] : crs[3:0];
+  assign _1_ = w_in[2] ? w_in[16:13] : crs[7:4];
+  assign _2_ = w_in[3] ? w_in[20:17] : crs[11:8];
+  assign _3_ = w_in[4] ? w_in[24:21] : crs[15:12];
+  assign _4_ = w_in[5] ? w_in[28:25] : crs[19:16];
+  assign _5_ = w_in[6] ? w_in[32:29] : crs[23:20];
+  assign _6_ = w_in[7] ? w_in[36:33] : crs[27:24];
+  assign _7_ = w_in[8] ? w_in[40:37] : crs[31:28];
+  assign xerc_updated = w_in[41] ? w_in[46:42] : xerc;
+  assign _8_ = w_in[0] ? { _7_, _6_, _5_, _4_, _3_, _2_, _1_, _0_ } : crs;
+  always @(posedge clk)
+    crs <= _8_;
+  assign _9_ = w_in[41] ? xerc_updated : xerc;
+  always @(posedge clk)
+    xerc <= _9_;
+  assign d_out = { xerc_updated, _7_, _6_, _5_, _4_, _3_, _2_, _1_, _0_ };
+  assign log_out = 13'hzzzz;
+endmodule
+
+module cr_hazard_1(clk, busy_in, deferred, complete_in, flush_in, issuing, cr_read_in, cr_write_in, bypassable, stall_out, use_bypass);
+  wire _00_;
+  wire _01_;
+  wire _02_;
+  wire _03_;
+  wire _04_;
+  wire _05_;
+  wire _06_;
+  wire _07_;
+  wire _08_;
+  wire _09_;
+  wire _10_;
+  wire _11_;
+  wire _12_;
+  wire _13_;
+  wire _14_;
+  wire _15_;
+  wire _16_;
+  wire _17_;
+  wire _18_;
+  wire _19_;
+  wire _20_;
+  input busy_in;
+  input bypassable;
+  input clk;
+  input complete_in;
+  input cr_read_in;
+  input cr_write_in;
+  input deferred;
+  input flush_in;
+  input issuing;
+  reg [3:0] r = 4'h0;
+  output stall_out;
+  output use_bypass;
+  always @(posedge clk)
+    r <= { _20_, _18_, _19_, _16_ };
+  assign _00_ = complete_in ? 1'h0 : r[0];
+  assign _01_ = r[3] ? 1'h0 : 1'h1;
+  assign _02_ = r[3] ? 1'h1 : 1'h0;
+  assign _03_ = r[2] ? _01_ : 1'h0;
+  assign _04_ = r[2] ? _02_ : 1'h0;
+  assign _05_ = r[1] ? _03_ : 1'h1;
+  assign _06_ = _08_ ? 1'h1 : _04_;
+  assign _07_ = _00_ ? _05_ : _03_;
+  assign _08_ = _00_ & r[1];
+  assign _09_ = cr_read_in ? _07_ : 1'h0;
+  assign _10_ = cr_read_in ? _06_ : 1'h0;
+  assign _11_ = ~ busy_in;
+  assign _12_ = ~ deferred;
+  assign _13_ = _12_ & issuing;
+  assign _14_ = _11_ ? 1'h0 : r[2];
+  assign _15_ = _11_ ? r[2] : _00_;
+  assign _16_ = flush_in ? 1'h0 : _15_;
+  assign _17_ = _13_ ? cr_write_in : _14_;
+  assign _18_ = flush_in ? 1'h0 : _17_;
+  assign _19_ = _11_ ? r[3] : r[1];
+  assign _20_ = _13_ ? bypassable : r[3];
+  assign stall_out = _09_;
+  assign use_bypass = _10_;
+endmodule
+
+
+module decode1_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, rst, stall_in, flush_in, f_in, busy_out, flush_out, f_out, d_out, log_out);
+  wire _000_;
+  wire [153:0] _001_;
+  wire _002_;
+  wire [43:0] _003_;
+  wire _004_;
+  wire _005_;
+  wire _006_;
+  wire _007_;
+  wire _008_;
+  wire [153:0] _009_;
+  wire [43:0] _010_;
+  wire [153:0] _011_;
+  wire _012_;
+  wire [152:0] _013_;
+  wire [43:0] _014_;
+  wire [43:0] _015_;
+  wire _016_;
+  wire [152:0] _017_;
+  wire _018_;
+  wire [152:0] _019_;
+  wire [43:0] _020_;
+  wire [43:0] _021_;
+  wire [153:0] _022_;
+  wire [153:0] _023_;
+  wire [43:0] _024_;
+  wire [43:0] _025_;
+  wire [5:0] _026_;
+  wire [10:0] _027_;
+  wire _028_;
+  wire [5:0] _029_;
+  wire _030_;
+  wire [9:0] _031_;
+  wire _032_;
+  wire _033_;
+  wire _034_;
+  wire _035_;
+  wire _036_;
+  wire _037_;
+  wire _038_;
+  wire _039_;
+  wire _040_;
+  wire _041_;
+  wire _042_;
+  wire _043_;
+  wire _044_;
+  wire _045_;
+  wire _046_;
+  wire _047_;
+  wire _048_;
+  wire [6:0] _049_;
+  wire [4:0] _050_;
+  wire [4:0] _051_;
+  wire [6:0] _052_;
+  wire [9:0] _053_;
+  wire _054_;
+  wire _055_;
+  wire _056_;
+  wire _057_;
+  wire _058_;
+  wire _059_;
+  wire _060_;
+  wire _061_;
+  wire _062_;
+  wire [1:0] _063_;
+  wire _064_;
+  wire [1:0] _065_;
+  wire [1:0] _066_;
+  wire [1:0] _067_;
+  wire [1:0] _068_;
+  wire _069_;
+  wire _070_;
+  wire [6:0] _071_;
+  wire _072_;
+  wire _073_;
+  wire [9:0] _074_;
+  wire _075_;
+  wire [2:0] _076_;
+  wire _077_;
+  wire _078_;
+  wire [6:0] _079_;
+  wire _080_;
+  wire _081_;
+  wire [6:0] _082_;
+  wire [6:0] _083_;
+  wire [13:0] _084_;
+  wire _085_;
+  wire [3:0] _086_;
+  wire _087_;
+  wire [31:0] _088_;
+  wire _089_;
+  wire [41:0] _090_;
+  wire _091_;
+  wire [1:0] _092_;
+  wire _093_;
+  wire _094_;
+  wire [1:0] _095_;
+  wire _096_;
+  wire _097_;
+  wire [6:0] _098_;
+  wire [6:0] _099_;
+  wire [40:0] _100_;
+  wire _101_;
+  wire _102_;
+  wire [1:0] _103_;
+  wire [38:0] _104_;
+  wire [1:0] _105_;
+  wire [23:0] _106_;
+  wire _107_;
+  wire _108_;
+  wire _109_;
+  wire _110_;
+  wire [41:0] _111_;
+  wire [61:0] _112_;
+  wire [61:0] _113_;
+  wire _114_;
+  wire _115_;
+  wire _116_;
+  wire _117_;
+  wire _118_;
+  wire [1:0] _119_;
+  wire [1:0] _120_;
+  wire _121_;
+  wire _122_;
+  wire [37:0] _123_;
+  wire [2623:0] _124_;
+  wire [40:0] _125_;
+  wire [2047:0] _126_;
+  wire _127_;
+  wire [2623:0] _128_;
+  wire [40:0] _129_;
+  wire [41983:0] _130_;
+  wire [40:0] _131_;
+  wire [1023:0] _132_;
+  wire _133_;
+  wire [327:0] _134_;
+  wire [40:0] _135_;
+  wire [655:0] _136_;
+  wire [40:0] _137_;
+  wire [163:0] _138_;
+  wire [40:0] _139_;
+  wire [163:0] _140_;
+  wire [40:0] _141_;
+  output busy_out;
+  input clk;
+  output [153:0] d_out;
+  input [98:0] f_in;
+  output [64:0] f_out;
+  input flush_in;
+  output flush_out;
+  output [12:0] log_out;
+  reg [153:0] r;
+  reg [43:0] ri;
+  input rst;
+  reg [153:0] s;
+  reg [43:0] si;
+  input stall_in;
+  reg [40:0] \$mem$\8810  [63:0];
+  reg [0:0] \$mem$\8812  [2047:0];
+  reg [40:0] \$mem$\8814  [63:0];
+  reg [40:0] \$mem$\8816  [1023:0];
+  reg [0:0] \$mem$\8818  [1023:0];
+  reg [40:0] \$mem$\8820  [7:0];
+  reg [40:0] \$mem$\8822  [15:0];
+  reg [40:0] \$mem$\8824  [3:0];
+  reg [40:0] \$mem$\8826  [3:0];
+  reg [40:0] \8810  [63:0];
+  initial begin
+    \8810 [0] = 41'h00000000000;
+    \8810 [1] = 41'h00000000000;
+    \8810 [2] = 41'h00000000000;
+    \8810 [3] = 41'h00000000000;
+    \8810 [4] = 41'h00000000000;
+    \8810 [5] = 41'h00000000000;
+    \8810 [6] = 41'h00000000000;
+    \8810 [7] = 41'h00000000000;
+    \8810 [8] = 41'h00240021a8a;
+    \8810 [9] = 41'h00040021a8a;
+    \8810 [10] = 41'h00a30021a8a;
+    \8810 [11] = 41'h00830021a8a;
+    \8810 [12] = 41'h00240101a86;
+    \8810 [13] = 41'h00040101a86;
+    \8810 [14] = 41'h00a30101a86;
+    \8810 [15] = 41'h00830101a86;
+    \8810 [16] = 41'h00000000000;
+    \8810 [17] = 41'h00000000000;
+    \8810 [18] = 41'h00220009a82;
+    \8810 [19] = 41'h00020009a82;
+    \8810 [20] = 41'h00320041a7e;
+    \8810 [21] = 41'h00120041a7e;
+    \8810 [22] = 41'h00220041a7e;
+    \8810 [23] = 41'h00020041a7e;
+    \8810 [24] = 41'h00210009a82;
+    \8810 [25] = 41'h00010009a82;
+    \8810 [26] = 41'h00230009a82;
+    \8810 [27] = 41'h00030009a82;
+    \8810 [28] = 41'h00210041a7e;
+    \8810 [29] = 41'h00010041a7e;
+    \8810 [30] = 41'h00230041a7e;
+    \8810 [31] = 41'h00030041a7e;
+    \8810 [32] = 41'h00000000000;
+    \8810 [33] = 41'h00000000000;
+    \8810 [34] = 41'h0200008a80d;
+    \8810 [35] = 41'h0200008900d;
+    \8810 [36] = 41'h0000008a8f1;
+    \8810 [37] = 41'h000000890f1;
+    \8810 [38] = 41'h0000008a8b9;
+    \8810 [39] = 41'h000000890b9;
+    \8810 [40] = 41'h048000888c9;
+    \8810 [41] = 41'h00000000000;
+    \8810 [42] = 41'h0480008e0c9;
+    \8810 [43] = 41'h0480008e1c9;
+    \8810 [44] = 41'h00000000000;
+    \8810 [45] = 41'h08000003015;
+    \8810 [46] = 41'h000000000d5;
+    \8810 [47] = 41'h080002c3b19;
+    \8810 [48] = 41'h00000042209;
+    \8810 [49] = 41'h00000041a09;
+    \8810 [50] = 41'h02008041909;
+    \8810 [51] = 41'h00008041909;
+    \8810 [52] = 41'h01006c01925;
+    \8810 [53] = 41'h00006c01125;
+    \8810 [54] = 41'h00000000000;
+    \8810 [55] = 41'h0000e841909;
+    \8810 [56] = 41'h010000419ad;
+    \8810 [57] = 41'h00000000000;
+    \8810 [58] = 41'h00000000000;
+    \8810 [59] = 41'h00000000000;
+    \8810 [60] = 41'h108000019ed;
+    \8810 [61] = 41'h100000019ed;
+    \8810 [62] = 41'h00000000000;
+    \8810 [63] = 41'h10000000011;
+  end
+  assign _125_ = \8810 [_026_];
+  reg [0:0] \8812  [2047:0];
+  initial begin
+    \8812 [0] = 1'h0;
+    \8812 [1] = 1'h0;
+    \8812 [2] = 1'h0;
+    \8812 [3] = 1'h0;
+    \8812 [4] = 1'h0;
+    \8812 [5] = 1'h0;
+    \8812 [6] = 1'h0;
+    \8812 [7] = 1'h0;
+    \8812 [8] = 1'h0;
+    \8812 [9] = 1'h0;
+    \8812 [10] = 1'h0;
+    \8812 [11] = 1'h0;
+    \8812 [12] = 1'h0;
+    \8812 [13] = 1'h0;
+    \8812 [14] = 1'h0;
+    \8812 [15] = 1'h0;
+    \8812 [16] = 1'h0;
+    \8812 [17] = 1'h0;
+    \8812 [18] = 1'h0;
+    \8812 [19] = 1'h0;
+    \8812 [20] = 1'h0;
+    \8812 [21] = 1'h0;
+    \8812 [22] = 1'h0;
+    \8812 [23] = 1'h0;
+    \8812 [24] = 1'h0;
+    \8812 [25] = 1'h0;
+    \8812 [26] = 1'h0;
+    \8812 [27] = 1'h0;
+    \8812 [28] = 1'h0;
+    \8812 [29] = 1'h0;
+    \8812 [30] = 1'h0;
+    \8812 [31] = 1'h0;
+    \8812 [32] = 1'h0;
+    \8812 [33] = 1'h0;
+    \8812 [34] = 1'h0;
+    \8812 [35] = 1'h0;
+    \8812 [36] = 1'h0;
+    \8812 [37] = 1'h0;
+    \8812 [38] = 1'h0;
+    \8812 [39] = 1'h0;
+    \8812 [40] = 1'h0;
+    \8812 [41] = 1'h0;
+    \8812 [42] = 1'h0;
+    \8812 [43] = 1'h0;
+    \8812 [44] = 1'h0;
+    \8812 [45] = 1'h0;
+    \8812 [46] = 1'h0;
+    \8812 [47] = 1'h0;
+    \8812 [48] = 1'h0;
+    \8812 [49] = 1'h0;
+    \8812 [50] = 1'h0;
+    \8812 [51] = 1'h0;
+    \8812 [52] = 1'h0;
+    \8812 [53] = 1'h0;
+    \8812 [54] = 1'h0;
+    \8812 [55] = 1'h0;
+    \8812 [56] = 1'h0;
+    \8812 [57] = 1'h0;
+    \8812 [58] = 1'h0;
+    \8812 [59] = 1'h0;
+    \8812 [60] = 1'h0;
+    \8812 [61] = 1'h0;
+    \8812 [62] = 1'h0;
+    \8812 [63] = 1'h0;
+    \8812 [64] = 1'h0;
+    \8812 [65] = 1'h0;
+    \8812 [66] = 1'h0;
+    \8812 [67] = 1'h0;
+    \8812 [68] = 1'h0;
+    \8812 [69] = 1'h0;
+    \8812 [70] = 1'h0;
+    \8812 [71] = 1'h0;
+    \8812 [72] = 1'h0;
+    \8812 [73] = 1'h0;
+    \8812 [74] = 1'h0;
+    \8812 [75] = 1'h0;
+    \8812 [76] = 1'h0;
+    \8812 [77] = 1'h0;
+    \8812 [78] = 1'h0;
+    \8812 [79] = 1'h0;
+    \8812 [80] = 1'h0;
+    \8812 [81] = 1'h0;
+    \8812 [82] = 1'h0;
+    \8812 [83] = 1'h0;
+    \8812 [84] = 1'h0;
+    \8812 [85] = 1'h0;
+    \8812 [86] = 1'h0;
+    \8812 [87] = 1'h0;
+    \8812 [88] = 1'h0;
+    \8812 [89] = 1'h0;
+    \8812 [90] = 1'h0;
+    \8812 [91] = 1'h0;
+    \8812 [92] = 1'h0;
+    \8812 [93] = 1'h0;
+    \8812 [94] = 1'h0;
+    \8812 [95] = 1'h0;
+    \8812 [96] = 1'h0;
+    \8812 [97] = 1'h0;
+    \8812 [98] = 1'h0;
+    \8812 [99] = 1'h0;
+    \8812 [100] = 1'h0;
+    \8812 [101] = 1'h0;
+    \8812 [102] = 1'h0;
+    \8812 [103] = 1'h0;
+    \8812 [104] = 1'h0;
+    \8812 [105] = 1'h0;
+    \8812 [106] = 1'h0;
+    \8812 [107] = 1'h0;
+    \8812 [108] = 1'h0;
+    \8812 [109] = 1'h0;
+    \8812 [110] = 1'h0;
+    \8812 [111] = 1'h0;
+    \8812 [112] = 1'h0;
+    \8812 [113] = 1'h0;
+    \8812 [114] = 1'h0;
+    \8812 [115] = 1'h0;
+    \8812 [116] = 1'h0;
+    \8812 [117] = 1'h0;
+    \8812 [118] = 1'h0;
+    \8812 [119] = 1'h0;
+    \8812 [120] = 1'h0;
+    \8812 [121] = 1'h0;
+    \8812 [122] = 1'h0;
+    \8812 [123] = 1'h0;
+    \8812 [124] = 1'h0;
+    \8812 [125] = 1'h0;
+    \8812 [126] = 1'h0;
+    \8812 [127] = 1'h0;
+    \8812 [128] = 1'h0;
+    \8812 [129] = 1'h0;
+    \8812 [130] = 1'h0;
+    \8812 [131] = 1'h0;
+    \8812 [132] = 1'h0;
+    \8812 [133] = 1'h0;
+    \8812 [134] = 1'h0;
+    \8812 [135] = 1'h0;
+    \8812 [136] = 1'h0;
+    \8812 [137] = 1'h0;
+    \8812 [138] = 1'h0;
+    \8812 [139] = 1'h0;
+    \8812 [140] = 1'h0;
+    \8812 [141] = 1'h0;
+    \8812 [142] = 1'h0;
+    \8812 [143] = 1'h0;
+    \8812 [144] = 1'h0;
+    \8812 [145] = 1'h0;
+    \8812 [146] = 1'h0;
+    \8812 [147] = 1'h0;
+    \8812 [148] = 1'h0;
+    \8812 [149] = 1'h0;
+    \8812 [150] = 1'h0;
+    \8812 [151] = 1'h0;
+    \8812 [152] = 1'h0;
+    \8812 [153] = 1'h0;
+    \8812 [154] = 1'h0;
+    \8812 [155] = 1'h0;
+    \8812 [156] = 1'h0;
+    \8812 [157] = 1'h0;
+    \8812 [158] = 1'h0;
+    \8812 [159] = 1'h0;
+    \8812 [160] = 1'h0;
+    \8812 [161] = 1'h0;
+    \8812 [162] = 1'h0;
+    \8812 [163] = 1'h0;
+    \8812 [164] = 1'h0;
+    \8812 [165] = 1'h0;
+    \8812 [166] = 1'h0;
+    \8812 [167] = 1'h0;
+    \8812 [168] = 1'h0;
+    \8812 [169] = 1'h0;
+    \8812 [170] = 1'h0;
+    \8812 [171] = 1'h0;
+    \8812 [172] = 1'h0;
+    \8812 [173] = 1'h0;
+    \8812 [174] = 1'h0;
+    \8812 [175] = 1'h0;
+    \8812 [176] = 1'h0;
+    \8812 [177] = 1'h0;
+    \8812 [178] = 1'h0;
+    \8812 [179] = 1'h0;
+    \8812 [180] = 1'h0;
+    \8812 [181] = 1'h0;
+    \8812 [182] = 1'h0;
+    \8812 [183] = 1'h0;
+    \8812 [184] = 1'h0;
+    \8812 [185] = 1'h0;
+    \8812 [186] = 1'h0;
+    \8812 [187] = 1'h0;
+    \8812 [188] = 1'h0;
+    \8812 [189] = 1'h0;
+    \8812 [190] = 1'h0;
+    \8812 [191] = 1'h0;
+    \8812 [192] = 1'h0;
+    \8812 [193] = 1'h0;
+    \8812 [194] = 1'h0;
+    \8812 [195] = 1'h0;
+    \8812 [196] = 1'h0;
+    \8812 [197] = 1'h0;
+    \8812 [198] = 1'h0;
+    \8812 [199] = 1'h0;
+    \8812 [200] = 1'h0;
+    \8812 [201] = 1'h0;
+    \8812 [202] = 1'h0;
+    \8812 [203] = 1'h0;
+    \8812 [204] = 1'h0;
+    \8812 [205] = 1'h0;
+    \8812 [206] = 1'h0;
+    \8812 [207] = 1'h0;
+    \8812 [208] = 1'h0;
+    \8812 [209] = 1'h0;
+    \8812 [210] = 1'h0;
+    \8812 [211] = 1'h0;
+    \8812 [212] = 1'h0;
+    \8812 [213] = 1'h0;
+    \8812 [214] = 1'h0;
+    \8812 [215] = 1'h0;
+    \8812 [216] = 1'h0;
+    \8812 [217] = 1'h0;
+    \8812 [218] = 1'h0;
+    \8812 [219] = 1'h0;
+    \8812 [220] = 1'h0;
+    \8812 [221] = 1'h0;
+    \8812 [222] = 1'h0;
+    \8812 [223] = 1'h0;
+    \8812 [224] = 1'h0;
+    \8812 [225] = 1'h0;
+    \8812 [226] = 1'h0;
+    \8812 [227] = 1'h0;
+    \8812 [228] = 1'h0;
+    \8812 [229] = 1'h0;
+    \8812 [230] = 1'h0;
+    \8812 [231] = 1'h0;
+    \8812 [232] = 1'h0;
+    \8812 [233] = 1'h0;
+    \8812 [234] = 1'h0;
+    \8812 [235] = 1'h0;
+    \8812 [236] = 1'h0;
+    \8812 [237] = 1'h0;
+    \8812 [238] = 1'h0;
+    \8812 [239] = 1'h0;
+    \8812 [240] = 1'h0;
+    \8812 [241] = 1'h0;
+    \8812 [242] = 1'h0;
+    \8812 [243] = 1'h0;
+    \8812 [244] = 1'h0;
+    \8812 [245] = 1'h0;
+    \8812 [246] = 1'h0;
+    \8812 [247] = 1'h0;
+    \8812 [248] = 1'h0;
+    \8812 [249] = 1'h0;
+    \8812 [250] = 1'h0;
+    \8812 [251] = 1'h0;
+    \8812 [252] = 1'h0;
+    \8812 [253] = 1'h0;
+    \8812 [254] = 1'h0;
+    \8812 [255] = 1'h0;
+    \8812 [256] = 1'h0;
+    \8812 [257] = 1'h0;
+    \8812 [258] = 1'h0;
+    \8812 [259] = 1'h0;
+    \8812 [260] = 1'h0;
+    \8812 [261] = 1'h0;
+    \8812 [262] = 1'h0;
+    \8812 [263] = 1'h0;
+    \8812 [264] = 1'h0;
+    \8812 [265] = 1'h0;
+    \8812 [266] = 1'h0;
+    \8812 [267] = 1'h0;
+    \8812 [268] = 1'h0;
+    \8812 [269] = 1'h0;
+    \8812 [270] = 1'h0;
+    \8812 [271] = 1'h0;
+    \8812 [272] = 1'h0;
+    \8812 [273] = 1'h0;
+    \8812 [274] = 1'h0;
+    \8812 [275] = 1'h0;
+    \8812 [276] = 1'h0;
+    \8812 [277] = 1'h0;
+    \8812 [278] = 1'h0;
+    \8812 [279] = 1'h0;
+    \8812 [280] = 1'h0;
+    \8812 [281] = 1'h0;
+    \8812 [282] = 1'h0;
+    \8812 [283] = 1'h0;
+    \8812 [284] = 1'h0;
+    \8812 [285] = 1'h0;
+    \8812 [286] = 1'h0;
+    \8812 [287] = 1'h0;
+    \8812 [288] = 1'h0;
+    \8812 [289] = 1'h0;
+    \8812 [290] = 1'h0;
+    \8812 [291] = 1'h0;
+    \8812 [292] = 1'h0;
+    \8812 [293] = 1'h0;
+    \8812 [294] = 1'h0;
+    \8812 [295] = 1'h0;
+    \8812 [296] = 1'h0;
+    \8812 [297] = 1'h0;
+    \8812 [298] = 1'h0;
+    \8812 [299] = 1'h0;
+    \8812 [300] = 1'h0;
+    \8812 [301] = 1'h0;
+    \8812 [302] = 1'h0;
+    \8812 [303] = 1'h0;
+    \8812 [304] = 1'h0;
+    \8812 [305] = 1'h0;
+    \8812 [306] = 1'h0;
+    \8812 [307] = 1'h0;
+    \8812 [308] = 1'h0;
+    \8812 [309] = 1'h0;
+    \8812 [310] = 1'h0;
+    \8812 [311] = 1'h0;
+    \8812 [312] = 1'h0;
+    \8812 [313] = 1'h0;
+    \8812 [314] = 1'h0;
+    \8812 [315] = 1'h0;
+    \8812 [316] = 1'h0;
+    \8812 [317] = 1'h0;
+    \8812 [318] = 1'h0;
+    \8812 [319] = 1'h0;
+    \8812 [320] = 1'h0;
+    \8812 [321] = 1'h0;
+    \8812 [322] = 1'h0;
+    \8812 [323] = 1'h0;
+    \8812 [324] = 1'h0;
+    \8812 [325] = 1'h0;
+    \8812 [326] = 1'h0;
+    \8812 [327] = 1'h0;
+    \8812 [328] = 1'h0;
+    \8812 [329] = 1'h0;
+    \8812 [330] = 1'h0;
+    \8812 [331] = 1'h0;
+    \8812 [332] = 1'h0;
+    \8812 [333] = 1'h0;
+    \8812 [334] = 1'h0;
+    \8812 [335] = 1'h0;
+    \8812 [336] = 1'h0;
+    \8812 [337] = 1'h0;
+    \8812 [338] = 1'h0;
+    \8812 [339] = 1'h0;
+    \8812 [340] = 1'h0;
+    \8812 [341] = 1'h0;
+    \8812 [342] = 1'h0;
+    \8812 [343] = 1'h0;
+    \8812 [344] = 1'h0;
+    \8812 [345] = 1'h0;
+    \8812 [346] = 1'h0;
+    \8812 [347] = 1'h0;
+    \8812 [348] = 1'h0;
+    \8812 [349] = 1'h0;
+    \8812 [350] = 1'h0;
+    \8812 [351] = 1'h0;
+    \8812 [352] = 1'h0;
+    \8812 [353] = 1'h0;
+    \8812 [354] = 1'h0;
+    \8812 [355] = 1'h0;
+    \8812 [356] = 1'h0;
+    \8812 [357] = 1'h0;
+    \8812 [358] = 1'h0;
+    \8812 [359] = 1'h0;
+    \8812 [360] = 1'h0;
+    \8812 [361] = 1'h0;
+    \8812 [362] = 1'h0;
+    \8812 [363] = 1'h0;
+    \8812 [364] = 1'h0;
+    \8812 [365] = 1'h0;
+    \8812 [366] = 1'h0;
+    \8812 [367] = 1'h0;
+    \8812 [368] = 1'h0;
+    \8812 [369] = 1'h0;
+    \8812 [370] = 1'h0;
+    \8812 [371] = 1'h0;
+    \8812 [372] = 1'h0;
+    \8812 [373] = 1'h0;
+    \8812 [374] = 1'h0;
+    \8812 [375] = 1'h0;
+    \8812 [376] = 1'h0;
+    \8812 [377] = 1'h0;
+    \8812 [378] = 1'h0;
+    \8812 [379] = 1'h0;
+    \8812 [380] = 1'h0;
+    \8812 [381] = 1'h0;
+    \8812 [382] = 1'h0;
+    \8812 [383] = 1'h0;
+    \8812 [384] = 1'h1;
+    \8812 [385] = 1'h1;
+    \8812 [386] = 1'h1;
+    \8812 [387] = 1'h1;
+    \8812 [388] = 1'h1;
+    \8812 [389] = 1'h1;
+    \8812 [390] = 1'h1;
+    \8812 [391] = 1'h1;
+    \8812 [392] = 1'h1;
+    \8812 [393] = 1'h1;
+    \8812 [394] = 1'h1;
+    \8812 [395] = 1'h1;
+    \8812 [396] = 1'h1;
+    \8812 [397] = 1'h1;
+    \8812 [398] = 1'h1;
+    \8812 [399] = 1'h1;
+    \8812 [400] = 1'h1;
+    \8812 [401] = 1'h1;
+    \8812 [402] = 1'h1;
+    \8812 [403] = 1'h1;
+    \8812 [404] = 1'h1;
+    \8812 [405] = 1'h1;
+    \8812 [406] = 1'h1;
+    \8812 [407] = 1'h1;
+    \8812 [408] = 1'h1;
+    \8812 [409] = 1'h1;
+    \8812 [410] = 1'h1;
+    \8812 [411] = 1'h1;
+    \8812 [412] = 1'h1;
+    \8812 [413] = 1'h1;
+    \8812 [414] = 1'h1;
+    \8812 [415] = 1'h1;
+    \8812 [416] = 1'h0;
+    \8812 [417] = 1'h0;
+    \8812 [418] = 1'h0;
+    \8812 [419] = 1'h0;
+    \8812 [420] = 1'h0;
+    \8812 [421] = 1'h0;
+    \8812 [422] = 1'h0;
+    \8812 [423] = 1'h0;
+    \8812 [424] = 1'h0;
+    \8812 [425] = 1'h0;
+    \8812 [426] = 1'h0;
+    \8812 [427] = 1'h0;
+    \8812 [428] = 1'h0;
+    \8812 [429] = 1'h0;
+    \8812 [430] = 1'h0;
+    \8812 [431] = 1'h0;
+    \8812 [432] = 1'h0;
+    \8812 [433] = 1'h0;
+    \8812 [434] = 1'h0;
+    \8812 [435] = 1'h0;
+    \8812 [436] = 1'h0;
+    \8812 [437] = 1'h0;
+    \8812 [438] = 1'h0;
+    \8812 [439] = 1'h0;
+    \8812 [440] = 1'h0;
+    \8812 [441] = 1'h0;
+    \8812 [442] = 1'h0;
+    \8812 [443] = 1'h0;
+    \8812 [444] = 1'h0;
+    \8812 [445] = 1'h0;
+    \8812 [446] = 1'h0;
+    \8812 [447] = 1'h0;
+    \8812 [448] = 1'h1;
+    \8812 [449] = 1'h1;
+    \8812 [450] = 1'h1;
+    \8812 [451] = 1'h1;
+    \8812 [452] = 1'h1;
+    \8812 [453] = 1'h1;
+    \8812 [454] = 1'h1;
+    \8812 [455] = 1'h1;
+    \8812 [456] = 1'h1;
+    \8812 [457] = 1'h1;
+    \8812 [458] = 1'h1;
+    \8812 [459] = 1'h1;
+    \8812 [460] = 1'h1;
+    \8812 [461] = 1'h1;
+    \8812 [462] = 1'h1;
+    \8812 [463] = 1'h1;
+    \8812 [464] = 1'h1;
+    \8812 [465] = 1'h1;
+    \8812 [466] = 1'h1;
+    \8812 [467] = 1'h1;
+    \8812 [468] = 1'h1;
+    \8812 [469] = 1'h1;
+    \8812 [470] = 1'h1;
+    \8812 [471] = 1'h1;
+    \8812 [472] = 1'h1;
+    \8812 [473] = 1'h1;
+    \8812 [474] = 1'h1;
+    \8812 [475] = 1'h1;
+    \8812 [476] = 1'h1;
+    \8812 [477] = 1'h1;
+    \8812 [478] = 1'h1;
+    \8812 [479] = 1'h1;
+    \8812 [480] = 1'h1;
+    \8812 [481] = 1'h1;
+    \8812 [482] = 1'h1;
+    \8812 [483] = 1'h1;
+    \8812 [484] = 1'h1;
+    \8812 [485] = 1'h1;
+    \8812 [486] = 1'h1;
+    \8812 [487] = 1'h1;
+    \8812 [488] = 1'h1;
+    \8812 [489] = 1'h1;
+    \8812 [490] = 1'h1;
+    \8812 [491] = 1'h1;
+    \8812 [492] = 1'h1;
+    \8812 [493] = 1'h1;
+    \8812 [494] = 1'h1;
+    \8812 [495] = 1'h1;
+    \8812 [496] = 1'h1;
+    \8812 [497] = 1'h1;
+    \8812 [498] = 1'h1;
+    \8812 [499] = 1'h1;
+    \8812 [500] = 1'h1;
+    \8812 [501] = 1'h1;
+    \8812 [502] = 1'h1;
+    \8812 [503] = 1'h1;
+    \8812 [504] = 1'h1;
+    \8812 [505] = 1'h1;
+    \8812 [506] = 1'h1;
+    \8812 [507] = 1'h1;
+    \8812 [508] = 1'h1;
+    \8812 [509] = 1'h1;
+    \8812 [510] = 1'h1;
+    \8812 [511] = 1'h1;
+    \8812 [512] = 1'h0;
+    \8812 [513] = 1'h0;
+    \8812 [514] = 1'h0;
+    \8812 [515] = 1'h0;
+    \8812 [516] = 1'h0;
+    \8812 [517] = 1'h0;
+    \8812 [518] = 1'h0;
+    \8812 [519] = 1'h0;
+    \8812 [520] = 1'h0;
+    \8812 [521] = 1'h0;
+    \8812 [522] = 1'h0;
+    \8812 [523] = 1'h0;
+    \8812 [524] = 1'h0;
+    \8812 [525] = 1'h0;
+    \8812 [526] = 1'h0;
+    \8812 [527] = 1'h0;
+    \8812 [528] = 1'h0;
+    \8812 [529] = 1'h0;
+    \8812 [530] = 1'h0;
+    \8812 [531] = 1'h0;
+    \8812 [532] = 1'h0;
+    \8812 [533] = 1'h0;
+    \8812 [534] = 1'h0;
+    \8812 [535] = 1'h0;
+    \8812 [536] = 1'h0;
+    \8812 [537] = 1'h0;
+    \8812 [538] = 1'h0;
+    \8812 [539] = 1'h0;
+    \8812 [540] = 1'h0;
+    \8812 [541] = 1'h0;
+    \8812 [542] = 1'h0;
+    \8812 [543] = 1'h0;
+    \8812 [544] = 1'h0;
+    \8812 [545] = 1'h0;
+    \8812 [546] = 1'h0;
+    \8812 [547] = 1'h0;
+    \8812 [548] = 1'h0;
+    \8812 [549] = 1'h0;
+    \8812 [550] = 1'h0;
+    \8812 [551] = 1'h0;
+    \8812 [552] = 1'h0;
+    \8812 [553] = 1'h0;
+    \8812 [554] = 1'h0;
+    \8812 [555] = 1'h0;
+    \8812 [556] = 1'h0;
+    \8812 [557] = 1'h0;
+    \8812 [558] = 1'h0;
+    \8812 [559] = 1'h0;
+    \8812 [560] = 1'h0;
+    \8812 [561] = 1'h0;
+    \8812 [562] = 1'h0;
+    \8812 [563] = 1'h0;
+    \8812 [564] = 1'h0;
+    \8812 [565] = 1'h0;
+    \8812 [566] = 1'h0;
+    \8812 [567] = 1'h0;
+    \8812 [568] = 1'h0;
+    \8812 [569] = 1'h0;
+    \8812 [570] = 1'h0;
+    \8812 [571] = 1'h0;
+    \8812 [572] = 1'h0;
+    \8812 [573] = 1'h0;
+    \8812 [574] = 1'h0;
+    \8812 [575] = 1'h0;
+    \8812 [576] = 1'h0;
+    \8812 [577] = 1'h0;
+    \8812 [578] = 1'h0;
+    \8812 [579] = 1'h0;
+    \8812 [580] = 1'h0;
+    \8812 [581] = 1'h0;
+    \8812 [582] = 1'h0;
+    \8812 [583] = 1'h0;
+    \8812 [584] = 1'h0;
+    \8812 [585] = 1'h0;
+    \8812 [586] = 1'h0;
+    \8812 [587] = 1'h0;
+    \8812 [588] = 1'h0;
+    \8812 [589] = 1'h0;
+    \8812 [590] = 1'h0;
+    \8812 [591] = 1'h0;
+    \8812 [592] = 1'h0;
+    \8812 [593] = 1'h0;
+    \8812 [594] = 1'h0;
+    \8812 [595] = 1'h0;
+    \8812 [596] = 1'h0;
+    \8812 [597] = 1'h0;
+    \8812 [598] = 1'h0;
+    \8812 [599] = 1'h0;
+    \8812 [600] = 1'h0;
+    \8812 [601] = 1'h0;
+    \8812 [602] = 1'h0;
+    \8812 [603] = 1'h0;
+    \8812 [604] = 1'h0;
+    \8812 [605] = 1'h0;
+    \8812 [606] = 1'h0;
+    \8812 [607] = 1'h0;
+    \8812 [608] = 1'h0;
+    \8812 [609] = 1'h0;
+    \8812 [610] = 1'h0;
+    \8812 [611] = 1'h0;
+    \8812 [612] = 1'h0;
+    \8812 [613] = 1'h0;
+    \8812 [614] = 1'h0;
+    \8812 [615] = 1'h0;
+    \8812 [616] = 1'h0;
+    \8812 [617] = 1'h0;
+    \8812 [618] = 1'h0;
+    \8812 [619] = 1'h0;
+    \8812 [620] = 1'h0;
+    \8812 [621] = 1'h0;
+    \8812 [622] = 1'h0;
+    \8812 [623] = 1'h0;
+    \8812 [624] = 1'h0;
+    \8812 [625] = 1'h0;
+    \8812 [626] = 1'h0;
+    \8812 [627] = 1'h0;
+    \8812 [628] = 1'h0;
+    \8812 [629] = 1'h0;
+    \8812 [630] = 1'h0;
+    \8812 [631] = 1'h0;
+    \8812 [632] = 1'h0;
+    \8812 [633] = 1'h0;
+    \8812 [634] = 1'h0;
+    \8812 [635] = 1'h0;
+    \8812 [636] = 1'h0;
+    \8812 [637] = 1'h0;
+    \8812 [638] = 1'h0;
+    \8812 [639] = 1'h0;
+    \8812 [640] = 1'h0;
+    \8812 [641] = 1'h0;
+    \8812 [642] = 1'h0;
+    \8812 [643] = 1'h0;
+    \8812 [644] = 1'h0;
+    \8812 [645] = 1'h0;
+    \8812 [646] = 1'h0;
+    \8812 [647] = 1'h0;
+    \8812 [648] = 1'h0;
+    \8812 [649] = 1'h0;
+    \8812 [650] = 1'h0;
+    \8812 [651] = 1'h0;
+    \8812 [652] = 1'h0;
+    \8812 [653] = 1'h0;
+    \8812 [654] = 1'h0;
+    \8812 [655] = 1'h0;
+    \8812 [656] = 1'h0;
+    \8812 [657] = 1'h0;
+    \8812 [658] = 1'h0;
+    \8812 [659] = 1'h0;
+    \8812 [660] = 1'h0;
+    \8812 [661] = 1'h0;
+    \8812 [662] = 1'h0;
+    \8812 [663] = 1'h0;
+    \8812 [664] = 1'h0;
+    \8812 [665] = 1'h0;
+    \8812 [666] = 1'h0;
+    \8812 [667] = 1'h0;
+    \8812 [668] = 1'h0;
+    \8812 [669] = 1'h0;
+    \8812 [670] = 1'h0;
+    \8812 [671] = 1'h0;
+    \8812 [672] = 1'h0;
+    \8812 [673] = 1'h0;
+    \8812 [674] = 1'h0;
+    \8812 [675] = 1'h0;
+    \8812 [676] = 1'h0;
+    \8812 [677] = 1'h0;
+    \8812 [678] = 1'h0;
+    \8812 [679] = 1'h0;
+    \8812 [680] = 1'h0;
+    \8812 [681] = 1'h0;
+    \8812 [682] = 1'h0;
+    \8812 [683] = 1'h0;
+    \8812 [684] = 1'h0;
+    \8812 [685] = 1'h0;
+    \8812 [686] = 1'h0;
+    \8812 [687] = 1'h0;
+    \8812 [688] = 1'h0;
+    \8812 [689] = 1'h0;
+    \8812 [690] = 1'h0;
+    \8812 [691] = 1'h0;
+    \8812 [692] = 1'h0;
+    \8812 [693] = 1'h0;
+    \8812 [694] = 1'h0;
+    \8812 [695] = 1'h0;
+    \8812 [696] = 1'h0;
+    \8812 [697] = 1'h0;
+    \8812 [698] = 1'h0;
+    \8812 [699] = 1'h0;
+    \8812 [700] = 1'h0;
+    \8812 [701] = 1'h0;
+    \8812 [702] = 1'h0;
+    \8812 [703] = 1'h0;
+    \8812 [704] = 1'h0;
+    \8812 [705] = 1'h0;
+    \8812 [706] = 1'h0;
+    \8812 [707] = 1'h0;
+    \8812 [708] = 1'h0;
+    \8812 [709] = 1'h0;
+    \8812 [710] = 1'h0;
+    \8812 [711] = 1'h0;
+    \8812 [712] = 1'h0;
+    \8812 [713] = 1'h0;
+    \8812 [714] = 1'h0;
+    \8812 [715] = 1'h0;
+    \8812 [716] = 1'h0;
+    \8812 [717] = 1'h0;
+    \8812 [718] = 1'h0;
+    \8812 [719] = 1'h0;
+    \8812 [720] = 1'h0;
+    \8812 [721] = 1'h0;
+    \8812 [722] = 1'h0;
+    \8812 [723] = 1'h0;
+    \8812 [724] = 1'h0;
+    \8812 [725] = 1'h0;
+    \8812 [726] = 1'h0;
+    \8812 [727] = 1'h0;
+    \8812 [728] = 1'h0;
+    \8812 [729] = 1'h0;
+    \8812 [730] = 1'h0;
+    \8812 [731] = 1'h0;
+    \8812 [732] = 1'h0;
+    \8812 [733] = 1'h0;
+    \8812 [734] = 1'h0;
+    \8812 [735] = 1'h0;
+    \8812 [736] = 1'h0;
+    \8812 [737] = 1'h0;
+    \8812 [738] = 1'h0;
+    \8812 [739] = 1'h0;
+    \8812 [740] = 1'h0;
+    \8812 [741] = 1'h0;
+    \8812 [742] = 1'h0;
+    \8812 [743] = 1'h0;
+    \8812 [744] = 1'h0;
+    \8812 [745] = 1'h0;
+    \8812 [746] = 1'h0;
+    \8812 [747] = 1'h0;
+    \8812 [748] = 1'h0;
+    \8812 [749] = 1'h0;
+    \8812 [750] = 1'h0;
+    \8812 [751] = 1'h0;
+    \8812 [752] = 1'h0;
+    \8812 [753] = 1'h0;
+    \8812 [754] = 1'h0;
+    \8812 [755] = 1'h0;
+    \8812 [756] = 1'h0;
+    \8812 [757] = 1'h0;
+    \8812 [758] = 1'h0;
+    \8812 [759] = 1'h0;
+    \8812 [760] = 1'h0;
+    \8812 [761] = 1'h0;
+    \8812 [762] = 1'h0;
+    \8812 [763] = 1'h0;
+    \8812 [764] = 1'h0;
+    \8812 [765] = 1'h0;
+    \8812 [766] = 1'h0;
+    \8812 [767] = 1'h0;
+    \8812 [768] = 1'h0;
+    \8812 [769] = 1'h0;
+    \8812 [770] = 1'h0;
+    \8812 [771] = 1'h0;
+    \8812 [772] = 1'h0;
+    \8812 [773] = 1'h0;
+    \8812 [774] = 1'h0;
+    \8812 [775] = 1'h0;
+    \8812 [776] = 1'h0;
+    \8812 [777] = 1'h0;
+    \8812 [778] = 1'h0;
+    \8812 [779] = 1'h0;
+    \8812 [780] = 1'h0;
+    \8812 [781] = 1'h0;
+    \8812 [782] = 1'h0;
+    \8812 [783] = 1'h0;
+    \8812 [784] = 1'h0;
+    \8812 [785] = 1'h0;
+    \8812 [786] = 1'h0;
+    \8812 [787] = 1'h0;
+    \8812 [788] = 1'h0;
+    \8812 [789] = 1'h0;
+    \8812 [790] = 1'h0;
+    \8812 [791] = 1'h0;
+    \8812 [792] = 1'h0;
+    \8812 [793] = 1'h0;
+    \8812 [794] = 1'h0;
+    \8812 [795] = 1'h0;
+    \8812 [796] = 1'h0;
+    \8812 [797] = 1'h0;
+    \8812 [798] = 1'h0;
+    \8812 [799] = 1'h0;
+    \8812 [800] = 1'h0;
+    \8812 [801] = 1'h0;
+    \8812 [802] = 1'h0;
+    \8812 [803] = 1'h0;
+    \8812 [804] = 1'h0;
+    \8812 [805] = 1'h0;
+    \8812 [806] = 1'h0;
+    \8812 [807] = 1'h0;
+    \8812 [808] = 1'h0;
+    \8812 [809] = 1'h0;
+    \8812 [810] = 1'h0;
+    \8812 [811] = 1'h0;
+    \8812 [812] = 1'h0;
+    \8812 [813] = 1'h0;
+    \8812 [814] = 1'h0;
+    \8812 [815] = 1'h0;
+    \8812 [816] = 1'h0;
+    \8812 [817] = 1'h0;
+    \8812 [818] = 1'h0;
+    \8812 [819] = 1'h0;
+    \8812 [820] = 1'h0;
+    \8812 [821] = 1'h0;
+    \8812 [822] = 1'h0;
+    \8812 [823] = 1'h0;
+    \8812 [824] = 1'h0;
+    \8812 [825] = 1'h0;
+    \8812 [826] = 1'h0;
+    \8812 [827] = 1'h0;
+    \8812 [828] = 1'h0;
+    \8812 [829] = 1'h0;
+    \8812 [830] = 1'h0;
+    \8812 [831] = 1'h0;
+    \8812 [832] = 1'h0;
+    \8812 [833] = 1'h0;
+    \8812 [834] = 1'h0;
+    \8812 [835] = 1'h0;
+    \8812 [836] = 1'h0;
+    \8812 [837] = 1'h0;
+    \8812 [838] = 1'h0;
+    \8812 [839] = 1'h0;
+    \8812 [840] = 1'h0;
+    \8812 [841] = 1'h0;
+    \8812 [842] = 1'h0;
+    \8812 [843] = 1'h0;
+    \8812 [844] = 1'h0;
+    \8812 [845] = 1'h0;
+    \8812 [846] = 1'h0;
+    \8812 [847] = 1'h0;
+    \8812 [848] = 1'h0;
+    \8812 [849] = 1'h0;
+    \8812 [850] = 1'h0;
+    \8812 [851] = 1'h0;
+    \8812 [852] = 1'h0;
+    \8812 [853] = 1'h0;
+    \8812 [854] = 1'h0;
+    \8812 [855] = 1'h0;
+    \8812 [856] = 1'h0;
+    \8812 [857] = 1'h0;
+    \8812 [858] = 1'h0;
+    \8812 [859] = 1'h0;
+    \8812 [860] = 1'h0;
+    \8812 [861] = 1'h0;
+    \8812 [862] = 1'h0;
+    \8812 [863] = 1'h0;
+    \8812 [864] = 1'h0;
+    \8812 [865] = 1'h0;
+    \8812 [866] = 1'h0;
+    \8812 [867] = 1'h0;
+    \8812 [868] = 1'h0;
+    \8812 [869] = 1'h0;
+    \8812 [870] = 1'h0;
+    \8812 [871] = 1'h0;
+    \8812 [872] = 1'h0;
+    \8812 [873] = 1'h0;
+    \8812 [874] = 1'h0;
+    \8812 [875] = 1'h0;
+    \8812 [876] = 1'h0;
+    \8812 [877] = 1'h0;
+    \8812 [878] = 1'h0;
+    \8812 [879] = 1'h0;
+    \8812 [880] = 1'h0;
+    \8812 [881] = 1'h0;
+    \8812 [882] = 1'h0;
+    \8812 [883] = 1'h0;
+    \8812 [884] = 1'h0;
+    \8812 [885] = 1'h0;
+    \8812 [886] = 1'h0;
+    \8812 [887] = 1'h0;
+    \8812 [888] = 1'h0;
+    \8812 [889] = 1'h0;
+    \8812 [890] = 1'h0;
+    \8812 [891] = 1'h0;
+    \8812 [892] = 1'h0;
+    \8812 [893] = 1'h0;
+    \8812 [894] = 1'h0;
+    \8812 [895] = 1'h0;
+    \8812 [896] = 1'h0;
+    \8812 [897] = 1'h0;
+    \8812 [898] = 1'h0;
+    \8812 [899] = 1'h0;
+    \8812 [900] = 1'h0;
+    \8812 [901] = 1'h0;
+    \8812 [902] = 1'h0;
+    \8812 [903] = 1'h0;
+    \8812 [904] = 1'h0;
+    \8812 [905] = 1'h0;
+    \8812 [906] = 1'h0;
+    \8812 [907] = 1'h0;
+    \8812 [908] = 1'h0;
+    \8812 [909] = 1'h0;
+    \8812 [910] = 1'h0;
+    \8812 [911] = 1'h0;
+    \8812 [912] = 1'h0;
+    \8812 [913] = 1'h0;
+    \8812 [914] = 1'h0;
+    \8812 [915] = 1'h0;
+    \8812 [916] = 1'h0;
+    \8812 [917] = 1'h0;
+    \8812 [918] = 1'h0;
+    \8812 [919] = 1'h0;
+    \8812 [920] = 1'h0;
+    \8812 [921] = 1'h0;
+    \8812 [922] = 1'h0;
+    \8812 [923] = 1'h0;
+    \8812 [924] = 1'h0;
+    \8812 [925] = 1'h0;
+    \8812 [926] = 1'h0;
+    \8812 [927] = 1'h0;
+    \8812 [928] = 1'h0;
+    \8812 [929] = 1'h0;
+    \8812 [930] = 1'h0;
+    \8812 [931] = 1'h0;
+    \8812 [932] = 1'h0;
+    \8812 [933] = 1'h0;
+    \8812 [934] = 1'h0;
+    \8812 [935] = 1'h0;
+    \8812 [936] = 1'h0;
+    \8812 [937] = 1'h0;
+    \8812 [938] = 1'h0;
+    \8812 [939] = 1'h0;
+    \8812 [940] = 1'h0;
+    \8812 [941] = 1'h0;
+    \8812 [942] = 1'h0;
+    \8812 [943] = 1'h0;
+    \8812 [944] = 1'h0;
+    \8812 [945] = 1'h0;
+    \8812 [946] = 1'h0;
+    \8812 [947] = 1'h0;
+    \8812 [948] = 1'h0;
+    \8812 [949] = 1'h0;
+    \8812 [950] = 1'h0;
+    \8812 [951] = 1'h0;
+    \8812 [952] = 1'h0;
+    \8812 [953] = 1'h0;
+    \8812 [954] = 1'h0;
+    \8812 [955] = 1'h0;
+    \8812 [956] = 1'h0;
+    \8812 [957] = 1'h0;
+    \8812 [958] = 1'h0;
+    \8812 [959] = 1'h0;
+    \8812 [960] = 1'h0;
+    \8812 [961] = 1'h0;
+    \8812 [962] = 1'h0;
+    \8812 [963] = 1'h0;
+    \8812 [964] = 1'h0;
+    \8812 [965] = 1'h0;
+    \8812 [966] = 1'h0;
+    \8812 [967] = 1'h0;
+    \8812 [968] = 1'h0;
+    \8812 [969] = 1'h0;
+    \8812 [970] = 1'h0;
+    \8812 [971] = 1'h0;
+    \8812 [972] = 1'h0;
+    \8812 [973] = 1'h0;
+    \8812 [974] = 1'h0;
+    \8812 [975] = 1'h0;
+    \8812 [976] = 1'h0;
+    \8812 [977] = 1'h0;
+    \8812 [978] = 1'h0;
+    \8812 [979] = 1'h0;
+    \8812 [980] = 1'h0;
+    \8812 [981] = 1'h0;
+    \8812 [982] = 1'h0;
+    \8812 [983] = 1'h0;
+    \8812 [984] = 1'h0;
+    \8812 [985] = 1'h0;
+    \8812 [986] = 1'h0;
+    \8812 [987] = 1'h0;
+    \8812 [988] = 1'h0;
+    \8812 [989] = 1'h0;
+    \8812 [990] = 1'h0;
+    \8812 [991] = 1'h0;
+    \8812 [992] = 1'h0;
+    \8812 [993] = 1'h0;
+    \8812 [994] = 1'h0;
+    \8812 [995] = 1'h0;
+    \8812 [996] = 1'h0;
+    \8812 [997] = 1'h0;
+    \8812 [998] = 1'h0;
+    \8812 [999] = 1'h0;
+    \8812 [1000] = 1'h0;
+    \8812 [1001] = 1'h0;
+    \8812 [1002] = 1'h0;
+    \8812 [1003] = 1'h0;
+    \8812 [1004] = 1'h0;
+    \8812 [1005] = 1'h0;
+    \8812 [1006] = 1'h0;
+    \8812 [1007] = 1'h0;
+    \8812 [1008] = 1'h0;
+    \8812 [1009] = 1'h0;
+    \8812 [1010] = 1'h0;
+    \8812 [1011] = 1'h0;
+    \8812 [1012] = 1'h0;
+    \8812 [1013] = 1'h0;
+    \8812 [1014] = 1'h0;
+    \8812 [1015] = 1'h0;
+    \8812 [1016] = 1'h0;
+    \8812 [1017] = 1'h0;
+    \8812 [1018] = 1'h0;
+    \8812 [1019] = 1'h0;
+    \8812 [1020] = 1'h0;
+    \8812 [1021] = 1'h0;
+    \8812 [1022] = 1'h0;
+    \8812 [1023] = 1'h0;
+    \8812 [1024] = 1'h0;
+    \8812 [1025] = 1'h0;
+    \8812 [1026] = 1'h0;
+    \8812 [1027] = 1'h0;
+    \8812 [1028] = 1'h0;
+    \8812 [1029] = 1'h0;
+    \8812 [1030] = 1'h0;
+    \8812 [1031] = 1'h0;
+    \8812 [1032] = 1'h0;
+    \8812 [1033] = 1'h0;
+    \8812 [1034] = 1'h0;
+    \8812 [1035] = 1'h0;
+    \8812 [1036] = 1'h0;
+    \8812 [1037] = 1'h0;
+    \8812 [1038] = 1'h0;
+    \8812 [1039] = 1'h0;
+    \8812 [1040] = 1'h0;
+    \8812 [1041] = 1'h0;
+    \8812 [1042] = 1'h0;
+    \8812 [1043] = 1'h0;
+    \8812 [1044] = 1'h0;
+    \8812 [1045] = 1'h0;
+    \8812 [1046] = 1'h0;
+    \8812 [1047] = 1'h0;
+    \8812 [1048] = 1'h0;
+    \8812 [1049] = 1'h0;
+    \8812 [1050] = 1'h0;
+    \8812 [1051] = 1'h0;
+    \8812 [1052] = 1'h0;
+    \8812 [1053] = 1'h0;
+    \8812 [1054] = 1'h0;
+    \8812 [1055] = 1'h0;
+    \8812 [1056] = 1'h0;
+    \8812 [1057] = 1'h0;
+    \8812 [1058] = 1'h0;
+    \8812 [1059] = 1'h0;
+    \8812 [1060] = 1'h0;
+    \8812 [1061] = 1'h0;
+    \8812 [1062] = 1'h0;
+    \8812 [1063] = 1'h0;
+    \8812 [1064] = 1'h0;
+    \8812 [1065] = 1'h0;
+    \8812 [1066] = 1'h0;
+    \8812 [1067] = 1'h0;
+    \8812 [1068] = 1'h0;
+    \8812 [1069] = 1'h0;
+    \8812 [1070] = 1'h0;
+    \8812 [1071] = 1'h0;
+    \8812 [1072] = 1'h0;
+    \8812 [1073] = 1'h0;
+    \8812 [1074] = 1'h0;
+    \8812 [1075] = 1'h0;
+    \8812 [1076] = 1'h0;
+    \8812 [1077] = 1'h0;
+    \8812 [1078] = 1'h0;
+    \8812 [1079] = 1'h0;
+    \8812 [1080] = 1'h0;
+    \8812 [1081] = 1'h0;
+    \8812 [1082] = 1'h0;
+    \8812 [1083] = 1'h0;
+    \8812 [1084] = 1'h0;
+    \8812 [1085] = 1'h0;
+    \8812 [1086] = 1'h0;
+    \8812 [1087] = 1'h0;
+    \8812 [1088] = 1'h0;
+    \8812 [1089] = 1'h0;
+    \8812 [1090] = 1'h0;
+    \8812 [1091] = 1'h0;
+    \8812 [1092] = 1'h0;
+    \8812 [1093] = 1'h0;
+    \8812 [1094] = 1'h0;
+    \8812 [1095] = 1'h0;
+    \8812 [1096] = 1'h0;
+    \8812 [1097] = 1'h0;
+    \8812 [1098] = 1'h0;
+    \8812 [1099] = 1'h0;
+    \8812 [1100] = 1'h0;
+    \8812 [1101] = 1'h0;
+    \8812 [1102] = 1'h0;
+    \8812 [1103] = 1'h0;
+    \8812 [1104] = 1'h0;
+    \8812 [1105] = 1'h0;
+    \8812 [1106] = 1'h0;
+    \8812 [1107] = 1'h0;
+    \8812 [1108] = 1'h0;
+    \8812 [1109] = 1'h0;
+    \8812 [1110] = 1'h0;
+    \8812 [1111] = 1'h0;
+    \8812 [1112] = 1'h0;
+    \8812 [1113] = 1'h0;
+    \8812 [1114] = 1'h0;
+    \8812 [1115] = 1'h0;
+    \8812 [1116] = 1'h0;
+    \8812 [1117] = 1'h0;
+    \8812 [1118] = 1'h0;
+    \8812 [1119] = 1'h0;
+    \8812 [1120] = 1'h0;
+    \8812 [1121] = 1'h0;
+    \8812 [1122] = 1'h0;
+    \8812 [1123] = 1'h0;
+    \8812 [1124] = 1'h0;
+    \8812 [1125] = 1'h0;
+    \8812 [1126] = 1'h0;
+    \8812 [1127] = 1'h0;
+    \8812 [1128] = 1'h0;
+    \8812 [1129] = 1'h0;
+    \8812 [1130] = 1'h0;
+    \8812 [1131] = 1'h0;
+    \8812 [1132] = 1'h0;
+    \8812 [1133] = 1'h0;
+    \8812 [1134] = 1'h0;
+    \8812 [1135] = 1'h0;
+    \8812 [1136] = 1'h0;
+    \8812 [1137] = 1'h0;
+    \8812 [1138] = 1'h0;
+    \8812 [1139] = 1'h0;
+    \8812 [1140] = 1'h0;
+    \8812 [1141] = 1'h0;
+    \8812 [1142] = 1'h0;
+    \8812 [1143] = 1'h0;
+    \8812 [1144] = 1'h0;
+    \8812 [1145] = 1'h0;
+    \8812 [1146] = 1'h0;
+    \8812 [1147] = 1'h0;
+    \8812 [1148] = 1'h0;
+    \8812 [1149] = 1'h0;
+    \8812 [1150] = 1'h0;
+    \8812 [1151] = 1'h0;
+    \8812 [1152] = 1'h0;
+    \8812 [1153] = 1'h0;
+    \8812 [1154] = 1'h0;
+    \8812 [1155] = 1'h0;
+    \8812 [1156] = 1'h0;
+    \8812 [1157] = 1'h0;
+    \8812 [1158] = 1'h0;
+    \8812 [1159] = 1'h0;
+    \8812 [1160] = 1'h0;
+    \8812 [1161] = 1'h0;
+    \8812 [1162] = 1'h0;
+    \8812 [1163] = 1'h0;
+    \8812 [1164] = 1'h0;
+    \8812 [1165] = 1'h0;
+    \8812 [1166] = 1'h0;
+    \8812 [1167] = 1'h0;
+    \8812 [1168] = 1'h0;
+    \8812 [1169] = 1'h0;
+    \8812 [1170] = 1'h0;
+    \8812 [1171] = 1'h0;
+    \8812 [1172] = 1'h0;
+    \8812 [1173] = 1'h0;
+    \8812 [1174] = 1'h0;
+    \8812 [1175] = 1'h0;
+    \8812 [1176] = 1'h0;
+    \8812 [1177] = 1'h0;
+    \8812 [1178] = 1'h0;
+    \8812 [1179] = 1'h0;
+    \8812 [1180] = 1'h0;
+    \8812 [1181] = 1'h0;
+    \8812 [1182] = 1'h0;
+    \8812 [1183] = 1'h0;
+    \8812 [1184] = 1'h0;
+    \8812 [1185] = 1'h0;
+    \8812 [1186] = 1'h0;
+    \8812 [1187] = 1'h0;
+    \8812 [1188] = 1'h0;
+    \8812 [1189] = 1'h0;
+    \8812 [1190] = 1'h0;
+    \8812 [1191] = 1'h0;
+    \8812 [1192] = 1'h0;
+    \8812 [1193] = 1'h0;
+    \8812 [1194] = 1'h0;
+    \8812 [1195] = 1'h0;
+    \8812 [1196] = 1'h0;
+    \8812 [1197] = 1'h0;
+    \8812 [1198] = 1'h0;
+    \8812 [1199] = 1'h0;
+    \8812 [1200] = 1'h0;
+    \8812 [1201] = 1'h0;
+    \8812 [1202] = 1'h0;
+    \8812 [1203] = 1'h0;
+    \8812 [1204] = 1'h0;
+    \8812 [1205] = 1'h0;
+    \8812 [1206] = 1'h0;
+    \8812 [1207] = 1'h0;
+    \8812 [1208] = 1'h0;
+    \8812 [1209] = 1'h0;
+    \8812 [1210] = 1'h0;
+    \8812 [1211] = 1'h0;
+    \8812 [1212] = 1'h0;
+    \8812 [1213] = 1'h0;
+    \8812 [1214] = 1'h0;
+    \8812 [1215] = 1'h0;
+    \8812 [1216] = 1'h0;
+    \8812 [1217] = 1'h0;
+    \8812 [1218] = 1'h0;
+    \8812 [1219] = 1'h0;
+    \8812 [1220] = 1'h0;
+    \8812 [1221] = 1'h0;
+    \8812 [1222] = 1'h0;
+    \8812 [1223] = 1'h0;
+    \8812 [1224] = 1'h0;
+    \8812 [1225] = 1'h0;
+    \8812 [1226] = 1'h0;
+    \8812 [1227] = 1'h0;
+    \8812 [1228] = 1'h0;
+    \8812 [1229] = 1'h0;
+    \8812 [1230] = 1'h0;
+    \8812 [1231] = 1'h0;
+    \8812 [1232] = 1'h0;
+    \8812 [1233] = 1'h0;
+    \8812 [1234] = 1'h0;
+    \8812 [1235] = 1'h0;
+    \8812 [1236] = 1'h0;
+    \8812 [1237] = 1'h0;
+    \8812 [1238] = 1'h0;
+    \8812 [1239] = 1'h0;
+    \8812 [1240] = 1'h0;
+    \8812 [1241] = 1'h0;
+    \8812 [1242] = 1'h0;
+    \8812 [1243] = 1'h0;
+    \8812 [1244] = 1'h0;
+    \8812 [1245] = 1'h0;
+    \8812 [1246] = 1'h0;
+    \8812 [1247] = 1'h0;
+    \8812 [1248] = 1'h0;
+    \8812 [1249] = 1'h0;
+    \8812 [1250] = 1'h0;
+    \8812 [1251] = 1'h0;
+    \8812 [1252] = 1'h0;
+    \8812 [1253] = 1'h0;
+    \8812 [1254] = 1'h0;
+    \8812 [1255] = 1'h0;
+    \8812 [1256] = 1'h0;
+    \8812 [1257] = 1'h0;
+    \8812 [1258] = 1'h0;
+    \8812 [1259] = 1'h0;
+    \8812 [1260] = 1'h0;
+    \8812 [1261] = 1'h0;
+    \8812 [1262] = 1'h0;
+    \8812 [1263] = 1'h0;
+    \8812 [1264] = 1'h0;
+    \8812 [1265] = 1'h0;
+    \8812 [1266] = 1'h0;
+    \8812 [1267] = 1'h0;
+    \8812 [1268] = 1'h0;
+    \8812 [1269] = 1'h0;
+    \8812 [1270] = 1'h0;
+    \8812 [1271] = 1'h0;
+    \8812 [1272] = 1'h0;
+    \8812 [1273] = 1'h0;
+    \8812 [1274] = 1'h0;
+    \8812 [1275] = 1'h0;
+    \8812 [1276] = 1'h0;
+    \8812 [1277] = 1'h0;
+    \8812 [1278] = 1'h0;
+    \8812 [1279] = 1'h0;
+    \8812 [1280] = 1'h0;
+    \8812 [1281] = 1'h0;
+    \8812 [1282] = 1'h0;
+    \8812 [1283] = 1'h0;
+    \8812 [1284] = 1'h0;
+    \8812 [1285] = 1'h0;
+    \8812 [1286] = 1'h0;
+    \8812 [1287] = 1'h0;
+    \8812 [1288] = 1'h0;
+    \8812 [1289] = 1'h0;
+    \8812 [1290] = 1'h0;
+    \8812 [1291] = 1'h0;
+    \8812 [1292] = 1'h0;
+    \8812 [1293] = 1'h0;
+    \8812 [1294] = 1'h0;
+    \8812 [1295] = 1'h0;
+    \8812 [1296] = 1'h0;
+    \8812 [1297] = 1'h0;
+    \8812 [1298] = 1'h0;
+    \8812 [1299] = 1'h0;
+    \8812 [1300] = 1'h0;
+    \8812 [1301] = 1'h0;
+    \8812 [1302] = 1'h0;
+    \8812 [1303] = 1'h0;
+    \8812 [1304] = 1'h0;
+    \8812 [1305] = 1'h0;
+    \8812 [1306] = 1'h0;
+    \8812 [1307] = 1'h0;
+    \8812 [1308] = 1'h0;
+    \8812 [1309] = 1'h0;
+    \8812 [1310] = 1'h0;
+    \8812 [1311] = 1'h0;
+    \8812 [1312] = 1'h0;
+    \8812 [1313] = 1'h0;
+    \8812 [1314] = 1'h0;
+    \8812 [1315] = 1'h0;
+    \8812 [1316] = 1'h0;
+    \8812 [1317] = 1'h0;
+    \8812 [1318] = 1'h0;
+    \8812 [1319] = 1'h0;
+    \8812 [1320] = 1'h0;
+    \8812 [1321] = 1'h0;
+    \8812 [1322] = 1'h0;
+    \8812 [1323] = 1'h0;
+    \8812 [1324] = 1'h0;
+    \8812 [1325] = 1'h0;
+    \8812 [1326] = 1'h0;
+    \8812 [1327] = 1'h0;
+    \8812 [1328] = 1'h0;
+    \8812 [1329] = 1'h0;
+    \8812 [1330] = 1'h0;
+    \8812 [1331] = 1'h0;
+    \8812 [1332] = 1'h0;
+    \8812 [1333] = 1'h0;
+    \8812 [1334] = 1'h0;
+    \8812 [1335] = 1'h0;
+    \8812 [1336] = 1'h0;
+    \8812 [1337] = 1'h0;
+    \8812 [1338] = 1'h0;
+    \8812 [1339] = 1'h0;
+    \8812 [1340] = 1'h0;
+    \8812 [1341] = 1'h0;
+    \8812 [1342] = 1'h0;
+    \8812 [1343] = 1'h0;
+    \8812 [1344] = 1'h0;
+    \8812 [1345] = 1'h0;
+    \8812 [1346] = 1'h0;
+    \8812 [1347] = 1'h0;
+    \8812 [1348] = 1'h0;
+    \8812 [1349] = 1'h0;
+    \8812 [1350] = 1'h0;
+    \8812 [1351] = 1'h0;
+    \8812 [1352] = 1'h0;
+    \8812 [1353] = 1'h0;
+    \8812 [1354] = 1'h0;
+    \8812 [1355] = 1'h0;
+    \8812 [1356] = 1'h0;
+    \8812 [1357] = 1'h0;
+    \8812 [1358] = 1'h0;
+    \8812 [1359] = 1'h0;
+    \8812 [1360] = 1'h0;
+    \8812 [1361] = 1'h0;
+    \8812 [1362] = 1'h0;
+    \8812 [1363] = 1'h0;
+    \8812 [1364] = 1'h0;
+    \8812 [1365] = 1'h0;
+    \8812 [1366] = 1'h0;
+    \8812 [1367] = 1'h0;
+    \8812 [1368] = 1'h0;
+    \8812 [1369] = 1'h0;
+    \8812 [1370] = 1'h0;
+    \8812 [1371] = 1'h0;
+    \8812 [1372] = 1'h0;
+    \8812 [1373] = 1'h0;
+    \8812 [1374] = 1'h0;
+    \8812 [1375] = 1'h0;
+    \8812 [1376] = 1'h0;
+    \8812 [1377] = 1'h0;
+    \8812 [1378] = 1'h0;
+    \8812 [1379] = 1'h0;
+    \8812 [1380] = 1'h0;
+    \8812 [1381] = 1'h0;
+    \8812 [1382] = 1'h0;
+    \8812 [1383] = 1'h0;
+    \8812 [1384] = 1'h0;
+    \8812 [1385] = 1'h0;
+    \8812 [1386] = 1'h0;
+    \8812 [1387] = 1'h0;
+    \8812 [1388] = 1'h0;
+    \8812 [1389] = 1'h0;
+    \8812 [1390] = 1'h0;
+    \8812 [1391] = 1'h0;
+    \8812 [1392] = 1'h0;
+    \8812 [1393] = 1'h0;
+    \8812 [1394] = 1'h0;
+    \8812 [1395] = 1'h0;
+    \8812 [1396] = 1'h0;
+    \8812 [1397] = 1'h0;
+    \8812 [1398] = 1'h0;
+    \8812 [1399] = 1'h0;
+    \8812 [1400] = 1'h0;
+    \8812 [1401] = 1'h0;
+    \8812 [1402] = 1'h0;
+    \8812 [1403] = 1'h0;
+    \8812 [1404] = 1'h0;
+    \8812 [1405] = 1'h0;
+    \8812 [1406] = 1'h0;
+    \8812 [1407] = 1'h0;
+    \8812 [1408] = 1'h0;
+    \8812 [1409] = 1'h0;
+    \8812 [1410] = 1'h0;
+    \8812 [1411] = 1'h0;
+    \8812 [1412] = 1'h0;
+    \8812 [1413] = 1'h0;
+    \8812 [1414] = 1'h0;
+    \8812 [1415] = 1'h0;
+    \8812 [1416] = 1'h0;
+    \8812 [1417] = 1'h0;
+    \8812 [1418] = 1'h0;
+    \8812 [1419] = 1'h0;
+    \8812 [1420] = 1'h0;
+    \8812 [1421] = 1'h0;
+    \8812 [1422] = 1'h0;
+    \8812 [1423] = 1'h0;
+    \8812 [1424] = 1'h0;
+    \8812 [1425] = 1'h0;
+    \8812 [1426] = 1'h0;
+    \8812 [1427] = 1'h0;
+    \8812 [1428] = 1'h0;
+    \8812 [1429] = 1'h0;
+    \8812 [1430] = 1'h0;
+    \8812 [1431] = 1'h0;
+    \8812 [1432] = 1'h0;
+    \8812 [1433] = 1'h0;
+    \8812 [1434] = 1'h0;
+    \8812 [1435] = 1'h0;
+    \8812 [1436] = 1'h0;
+    \8812 [1437] = 1'h0;
+    \8812 [1438] = 1'h0;
+    \8812 [1439] = 1'h0;
+    \8812 [1440] = 1'h0;
+    \8812 [1441] = 1'h0;
+    \8812 [1442] = 1'h0;
+    \8812 [1443] = 1'h0;
+    \8812 [1444] = 1'h0;
+    \8812 [1445] = 1'h0;
+    \8812 [1446] = 1'h0;
+    \8812 [1447] = 1'h0;
+    \8812 [1448] = 1'h0;
+    \8812 [1449] = 1'h0;
+    \8812 [1450] = 1'h0;
+    \8812 [1451] = 1'h0;
+    \8812 [1452] = 1'h0;
+    \8812 [1453] = 1'h0;
+    \8812 [1454] = 1'h0;
+    \8812 [1455] = 1'h0;
+    \8812 [1456] = 1'h0;
+    \8812 [1457] = 1'h0;
+    \8812 [1458] = 1'h0;
+    \8812 [1459] = 1'h0;
+    \8812 [1460] = 1'h0;
+    \8812 [1461] = 1'h0;
+    \8812 [1462] = 1'h0;
+    \8812 [1463] = 1'h0;
+    \8812 [1464] = 1'h0;
+    \8812 [1465] = 1'h0;
+    \8812 [1466] = 1'h0;
+    \8812 [1467] = 1'h0;
+    \8812 [1468] = 1'h0;
+    \8812 [1469] = 1'h0;
+    \8812 [1470] = 1'h0;
+    \8812 [1471] = 1'h0;
+    \8812 [1472] = 1'h0;
+    \8812 [1473] = 1'h0;
+    \8812 [1474] = 1'h0;
+    \8812 [1475] = 1'h0;
+    \8812 [1476] = 1'h0;
+    \8812 [1477] = 1'h0;
+    \8812 [1478] = 1'h0;
+    \8812 [1479] = 1'h0;
+    \8812 [1480] = 1'h0;
+    \8812 [1481] = 1'h0;
+    \8812 [1482] = 1'h0;
+    \8812 [1483] = 1'h0;
+    \8812 [1484] = 1'h0;
+    \8812 [1485] = 1'h0;
+    \8812 [1486] = 1'h0;
+    \8812 [1487] = 1'h0;
+    \8812 [1488] = 1'h0;
+    \8812 [1489] = 1'h0;
+    \8812 [1490] = 1'h0;
+    \8812 [1491] = 1'h0;
+    \8812 [1492] = 1'h0;
+    \8812 [1493] = 1'h0;
+    \8812 [1494] = 1'h0;
+    \8812 [1495] = 1'h0;
+    \8812 [1496] = 1'h0;
+    \8812 [1497] = 1'h0;
+    \8812 [1498] = 1'h0;
+    \8812 [1499] = 1'h0;
+    \8812 [1500] = 1'h0;
+    \8812 [1501] = 1'h0;
+    \8812 [1502] = 1'h0;
+    \8812 [1503] = 1'h0;
+    \8812 [1504] = 1'h0;
+    \8812 [1505] = 1'h0;
+    \8812 [1506] = 1'h0;
+    \8812 [1507] = 1'h0;
+    \8812 [1508] = 1'h0;
+    \8812 [1509] = 1'h0;
+    \8812 [1510] = 1'h0;
+    \8812 [1511] = 1'h0;
+    \8812 [1512] = 1'h0;
+    \8812 [1513] = 1'h0;
+    \8812 [1514] = 1'h0;
+    \8812 [1515] = 1'h0;
+    \8812 [1516] = 1'h0;
+    \8812 [1517] = 1'h0;
+    \8812 [1518] = 1'h0;
+    \8812 [1519] = 1'h0;
+    \8812 [1520] = 1'h0;
+    \8812 [1521] = 1'h0;
+    \8812 [1522] = 1'h0;
+    \8812 [1523] = 1'h0;
+    \8812 [1524] = 1'h0;
+    \8812 [1525] = 1'h0;
+    \8812 [1526] = 1'h0;
+    \8812 [1527] = 1'h0;
+    \8812 [1528] = 1'h0;
+    \8812 [1529] = 1'h0;
+    \8812 [1530] = 1'h0;
+    \8812 [1531] = 1'h0;
+    \8812 [1532] = 1'h0;
+    \8812 [1533] = 1'h0;
+    \8812 [1534] = 1'h0;
+    \8812 [1535] = 1'h0;
+    \8812 [1536] = 1'h0;
+    \8812 [1537] = 1'h0;
+    \8812 [1538] = 1'h0;
+    \8812 [1539] = 1'h0;
+    \8812 [1540] = 1'h0;
+    \8812 [1541] = 1'h0;
+    \8812 [1542] = 1'h0;
+    \8812 [1543] = 1'h0;
+    \8812 [1544] = 1'h0;
+    \8812 [1545] = 1'h0;
+    \8812 [1546] = 1'h0;
+    \8812 [1547] = 1'h0;
+    \8812 [1548] = 1'h0;
+    \8812 [1549] = 1'h0;
+    \8812 [1550] = 1'h0;
+    \8812 [1551] = 1'h0;
+    \8812 [1552] = 1'h0;
+    \8812 [1553] = 1'h0;
+    \8812 [1554] = 1'h0;
+    \8812 [1555] = 1'h0;
+    \8812 [1556] = 1'h0;
+    \8812 [1557] = 1'h0;
+    \8812 [1558] = 1'h0;
+    \8812 [1559] = 1'h0;
+    \8812 [1560] = 1'h0;
+    \8812 [1561] = 1'h0;
+    \8812 [1562] = 1'h0;
+    \8812 [1563] = 1'h0;
+    \8812 [1564] = 1'h0;
+    \8812 [1565] = 1'h0;
+    \8812 [1566] = 1'h0;
+    \8812 [1567] = 1'h0;
+    \8812 [1568] = 1'h0;
+    \8812 [1569] = 1'h0;
+    \8812 [1570] = 1'h0;
+    \8812 [1571] = 1'h0;
+    \8812 [1572] = 1'h0;
+    \8812 [1573] = 1'h0;
+    \8812 [1574] = 1'h0;
+    \8812 [1575] = 1'h0;
+    \8812 [1576] = 1'h0;
+    \8812 [1577] = 1'h0;
+    \8812 [1578] = 1'h0;
+    \8812 [1579] = 1'h0;
+    \8812 [1580] = 1'h0;
+    \8812 [1581] = 1'h0;
+    \8812 [1582] = 1'h0;
+    \8812 [1583] = 1'h0;
+    \8812 [1584] = 1'h0;
+    \8812 [1585] = 1'h0;
+    \8812 [1586] = 1'h0;
+    \8812 [1587] = 1'h0;
+    \8812 [1588] = 1'h0;
+    \8812 [1589] = 1'h0;
+    \8812 [1590] = 1'h0;
+    \8812 [1591] = 1'h0;
+    \8812 [1592] = 1'h0;
+    \8812 [1593] = 1'h0;
+    \8812 [1594] = 1'h0;
+    \8812 [1595] = 1'h0;
+    \8812 [1596] = 1'h0;
+    \8812 [1597] = 1'h0;
+    \8812 [1598] = 1'h0;
+    \8812 [1599] = 1'h0;
+    \8812 [1600] = 1'h0;
+    \8812 [1601] = 1'h0;
+    \8812 [1602] = 1'h0;
+    \8812 [1603] = 1'h0;
+    \8812 [1604] = 1'h0;
+    \8812 [1605] = 1'h0;
+    \8812 [1606] = 1'h0;
+    \8812 [1607] = 1'h0;
+    \8812 [1608] = 1'h0;
+    \8812 [1609] = 1'h0;
+    \8812 [1610] = 1'h0;
+    \8812 [1611] = 1'h0;
+    \8812 [1612] = 1'h0;
+    \8812 [1613] = 1'h0;
+    \8812 [1614] = 1'h0;
+    \8812 [1615] = 1'h0;
+    \8812 [1616] = 1'h0;
+    \8812 [1617] = 1'h0;
+    \8812 [1618] = 1'h0;
+    \8812 [1619] = 1'h0;
+    \8812 [1620] = 1'h0;
+    \8812 [1621] = 1'h0;
+    \8812 [1622] = 1'h0;
+    \8812 [1623] = 1'h0;
+    \8812 [1624] = 1'h0;
+    \8812 [1625] = 1'h0;
+    \8812 [1626] = 1'h0;
+    \8812 [1627] = 1'h0;
+    \8812 [1628] = 1'h0;
+    \8812 [1629] = 1'h0;
+    \8812 [1630] = 1'h0;
+    \8812 [1631] = 1'h0;
+    \8812 [1632] = 1'h0;
+    \8812 [1633] = 1'h0;
+    \8812 [1634] = 1'h0;
+    \8812 [1635] = 1'h0;
+    \8812 [1636] = 1'h0;
+    \8812 [1637] = 1'h0;
+    \8812 [1638] = 1'h0;
+    \8812 [1639] = 1'h0;
+    \8812 [1640] = 1'h0;
+    \8812 [1641] = 1'h0;
+    \8812 [1642] = 1'h0;
+    \8812 [1643] = 1'h0;
+    \8812 [1644] = 1'h0;
+    \8812 [1645] = 1'h0;
+    \8812 [1646] = 1'h0;
+    \8812 [1647] = 1'h0;
+    \8812 [1648] = 1'h0;
+    \8812 [1649] = 1'h0;
+    \8812 [1650] = 1'h0;
+    \8812 [1651] = 1'h0;
+    \8812 [1652] = 1'h0;
+    \8812 [1653] = 1'h0;
+    \8812 [1654] = 1'h0;
+    \8812 [1655] = 1'h0;
+    \8812 [1656] = 1'h0;
+    \8812 [1657] = 1'h0;
+    \8812 [1658] = 1'h0;
+    \8812 [1659] = 1'h0;
+    \8812 [1660] = 1'h0;
+    \8812 [1661] = 1'h0;
+    \8812 [1662] = 1'h0;
+    \8812 [1663] = 1'h0;
+    \8812 [1664] = 1'h0;
+    \8812 [1665] = 1'h0;
+    \8812 [1666] = 1'h0;
+    \8812 [1667] = 1'h0;
+    \8812 [1668] = 1'h0;
+    \8812 [1669] = 1'h0;
+    \8812 [1670] = 1'h0;
+    \8812 [1671] = 1'h0;
+    \8812 [1672] = 1'h0;
+    \8812 [1673] = 1'h0;
+    \8812 [1674] = 1'h0;
+    \8812 [1675] = 1'h0;
+    \8812 [1676] = 1'h0;
+    \8812 [1677] = 1'h0;
+    \8812 [1678] = 1'h0;
+    \8812 [1679] = 1'h0;
+    \8812 [1680] = 1'h0;
+    \8812 [1681] = 1'h0;
+    \8812 [1682] = 1'h0;
+    \8812 [1683] = 1'h0;
+    \8812 [1684] = 1'h0;
+    \8812 [1685] = 1'h0;
+    \8812 [1686] = 1'h0;
+    \8812 [1687] = 1'h0;
+    \8812 [1688] = 1'h0;
+    \8812 [1689] = 1'h0;
+    \8812 [1690] = 1'h0;
+    \8812 [1691] = 1'h0;
+    \8812 [1692] = 1'h0;
+    \8812 [1693] = 1'h0;
+    \8812 [1694] = 1'h0;
+    \8812 [1695] = 1'h0;
+    \8812 [1696] = 1'h0;
+    \8812 [1697] = 1'h0;
+    \8812 [1698] = 1'h0;
+    \8812 [1699] = 1'h0;
+    \8812 [1700] = 1'h0;
+    \8812 [1701] = 1'h0;
+    \8812 [1702] = 1'h0;
+    \8812 [1703] = 1'h0;
+    \8812 [1704] = 1'h0;
+    \8812 [1705] = 1'h0;
+    \8812 [1706] = 1'h0;
+    \8812 [1707] = 1'h0;
+    \8812 [1708] = 1'h0;
+    \8812 [1709] = 1'h0;
+    \8812 [1710] = 1'h0;
+    \8812 [1711] = 1'h0;
+    \8812 [1712] = 1'h0;
+    \8812 [1713] = 1'h0;
+    \8812 [1714] = 1'h0;
+    \8812 [1715] = 1'h0;
+    \8812 [1716] = 1'h0;
+    \8812 [1717] = 1'h0;
+    \8812 [1718] = 1'h0;
+    \8812 [1719] = 1'h0;
+    \8812 [1720] = 1'h0;
+    \8812 [1721] = 1'h0;
+    \8812 [1722] = 1'h0;
+    \8812 [1723] = 1'h0;
+    \8812 [1724] = 1'h0;
+    \8812 [1725] = 1'h0;
+    \8812 [1726] = 1'h0;
+    \8812 [1727] = 1'h0;
+    \8812 [1728] = 1'h0;
+    \8812 [1729] = 1'h0;
+    \8812 [1730] = 1'h0;
+    \8812 [1731] = 1'h0;
+    \8812 [1732] = 1'h0;
+    \8812 [1733] = 1'h0;
+    \8812 [1734] = 1'h0;
+    \8812 [1735] = 1'h0;
+    \8812 [1736] = 1'h0;
+    \8812 [1737] = 1'h0;
+    \8812 [1738] = 1'h0;
+    \8812 [1739] = 1'h0;
+    \8812 [1740] = 1'h0;
+    \8812 [1741] = 1'h0;
+    \8812 [1742] = 1'h0;
+    \8812 [1743] = 1'h0;
+    \8812 [1744] = 1'h0;
+    \8812 [1745] = 1'h0;
+    \8812 [1746] = 1'h0;
+    \8812 [1747] = 1'h0;
+    \8812 [1748] = 1'h0;
+    \8812 [1749] = 1'h0;
+    \8812 [1750] = 1'h0;
+    \8812 [1751] = 1'h0;
+    \8812 [1752] = 1'h0;
+    \8812 [1753] = 1'h0;
+    \8812 [1754] = 1'h0;
+    \8812 [1755] = 1'h0;
+    \8812 [1756] = 1'h0;
+    \8812 [1757] = 1'h0;
+    \8812 [1758] = 1'h0;
+    \8812 [1759] = 1'h0;
+    \8812 [1760] = 1'h0;
+    \8812 [1761] = 1'h0;
+    \8812 [1762] = 1'h0;
+    \8812 [1763] = 1'h0;
+    \8812 [1764] = 1'h0;
+    \8812 [1765] = 1'h0;
+    \8812 [1766] = 1'h0;
+    \8812 [1767] = 1'h0;
+    \8812 [1768] = 1'h0;
+    \8812 [1769] = 1'h0;
+    \8812 [1770] = 1'h0;
+    \8812 [1771] = 1'h0;
+    \8812 [1772] = 1'h0;
+    \8812 [1773] = 1'h0;
+    \8812 [1774] = 1'h0;
+    \8812 [1775] = 1'h0;
+    \8812 [1776] = 1'h0;
+    \8812 [1777] = 1'h0;
+    \8812 [1778] = 1'h0;
+    \8812 [1779] = 1'h0;
+    \8812 [1780] = 1'h0;
+    \8812 [1781] = 1'h0;
+    \8812 [1782] = 1'h0;
+    \8812 [1783] = 1'h0;
+    \8812 [1784] = 1'h0;
+    \8812 [1785] = 1'h0;
+    \8812 [1786] = 1'h0;
+    \8812 [1787] = 1'h0;
+    \8812 [1788] = 1'h0;
+    \8812 [1789] = 1'h0;
+    \8812 [1790] = 1'h0;
+    \8812 [1791] = 1'h0;
+    \8812 [1792] = 1'h0;
+    \8812 [1793] = 1'h0;
+    \8812 [1794] = 1'h0;
+    \8812 [1795] = 1'h0;
+    \8812 [1796] = 1'h0;
+    \8812 [1797] = 1'h0;
+    \8812 [1798] = 1'h0;
+    \8812 [1799] = 1'h0;
+    \8812 [1800] = 1'h0;
+    \8812 [1801] = 1'h0;
+    \8812 [1802] = 1'h0;
+    \8812 [1803] = 1'h0;
+    \8812 [1804] = 1'h0;
+    \8812 [1805] = 1'h0;
+    \8812 [1806] = 1'h0;
+    \8812 [1807] = 1'h0;
+    \8812 [1808] = 1'h0;
+    \8812 [1809] = 1'h0;
+    \8812 [1810] = 1'h0;
+    \8812 [1811] = 1'h0;
+    \8812 [1812] = 1'h0;
+    \8812 [1813] = 1'h0;
+    \8812 [1814] = 1'h0;
+    \8812 [1815] = 1'h0;
+    \8812 [1816] = 1'h0;
+    \8812 [1817] = 1'h0;
+    \8812 [1818] = 1'h0;
+    \8812 [1819] = 1'h0;
+    \8812 [1820] = 1'h0;
+    \8812 [1821] = 1'h0;
+    \8812 [1822] = 1'h0;
+    \8812 [1823] = 1'h0;
+    \8812 [1824] = 1'h0;
+    \8812 [1825] = 1'h0;
+    \8812 [1826] = 1'h0;
+    \8812 [1827] = 1'h0;
+    \8812 [1828] = 1'h0;
+    \8812 [1829] = 1'h0;
+    \8812 [1830] = 1'h0;
+    \8812 [1831] = 1'h0;
+    \8812 [1832] = 1'h0;
+    \8812 [1833] = 1'h0;
+    \8812 [1834] = 1'h0;
+    \8812 [1835] = 1'h0;
+    \8812 [1836] = 1'h0;
+    \8812 [1837] = 1'h0;
+    \8812 [1838] = 1'h0;
+    \8812 [1839] = 1'h0;
+    \8812 [1840] = 1'h0;
+    \8812 [1841] = 1'h0;
+    \8812 [1842] = 1'h0;
+    \8812 [1843] = 1'h0;
+    \8812 [1844] = 1'h0;
+    \8812 [1845] = 1'h0;
+    \8812 [1846] = 1'h0;
+    \8812 [1847] = 1'h0;
+    \8812 [1848] = 1'h0;
+    \8812 [1849] = 1'h0;
+    \8812 [1850] = 1'h0;
+    \8812 [1851] = 1'h0;
+    \8812 [1852] = 1'h0;
+    \8812 [1853] = 1'h0;
+    \8812 [1854] = 1'h0;
+    \8812 [1855] = 1'h0;
+    \8812 [1856] = 1'h0;
+    \8812 [1857] = 1'h0;
+    \8812 [1858] = 1'h0;
+    \8812 [1859] = 1'h0;
+    \8812 [1860] = 1'h0;
+    \8812 [1861] = 1'h0;
+    \8812 [1862] = 1'h0;
+    \8812 [1863] = 1'h0;
+    \8812 [1864] = 1'h0;
+    \8812 [1865] = 1'h0;
+    \8812 [1866] = 1'h0;
+    \8812 [1867] = 1'h0;
+    \8812 [1868] = 1'h0;
+    \8812 [1869] = 1'h0;
+    \8812 [1870] = 1'h0;
+    \8812 [1871] = 1'h0;
+    \8812 [1872] = 1'h0;
+    \8812 [1873] = 1'h0;
+    \8812 [1874] = 1'h0;
+    \8812 [1875] = 1'h0;
+    \8812 [1876] = 1'h0;
+    \8812 [1877] = 1'h0;
+    \8812 [1878] = 1'h0;
+    \8812 [1879] = 1'h0;
+    \8812 [1880] = 1'h0;
+    \8812 [1881] = 1'h0;
+    \8812 [1882] = 1'h0;
+    \8812 [1883] = 1'h0;
+    \8812 [1884] = 1'h0;
+    \8812 [1885] = 1'h0;
+    \8812 [1886] = 1'h0;
+    \8812 [1887] = 1'h0;
+    \8812 [1888] = 1'h0;
+    \8812 [1889] = 1'h0;
+    \8812 [1890] = 1'h0;
+    \8812 [1891] = 1'h0;
+    \8812 [1892] = 1'h0;
+    \8812 [1893] = 1'h0;
+    \8812 [1894] = 1'h0;
+    \8812 [1895] = 1'h0;
+    \8812 [1896] = 1'h0;
+    \8812 [1897] = 1'h0;
+    \8812 [1898] = 1'h0;
+    \8812 [1899] = 1'h0;
+    \8812 [1900] = 1'h0;
+    \8812 [1901] = 1'h0;
+    \8812 [1902] = 1'h0;
+    \8812 [1903] = 1'h0;
+    \8812 [1904] = 1'h0;
+    \8812 [1905] = 1'h0;
+    \8812 [1906] = 1'h0;
+    \8812 [1907] = 1'h0;
+    \8812 [1908] = 1'h0;
+    \8812 [1909] = 1'h0;
+    \8812 [1910] = 1'h0;
+    \8812 [1911] = 1'h0;
+    \8812 [1912] = 1'h0;
+    \8812 [1913] = 1'h0;
+    \8812 [1914] = 1'h0;
+    \8812 [1915] = 1'h0;
+    \8812 [1916] = 1'h0;
+    \8812 [1917] = 1'h0;
+    \8812 [1918] = 1'h0;
+    \8812 [1919] = 1'h0;
+    \8812 [1920] = 1'h0;
+    \8812 [1921] = 1'h0;
+    \8812 [1922] = 1'h0;
+    \8812 [1923] = 1'h0;
+    \8812 [1924] = 1'h0;
+    \8812 [1925] = 1'h0;
+    \8812 [1926] = 1'h0;
+    \8812 [1927] = 1'h0;
+    \8812 [1928] = 1'h0;
+    \8812 [1929] = 1'h0;
+    \8812 [1930] = 1'h0;
+    \8812 [1931] = 1'h0;
+    \8812 [1932] = 1'h0;
+    \8812 [1933] = 1'h0;
+    \8812 [1934] = 1'h0;
+    \8812 [1935] = 1'h0;
+    \8812 [1936] = 1'h0;
+    \8812 [1937] = 1'h0;
+    \8812 [1938] = 1'h0;
+    \8812 [1939] = 1'h0;
+    \8812 [1940] = 1'h0;
+    \8812 [1941] = 1'h0;
+    \8812 [1942] = 1'h0;
+    \8812 [1943] = 1'h0;
+    \8812 [1944] = 1'h0;
+    \8812 [1945] = 1'h0;
+    \8812 [1946] = 1'h0;
+    \8812 [1947] = 1'h0;
+    \8812 [1948] = 1'h0;
+    \8812 [1949] = 1'h0;
+    \8812 [1950] = 1'h0;
+    \8812 [1951] = 1'h0;
+    \8812 [1952] = 1'h0;
+    \8812 [1953] = 1'h0;
+    \8812 [1954] = 1'h0;
+    \8812 [1955] = 1'h0;
+    \8812 [1956] = 1'h0;
+    \8812 [1957] = 1'h0;
+    \8812 [1958] = 1'h0;
+    \8812 [1959] = 1'h0;
+    \8812 [1960] = 1'h0;
+    \8812 [1961] = 1'h0;
+    \8812 [1962] = 1'h0;
+    \8812 [1963] = 1'h0;
+    \8812 [1964] = 1'h0;
+    \8812 [1965] = 1'h0;
+    \8812 [1966] = 1'h0;
+    \8812 [1967] = 1'h0;
+    \8812 [1968] = 1'h0;
+    \8812 [1969] = 1'h0;
+    \8812 [1970] = 1'h0;
+    \8812 [1971] = 1'h0;
+    \8812 [1972] = 1'h0;
+    \8812 [1973] = 1'h0;
+    \8812 [1974] = 1'h0;
+    \8812 [1975] = 1'h0;
+    \8812 [1976] = 1'h0;
+    \8812 [1977] = 1'h0;
+    \8812 [1978] = 1'h0;
+    \8812 [1979] = 1'h0;
+    \8812 [1980] = 1'h0;
+    \8812 [1981] = 1'h0;
+    \8812 [1982] = 1'h0;
+    \8812 [1983] = 1'h0;
+    \8812 [1984] = 1'h0;
+    \8812 [1985] = 1'h0;
+    \8812 [1986] = 1'h0;
+    \8812 [1987] = 1'h0;
+    \8812 [1988] = 1'h0;
+    \8812 [1989] = 1'h0;
+    \8812 [1990] = 1'h0;
+    \8812 [1991] = 1'h0;
+    \8812 [1992] = 1'h0;
+    \8812 [1993] = 1'h0;
+    \8812 [1994] = 1'h0;
+    \8812 [1995] = 1'h0;
+    \8812 [1996] = 1'h0;
+    \8812 [1997] = 1'h0;
+    \8812 [1998] = 1'h0;
+    \8812 [1999] = 1'h0;
+    \8812 [2000] = 1'h0;
+    \8812 [2001] = 1'h0;
+    \8812 [2002] = 1'h0;
+    \8812 [2003] = 1'h0;
+    \8812 [2004] = 1'h0;
+    \8812 [2005] = 1'h0;
+    \8812 [2006] = 1'h0;
+    \8812 [2007] = 1'h0;
+    \8812 [2008] = 1'h0;
+    \8812 [2009] = 1'h0;
+    \8812 [2010] = 1'h0;
+    \8812 [2011] = 1'h0;
+    \8812 [2012] = 1'h0;
+    \8812 [2013] = 1'h0;
+    \8812 [2014] = 1'h0;
+    \8812 [2015] = 1'h0;
+    \8812 [2016] = 1'h0;
+    \8812 [2017] = 1'h0;
+    \8812 [2018] = 1'h0;
+    \8812 [2019] = 1'h0;
+    \8812 [2020] = 1'h0;
+    \8812 [2021] = 1'h0;
+    \8812 [2022] = 1'h0;
+    \8812 [2023] = 1'h0;
+    \8812 [2024] = 1'h0;
+    \8812 [2025] = 1'h0;
+    \8812 [2026] = 1'h0;
+    \8812 [2027] = 1'h0;
+    \8812 [2028] = 1'h0;
+    \8812 [2029] = 1'h0;
+    \8812 [2030] = 1'h0;
+    \8812 [2031] = 1'h0;
+    \8812 [2032] = 1'h0;
+    \8812 [2033] = 1'h0;
+    \8812 [2034] = 1'h0;
+    \8812 [2035] = 1'h0;
+    \8812 [2036] = 1'h0;
+    \8812 [2037] = 1'h0;
+    \8812 [2038] = 1'h0;
+    \8812 [2039] = 1'h0;
+    \8812 [2040] = 1'h0;
+    \8812 [2041] = 1'h0;
+    \8812 [2042] = 1'h0;
+    \8812 [2043] = 1'h0;
+    \8812 [2044] = 1'h0;
+    \8812 [2045] = 1'h0;
+    \8812 [2046] = 1'h0;
+    \8812 [2047] = 1'h0;
+  end
+  assign _127_ = \8812 [_027_];
+  reg [40:0] \8814  [63:0];
+  initial begin
+    \8814 [0] = 41'h00000000000;
+    \8814 [1] = 41'h00000000000;
+    \8814 [2] = 41'h00000000000;
+    \8814 [3] = 41'h00000000000;
+    \8814 [4] = 41'h00000000000;
+    \8814 [5] = 41'h00000000000;
+    \8814 [6] = 41'h00000000000;
+    \8814 [7] = 41'h00000000000;
+    \8814 [8] = 41'h00000000000;
+    \8814 [9] = 41'h00000000000;
+    \8814 [10] = 41'h00000000000;
+    \8814 [11] = 41'h00000000000;
+    \8814 [12] = 41'h050000509ad;
+    \8814 [13] = 41'h00000000000;
+    \8814 [14] = 41'h040000509b1;
+    \8814 [15] = 41'h050000509b1;
+    \8814 [16] = 41'h00000000000;
+    \8814 [17] = 41'h00000000000;
+    \8814 [18] = 41'h00000000000;
+    \8814 [19] = 41'h00000000000;
+    \8814 [20] = 41'h00000000000;
+    \8814 [21] = 41'h00000000000;
+    \8814 [22] = 41'h00000000000;
+    \8814 [23] = 41'h00000000000;
+    \8814 [24] = 41'h00000000000;
+    \8814 [25] = 41'h00000000000;
+    \8814 [26] = 41'h00000000000;
+    \8814 [27] = 41'h00000000000;
+    \8814 [28] = 41'h00000000000;
+    \8814 [29] = 41'h00000000000;
+    \8814 [30] = 41'h00000000000;
+    \8814 [31] = 41'h00000000000;
+    \8814 [32] = 41'h00000000000;
+    \8814 [33] = 41'h00000000000;
+    \8814 [34] = 41'h00000000000;
+    \8814 [35] = 41'h00000000000;
+    \8814 [36] = 41'h00000000000;
+    \8814 [37] = 41'h00000000000;
+    \8814 [38] = 41'h00000000000;
+    \8814 [39] = 41'h00000000000;
+    \8814 [40] = 41'h00000000000;
+    \8814 [41] = 41'h00000000000;
+    \8814 [42] = 41'h00000000000;
+    \8814 [43] = 41'h00000000000;
+    \8814 [44] = 41'h00000000000;
+    \8814 [45] = 41'h00000000000;
+    \8814 [46] = 41'h00000000000;
+    \8814 [47] = 41'h00000000000;
+    \8814 [48] = 41'h00000000000;
+    \8814 [49] = 41'h00000000000;
+    \8814 [50] = 41'h00000000000;
+    \8814 [51] = 41'h00000000000;
+    \8814 [52] = 41'h00000000000;
+    \8814 [53] = 41'h00000000000;
+    \8814 [54] = 41'h00000000000;
+    \8814 [55] = 41'h00000000000;
+    \8814 [56] = 41'h00000000000;
+    \8814 [57] = 41'h00000000000;
+    \8814 [58] = 41'h00000000000;
+    \8814 [59] = 41'h00000000000;
+    \8814 [60] = 41'h00000000000;
+    \8814 [61] = 41'h00000000000;
+    \8814 [62] = 41'h00000000000;
+    \8814 [63] = 41'h00000000000;
+  end
+  assign _129_ = \8814 [_029_];
+  reg [40:0] \8816  [1023:0];
+  initial begin
+    \8816 [0] = 41'h00000000000;
+    \8816 [1] = 41'h00000000000;
+    \8816 [2] = 41'h00000000000;
+    \8816 [3] = 41'h00000000000;
+    \8816 [4] = 41'h00000000000;
+    \8816 [5] = 41'h00000000000;
+    \8816 [6] = 41'h00000000000;
+    \8816 [7] = 41'h00000000000;
+    \8816 [8] = 41'h00000000000;
+    \8816 [9] = 41'h00000000a52;
+    \8816 [10] = 41'h00040008a82;
+    \8816 [11] = 41'h00000000000;
+    \8816 [12] = 41'h00000000000;
+    \8816 [13] = 41'h00000000000;
+    \8816 [14] = 41'h00000000000;
+    \8816 [15] = 41'h00000000000;
+    \8816 [16] = 41'h00000240a75;
+    \8816 [17] = 41'h00000000000;
+    \8816 [18] = 41'h00000000000;
+    \8816 [19] = 41'h00000000000;
+    \8816 [20] = 41'h05800040955;
+    \8816 [21] = 41'h00000000000;
+    \8816 [22] = 41'h05000040955;
+    \8816 [23] = 41'h00000000000;
+    \8816 [24] = 41'h00000000000;
+    \8816 [25] = 41'h00000000000;
+    \8816 [26] = 41'h00000000000;
+    \8816 [27] = 41'h00000000000;
+    \8816 [28] = 41'h00000000000;
+    \8816 [29] = 41'h00000000000;
+    \8816 [30] = 41'h00000000000;
+    \8816 [31] = 41'h00000000000;
+    \8816 [32] = 41'h00000000000;
+    \8816 [33] = 41'h00000000000;
+    \8816 [34] = 41'h00000000000;
+    \8816 [35] = 41'h00000000000;
+    \8816 [36] = 41'h00000000000;
+    \8816 [37] = 41'h0403008805d;
+    \8816 [38] = 41'h00000000000;
+    \8816 [39] = 41'h00000000000;
+    \8816 [40] = 41'h00030020a8a;
+    \8816 [41] = 41'h1000000006d;
+    \8816 [42] = 41'h00010008a82;
+    \8816 [43] = 41'h00000000000;
+    \8816 [44] = 41'h00000000000;
+    \8816 [45] = 41'h00000000000;
+    \8816 [46] = 41'h00000000000;
+    \8816 [47] = 41'h00000000000;
+    \8816 [48] = 41'h00000240a75;
+    \8816 [49] = 41'h00000000000;
+    \8816 [50] = 41'h00000000000;
+    \8816 [51] = 41'h00000000000;
+    \8816 [52] = 41'h04800040955;
+    \8816 [53] = 41'h00000000000;
+    \8816 [54] = 41'h04000040955;
+    \8816 [55] = 41'h00000000000;
+    \8816 [56] = 41'h00000000000;
+    \8816 [57] = 41'h00000000000;
+    \8816 [58] = 41'h00000000000;
+    \8816 [59] = 41'h00000000000;
+    \8816 [60] = 41'h00000000000;
+    \8816 [61] = 41'h00000000000;
+    \8816 [62] = 41'h00000000000;
+    \8816 [63] = 41'h00000000000;
+    \8816 [64] = 41'h00000000000;
+    \8816 [65] = 41'h00000000000;
+    \8816 [66] = 41'h00000000000;
+    \8816 [67] = 41'h00000000000;
+    \8816 [68] = 41'h00000000000;
+    \8816 [69] = 41'h0401008805d;
+    \8816 [70] = 41'h00000000000;
+    \8816 [71] = 41'h00000000000;
+    \8816 [72] = 41'h00000000000;
+    \8816 [73] = 41'h00000000000;
+    \8816 [74] = 41'h00020008a82;
+    \8816 [75] = 41'h00000000000;
+    \8816 [76] = 41'h00000000000;
+    \8816 [77] = 41'h00000000000;
+    \8816 [78] = 41'h00000000000;
+    \8816 [79] = 41'h00000000000;
+    \8816 [80] = 41'h00000240a75;
+    \8816 [81] = 41'h00000000000;
+    \8816 [82] = 41'h00000000000;
+    \8816 [83] = 41'h00000000000;
+    \8816 [84] = 41'h05800040959;
+    \8816 [85] = 41'h00000000000;
+    \8816 [86] = 41'h05000040959;
+    \8816 [87] = 41'h00000000000;
+    \8816 [88] = 41'h00000000000;
+    \8816 [89] = 41'h00000000000;
+    \8816 [90] = 41'h00000000000;
+    \8816 [91] = 41'h00000000000;
+    \8816 [92] = 41'h00000000000;
+    \8816 [93] = 41'h00000000000;
+    \8816 [94] = 41'h00000000000;
+    \8816 [95] = 41'h00000000000;
+    \8816 [96] = 41'h00000000000;
+    \8816 [97] = 41'h00000000000;
+    \8816 [98] = 41'h00000000000;
+    \8816 [99] = 41'h00000000000;
+    \8816 [100] = 41'h00000000000;
+    \8816 [101] = 41'h0402008805d;
+    \8816 [102] = 41'h00000000000;
+    \8816 [103] = 41'h00000000000;
+    \8816 [104] = 41'h00000000000;
+    \8816 [105] = 41'h000a0008a82;
+    \8816 [106] = 41'h00030008a82;
+    \8816 [107] = 41'h00000000000;
+    \8816 [108] = 41'h00000000000;
+    \8816 [109] = 41'h00000000000;
+    \8816 [110] = 41'h00000000000;
+    \8816 [111] = 41'h00000000000;
+    \8816 [112] = 41'h00000240a75;
+    \8816 [113] = 41'h00000000000;
+    \8816 [114] = 41'h00000000000;
+    \8816 [115] = 41'h00000000000;
+    \8816 [116] = 41'h04800040959;
+    \8816 [117] = 41'h00000000000;
+    \8816 [118] = 41'h04000040959;
+    \8816 [119] = 41'h00000000000;
+    \8816 [120] = 41'h00000000000;
+    \8816 [121] = 41'h00000000000;
+    \8816 [122] = 41'h00000000000;
+    \8816 [123] = 41'h00000000000;
+    \8816 [124] = 41'h00000000000;
+    \8816 [125] = 41'h00000000000;
+    \8816 [126] = 41'h00000000000;
+    \8816 [127] = 41'h00000000000;
+    \8816 [128] = 41'h00000000000;
+    \8816 [129] = 41'h00000000000;
+    \8816 [130] = 41'h00000000000;
+    \8816 [131] = 41'h00000000000;
+    \8816 [132] = 41'h0400008d861;
+    \8816 [133] = 41'h0400008d861;
+    \8816 [134] = 41'h00000000000;
+    \8816 [135] = 41'h00000000000;
+    \8816 [136] = 41'h00030100a86;
+    \8816 [137] = 41'h00000000000;
+    \8816 [138] = 41'h00040040a7e;
+    \8816 [139] = 41'h00000000000;
+    \8816 [140] = 41'h00000000000;
+    \8816 [141] = 41'h00000000000;
+    \8816 [142] = 41'h00000000000;
+    \8816 [143] = 41'h00000000000;
+    \8816 [144] = 41'h00000240a75;
+    \8816 [145] = 41'h00000000000;
+    \8816 [146] = 41'h00000000000;
+    \8816 [147] = 41'h00000000000;
+    \8816 [148] = 41'h00000000000;
+    \8816 [149] = 41'h00000000000;
+    \8816 [150] = 41'h00000000000;
+    \8816 [151] = 41'h00000000000;
+    \8816 [152] = 41'h00000000000;
+    \8816 [153] = 41'h00000000000;
+    \8816 [154] = 41'h00000000000;
+    \8816 [155] = 41'h00000000000;
+    \8816 [156] = 41'h00000000000;
+    \8816 [157] = 41'h00000000000;
+    \8816 [158] = 41'h00000000000;
+    \8816 [159] = 41'h00000000000;
+    \8816 [160] = 41'h00000000000;
+    \8816 [161] = 41'h00000000000;
+    \8816 [162] = 41'h00000000000;
+    \8816 [163] = 41'h00000000000;
+    \8816 [164] = 41'h00000000000;
+    \8816 [165] = 41'h00000000000;
+    \8816 [166] = 41'h00000000000;
+    \8816 [167] = 41'h00000000000;
+    \8816 [168] = 41'h00130100a86;
+    \8816 [169] = 41'h10000000005;
+    \8816 [170] = 41'h00010040a7e;
+    \8816 [171] = 41'h00000000000;
+    \8816 [172] = 41'h00000000000;
+    \8816 [173] = 41'h00000000000;
+    \8816 [174] = 41'h00000000000;
+    \8816 [175] = 41'h00000000000;
+    \8816 [176] = 41'h00000240a75;
+    \8816 [177] = 41'h00000000000;
+    \8816 [178] = 41'h00000000000;
+    \8816 [179] = 41'h00000000000;
+    \8816 [180] = 41'h00000000000;
+    \8816 [181] = 41'h00000000000;
+    \8816 [182] = 41'h00000000000;
+    \8816 [183] = 41'h00000000000;
+    \8816 [184] = 41'h00000000000;
+    \8816 [185] = 41'h00000000000;
+    \8816 [186] = 41'h00000000000;
+    \8816 [187] = 41'h00000000000;
+    \8816 [188] = 41'h00000000000;
+    \8816 [189] = 41'h00000000000;
+    \8816 [190] = 41'h00000000000;
+    \8816 [191] = 41'h00000000000;
+    \8816 [192] = 41'h00000000000;
+    \8816 [193] = 41'h00000000000;
+    \8816 [194] = 41'h00000000000;
+    \8816 [195] = 41'h00000000000;
+    \8816 [196] = 41'h0500808d8e1;
+    \8816 [197] = 41'h0500808d8e1;
+    \8816 [198] = 41'h00000000000;
+    \8816 [199] = 41'h0580808e0e1;
+    \8816 [200] = 41'h00000000000;
+    \8816 [201] = 41'h00000000000;
+    \8816 [202] = 41'h00020040a7e;
+    \8816 [203] = 41'h00000000000;
+    \8816 [204] = 41'h00000000000;
+    \8816 [205] = 41'h00000000000;
+    \8816 [206] = 41'h00000000000;
+    \8816 [207] = 41'h00000000000;
+    \8816 [208] = 41'h00000240a75;
+    \8816 [209] = 41'h00000000000;
+    \8816 [210] = 41'h00000000000;
+    \8816 [211] = 41'h00000000000;
+    \8816 [212] = 41'h00000000000;
+    \8816 [213] = 41'h00000000000;
+    \8816 [214] = 41'h00000000000;
+    \8816 [215] = 41'h00000000000;
+    \8816 [216] = 41'h00000000000;
+    \8816 [217] = 41'h00000000000;
+    \8816 [218] = 41'h00000000000;
+    \8816 [219] = 41'h00000000000;
+    \8816 [220] = 41'h00000000000;
+    \8816 [221] = 41'h00000000000;
+    \8816 [222] = 41'h00000000000;
+    \8816 [223] = 41'h00000000000;
+    \8816 [224] = 41'h00000000000;
+    \8816 [225] = 41'h00000000000;
+    \8816 [226] = 41'h00000000000;
+    \8816 [227] = 41'h00000000000;
+    \8816 [228] = 41'h00000000000;
+    \8816 [229] = 41'h050080888e1;
+    \8816 [230] = 41'h00000000000;
+    \8816 [231] = 41'h058080888e1;
+    \8816 [232] = 41'h00000000000;
+    \8816 [233] = 41'h000a0040a7e;
+    \8816 [234] = 41'h00030040a7e;
+    \8816 [235] = 41'h00000000000;
+    \8816 [236] = 41'h00000000000;
+    \8816 [237] = 41'h00000000000;
+    \8816 [238] = 41'h00000000000;
+    \8816 [239] = 41'h00000000000;
+    \8816 [240] = 41'h00000240a75;
+    \8816 [241] = 41'h00000000000;
+    \8816 [242] = 41'h00000000000;
+    \8816 [243] = 41'h00000000000;
+    \8816 [244] = 41'h0180004099d;
+    \8816 [245] = 41'h04000040909;
+    \8816 [246] = 41'h0100004099d;
+    \8816 [247] = 41'h00000000000;
+    \8816 [248] = 41'h00000000000;
+    \8816 [249] = 41'h00000000000;
+    \8816 [250] = 41'h00000000000;
+    \8816 [251] = 41'h00000000000;
+    \8816 [252] = 41'h00000000000;
+    \8816 [253] = 41'h00000000000;
+    \8816 [254] = 41'h00000000000;
+    \8816 [255] = 41'h00000000000;
+    \8816 [256] = 41'h00000000000;
+    \8816 [257] = 41'h00000000000;
+    \8816 [258] = 41'h00000000000;
+    \8816 [259] = 41'h00000000000;
+    \8816 [260] = 41'h00000000000;
+    \8816 [261] = 41'h00000000000;
+    \8816 [262] = 41'h00000000000;
+    \8816 [263] = 41'h00000000000;
+    \8816 [264] = 41'h00240020a8a;
+    \8816 [265] = 41'h00000000000;
+    \8816 [266] = 41'h00000000000;
+    \8816 [267] = 41'h00000000000;
+    \8816 [268] = 41'h0000004003d;
+    \8816 [269] = 41'h00000000005;
+    \8816 [270] = 41'h00000000000;
+    \8816 [271] = 41'h00000000000;
+    \8816 [272] = 41'h00000240a75;
+    \8816 [273] = 41'h00000000000;
+    \8816 [274] = 41'h00000000000;
+    \8816 [275] = 41'h00000000000;
+    \8816 [276] = 41'h058000409ad;
+    \8816 [277] = 41'h0400a045109;
+    \8816 [278] = 41'h050000409ad;
+    \8816 [279] = 41'h0400a845109;
+    \8816 [280] = 41'h00000000000;
+    \8816 [281] = 41'h00000000000;
+    \8816 [282] = 41'h00000000000;
+    \8816 [283] = 41'h00000000000;
+    \8816 [284] = 41'h00000000000;
+    \8816 [285] = 41'h00000000000;
+    \8816 [286] = 41'h00000000000;
+    \8816 [287] = 41'h00000000000;
+    \8816 [288] = 41'h00000000000;
+    \8816 [289] = 41'h00000000000;
+    \8816 [290] = 41'h00000000000;
+    \8816 [291] = 41'h00000000000;
+    \8816 [292] = 41'h00000000000;
+    \8816 [293] = 41'h00000000000;
+    \8816 [294] = 41'h00000000000;
+    \8816 [295] = 41'h00000000000;
+    \8816 [296] = 41'h00040020a8a;
+    \8816 [297] = 41'h02420008a82;
+    \8816 [298] = 41'h00000000000;
+    \8816 [299] = 41'h00000000000;
+    \8816 [300] = 41'h00000000000;
+    \8816 [301] = 41'h00000000005;
+    \8816 [302] = 41'h00000000000;
+    \8816 [303] = 41'h00000000000;
+    \8816 [304] = 41'h00000240a75;
+    \8816 [305] = 41'h00000000000;
+    \8816 [306] = 41'h00000000000;
+    \8816 [307] = 41'h00000000000;
+    \8816 [308] = 41'h00000000000;
+    \8816 [309] = 41'h0400a040109;
+    \8816 [310] = 41'h00000000000;
+    \8816 [311] = 41'h0400a840109;
+    \8816 [312] = 41'h00000000000;
+    \8816 [313] = 41'h00000000000;
+    \8816 [314] = 41'h00000000000;
+    \8816 [315] = 41'h00000000000;
+    \8816 [316] = 41'h00000000000;
+    \8816 [317] = 41'h00000000000;
+    \8816 [318] = 41'h00000000000;
+    \8816 [319] = 41'h00000000000;
+    \8816 [320] = 41'h00000000000;
+    \8816 [321] = 41'h00000000000;
+    \8816 [322] = 41'h00000000000;
+    \8816 [323] = 41'h00000000000;
+    \8816 [324] = 41'h00000000000;
+    \8816 [325] = 41'h00000000000;
+    \8816 [326] = 41'h00000000000;
+    \8816 [327] = 41'h00000000000;
+    \8816 [328] = 41'h00a30020a8a;
+    \8816 [329] = 41'h02410008a82;
+    \8816 [330] = 41'h00000000000;
+    \8816 [331] = 41'h00000000000;
+    \8816 [332] = 41'h00000000000;
+    \8816 [333] = 41'h00000000005;
+    \8816 [334] = 41'h00000000000;
+    \8816 [335] = 41'h00000000000;
+    \8816 [336] = 41'h00000240a75;
+    \8816 [337] = 41'h00000000000;
+    \8816 [338] = 41'h00000000000;
+    \8816 [339] = 41'h00000000000;
+    \8816 [340] = 41'h00000000000;
+    \8816 [341] = 41'h00000000000;
+    \8816 [342] = 41'h00000000000;
+    \8816 [343] = 41'h00000000000;
+    \8816 [344] = 41'h00000000000;
+    \8816 [345] = 41'h00000000000;
+    \8816 [346] = 41'h00000000000;
+    \8816 [347] = 41'h00000000000;
+    \8816 [348] = 41'h00000000000;
+    \8816 [349] = 41'h00000000000;
+    \8816 [350] = 41'h00000000000;
+    \8816 [351] = 41'h00000000000;
+    \8816 [352] = 41'h00000000000;
+    \8816 [353] = 41'h00000000000;
+    \8816 [354] = 41'h00000000000;
+    \8816 [355] = 41'h00000000000;
+    \8816 [356] = 41'h00000000000;
+    \8816 [357] = 41'h00000000000;
+    \8816 [358] = 41'h00000000000;
+    \8816 [359] = 41'h00000000000;
+    \8816 [360] = 41'h00830020a8a;
+    \8816 [361] = 41'h000b0008a82;
+    \8816 [362] = 41'h00000000000;
+    \8816 [363] = 41'h000c0008a82;
+    \8816 [364] = 41'h00000000000;
+    \8816 [365] = 41'h00000000005;
+    \8816 [366] = 41'h00000000000;
+    \8816 [367] = 41'h00000000000;
+    \8816 [368] = 41'h00000240a75;
+    \8816 [369] = 41'h00000000000;
+    \8816 [370] = 41'h00000000000;
+    \8816 [371] = 41'h00000000000;
+    \8816 [372] = 41'h00000000000;
+    \8816 [373] = 41'h0400a040909;
+    \8816 [374] = 41'h00000000000;
+    \8816 [375] = 41'h0400a840909;
+    \8816 [376] = 41'h00000000000;
+    \8816 [377] = 41'h00000000000;
+    \8816 [378] = 41'h00000000000;
+    \8816 [379] = 41'h00000000000;
+    \8816 [380] = 41'h00000000000;
+    \8816 [381] = 41'h00000000000;
+    \8816 [382] = 41'h00000000000;
+    \8816 [383] = 41'h00000000000;
+    \8816 [384] = 41'h00000000000;
+    \8816 [385] = 41'h00000000000;
+    \8816 [386] = 41'h00000000000;
+    \8816 [387] = 41'h00000000000;
+    \8816 [388] = 41'h00000000000;
+    \8816 [389] = 41'h00000000000;
+    \8816 [390] = 41'h00000000000;
+    \8816 [391] = 41'h00000000000;
+    \8816 [392] = 41'h00240100a86;
+    \8816 [393] = 41'h00000000000;
+    \8816 [394] = 41'h00000000000;
+    \8816 [395] = 41'h00000000000;
+    \8816 [396] = 41'h00000000000;
+    \8816 [397] = 41'h00000000005;
+    \8816 [398] = 41'h00000000000;
+    \8816 [399] = 41'h00000000000;
+    \8816 [400] = 41'h00000240a75;
+    \8816 [401] = 41'h00000000000;
+    \8816 [402] = 41'h00000000000;
+    \8816 [403] = 41'h00000000000;
+    \8816 [404] = 41'h00000000000;
+    \8816 [405] = 41'h00000000000;
+    \8816 [406] = 41'h00000000000;
+    \8816 [407] = 41'h04006840109;
+    \8816 [408] = 41'h00000000000;
+    \8816 [409] = 41'h00000000000;
+    \8816 [410] = 41'h00000000000;
+    \8816 [411] = 41'h00000000000;
+    \8816 [412] = 41'h00000000000;
+    \8816 [413] = 41'h00000000000;
+    \8816 [414] = 41'h00000000000;
+    \8816 [415] = 41'h00000000000;
+    \8816 [416] = 41'h00000000000;
+    \8816 [417] = 41'h00000000000;
+    \8816 [418] = 41'h00000000000;
+    \8816 [419] = 41'h00000000000;
+    \8816 [420] = 41'h00000000000;
+    \8816 [421] = 41'h00000000000;
+    \8816 [422] = 41'h00000000000;
+    \8816 [423] = 41'h00000000000;
+    \8816 [424] = 41'h00040100a86;
+    \8816 [425] = 41'h10000000005;
+    \8816 [426] = 41'h00000000000;
+    \8816 [427] = 41'h00000000000;
+    \8816 [428] = 41'h00000000000;
+    \8816 [429] = 41'h00000000005;
+    \8816 [430] = 41'h00000000000;
+    \8816 [431] = 41'h00000000000;
+    \8816 [432] = 41'h00000240a75;
+    \8816 [433] = 41'h00000000000;
+    \8816 [434] = 41'h00000000000;
+    \8816 [435] = 41'h00000000000;
+    \8816 [436] = 41'h058000409b5;
+    \8816 [437] = 41'h00000000000;
+    \8816 [438] = 41'h050000409b1;
+    \8816 [439] = 41'h00000000000;
+    \8816 [440] = 41'h00000000000;
+    \8816 [441] = 41'h00000000000;
+    \8816 [442] = 41'h00000000000;
+    \8816 [443] = 41'h00000000000;
+    \8816 [444] = 41'h00000000000;
+    \8816 [445] = 41'h00000000000;
+    \8816 [446] = 41'h00000000000;
+    \8816 [447] = 41'h0000040008d;
+    \8816 [448] = 41'h00000000000;
+    \8816 [449] = 41'h00000000000;
+    \8816 [450] = 41'h00000000000;
+    \8816 [451] = 41'h00000000000;
+    \8816 [452] = 41'h00000000000;
+    \8816 [453] = 41'h04000088035;
+    \8816 [454] = 41'h00000000000;
+    \8816 [455] = 41'h00000000000;
+    \8816 [456] = 41'h00a30100a86;
+    \8816 [457] = 41'h00000000000;
+    \8816 [458] = 41'h00000000000;
+    \8816 [459] = 41'h00000000000;
+    \8816 [460] = 41'h00000000000;
+    \8816 [461] = 41'h00000000005;
+    \8816 [462] = 41'h00000000000;
+    \8816 [463] = 41'h00000000000;
+    \8816 [464] = 41'h00000240a75;
+    \8816 [465] = 41'h00000000000;
+    \8816 [466] = 41'h00000000000;
+    \8816 [467] = 41'h00000000000;
+    \8816 [468] = 41'h00000000000;
+    \8816 [469] = 41'h00000000000;
+    \8816 [470] = 41'h00000000000;
+    \8816 [471] = 41'h04006840909;
+    \8816 [472] = 41'h00000000000;
+    \8816 [473] = 41'h00000000000;
+    \8816 [474] = 41'h00000000000;
+    \8816 [475] = 41'h00000000000;
+    \8816 [476] = 41'h00000000000;
+    \8816 [477] = 41'h00000000000;
+    \8816 [478] = 41'h00000000000;
+    \8816 [479] = 41'h00000000000;
+    \8816 [480] = 41'h00000000000;
+    \8816 [481] = 41'h00000000000;
+    \8816 [482] = 41'h00000000000;
+    \8816 [483] = 41'h00000000000;
+    \8816 [484] = 41'h040000888e1;
+    \8816 [485] = 41'h04800088035;
+    \8816 [486] = 41'h00000000000;
+    \8816 [487] = 41'h048000888e1;
+    \8816 [488] = 41'h00830100a86;
+    \8816 [489] = 41'h000b0040a7e;
+    \8816 [490] = 41'h00000000000;
+    \8816 [491] = 41'h000c0040a7e;
+    \8816 [492] = 41'h00000000000;
+    \8816 [493] = 41'h00000000005;
+    \8816 [494] = 41'h00000000000;
+    \8816 [495] = 41'h00000000000;
+    \8816 [496] = 41'h00000240a75;
+    \8816 [497] = 41'h00000000000;
+    \8816 [498] = 41'h00000000000;
+    \8816 [499] = 41'h00000000000;
+    \8816 [500] = 41'h048000409b5;
+    \8816 [501] = 41'h04008040909;
+    \8816 [502] = 41'h040000409b1;
+    \8816 [503] = 41'h0400e840909;
+    \8816 [504] = 41'h00000000000;
+    \8816 [505] = 41'h00000000000;
+    \8816 [506] = 41'h00000000000;
+    \8816 [507] = 41'h00000000000;
+    \8816 [508] = 41'h00000000000;
+    \8816 [509] = 41'h00000000000;
+    \8816 [510] = 41'h00000000000;
+    \8816 [511] = 41'h00000000000;
+    \8816 [512] = 41'h00000000000;
+    \8816 [513] = 41'h00000000000;
+    \8816 [514] = 41'h00000000000;
+    \8816 [515] = 41'h00000488829;
+    \8816 [516] = 41'h00000000000;
+    \8816 [517] = 41'h000400880bd;
+    \8816 [518] = 41'h00000000000;
+    \8816 [519] = 41'h00000000000;
+    \8816 [520] = 41'h00000000000;
+    \8816 [521] = 41'h00000000000;
+    \8816 [522] = 41'h00000000000;
+    \8816 [523] = 41'h00000000000;
+    \8816 [524] = 41'h00000000000;
+    \8816 [525] = 41'h000000000ea;
+    \8816 [526] = 41'h00000000000;
+    \8816 [527] = 41'h00000000000;
+    \8816 [528] = 41'h00000240a75;
+    \8816 [529] = 41'h00000000000;
+    \8816 [530] = 41'h00000000000;
+    \8816 [531] = 41'h00000000000;
+    \8816 [532] = 41'h05800040955;
+    \8816 [533] = 41'h00000000000;
+    \8816 [534] = 41'h05000040955;
+    \8816 [535] = 41'h00000000000;
+    \8816 [536] = 41'h00000000000;
+    \8816 [537] = 41'h00000000000;
+    \8816 [538] = 41'h00000000000;
+    \8816 [539] = 41'h00000000000;
+    \8816 [540] = 41'h00000000000;
+    \8816 [541] = 41'h00000000000;
+    \8816 [542] = 41'h00000000000;
+    \8816 [543] = 41'h00000000000;
+    \8816 [544] = 41'h00000000000;
+    \8816 [545] = 41'h00000000000;
+    \8816 [546] = 41'h00000000000;
+    \8816 [547] = 41'h0400108880d;
+    \8816 [548] = 41'h00000000000;
+    \8816 [549] = 41'h00000000000;
+    \8816 [550] = 41'h00000000000;
+    \8816 [551] = 41'h00000000000;
+    \8816 [552] = 41'h00000000000;
+    \8816 [553] = 41'h00000000000;
+    \8816 [554] = 41'h00000000000;
+    \8816 [555] = 41'h00000000000;
+    \8816 [556] = 41'h000000c80a9;
+    \8816 [557] = 41'h00000000000;
+    \8816 [558] = 41'h00000000000;
+    \8816 [559] = 41'h00000000000;
+    \8816 [560] = 41'h00000240a75;
+    \8816 [561] = 41'h00000000000;
+    \8816 [562] = 41'h00000000000;
+    \8816 [563] = 41'h00000000000;
+    \8816 [564] = 41'h04800040955;
+    \8816 [565] = 41'h00000000000;
+    \8816 [566] = 41'h04000040955;
+    \8816 [567] = 41'h00000000000;
+    \8816 [568] = 41'h00000000000;
+    \8816 [569] = 41'h00000000000;
+    \8816 [570] = 41'h00000000000;
+    \8816 [571] = 41'h00000000000;
+    \8816 [572] = 41'h00000000000;
+    \8816 [573] = 41'h00000000000;
+    \8816 [574] = 41'h00000000000;
+    \8816 [575] = 41'h00000000000;
+    \8816 [576] = 41'h00000000000;
+    \8816 [577] = 41'h00000000000;
+    \8816 [578] = 41'h00000000000;
+    \8816 [579] = 41'h040000888b9;
+    \8816 [580] = 41'h00000000000;
+    \8816 [581] = 41'h00000000000;
+    \8816 [582] = 41'h00000000000;
+    \8816 [583] = 41'h00000000000;
+    \8816 [584] = 41'h00220008a82;
+    \8816 [585] = 41'h00000000000;
+    \8816 [586] = 41'h00000000000;
+    \8816 [587] = 41'h00000000000;
+    \8816 [588] = 41'h00000000000;
+    \8816 [589] = 41'h00000000000;
+    \8816 [590] = 41'h00000000000;
+    \8816 [591] = 41'h00000000000;
+    \8816 [592] = 41'h00000240a75;
+    \8816 [593] = 41'h00000000000;
+    \8816 [594] = 41'h00000000000;
+    \8816 [595] = 41'h00000000000;
+    \8816 [596] = 41'h05800040959;
+    \8816 [597] = 41'h00000000000;
+    \8816 [598] = 41'h05000040959;
+    \8816 [599] = 41'h00000000000;
+    \8816 [600] = 41'h00000000000;
+    \8816 [601] = 41'h00000000000;
+    \8816 [602] = 41'h00000000000;
+    \8816 [603] = 41'h00000000000;
+    \8816 [604] = 41'h00000000000;
+    \8816 [605] = 41'h00000000000;
+    \8816 [606] = 41'h00000000000;
+    \8816 [607] = 41'h00000000000;
+    \8816 [608] = 41'h00000000000;
+    \8816 [609] = 41'h00000000000;
+    \8816 [610] = 41'h00000000000;
+    \8816 [611] = 41'h040008888b9;
+    \8816 [612] = 41'h00000000000;
+    \8816 [613] = 41'h00000000000;
+    \8816 [614] = 41'h00000000000;
+    \8816 [615] = 41'h00000000000;
+    \8816 [616] = 41'h00020008a82;
+    \8816 [617] = 41'h00000000000;
+    \8816 [618] = 41'h00000000000;
+    \8816 [619] = 41'h00000000000;
+    \8816 [620] = 41'h00000000000;
+    \8816 [621] = 41'h00000000000;
+    \8816 [622] = 41'h00000000000;
+    \8816 [623] = 41'h00000000000;
+    \8816 [624] = 41'h00000240a75;
+    \8816 [625] = 41'h00000000000;
+    \8816 [626] = 41'h00000000000;
+    \8816 [627] = 41'h00000000000;
+    \8816 [628] = 41'h04800040959;
+    \8816 [629] = 41'h00000000000;
+    \8816 [630] = 41'h04000040959;
+    \8816 [631] = 41'h00000000000;
+    \8816 [632] = 41'h00000000000;
+    \8816 [633] = 41'h00000000000;
+    \8816 [634] = 41'h00000000000;
+    \8816 [635] = 41'h00000000000;
+    \8816 [636] = 41'h00000000000;
+    \8816 [637] = 41'h00000000000;
+    \8816 [638] = 41'h00000000000;
+    \8816 [639] = 41'h00000000000;
+    \8816 [640] = 41'h00000000000;
+    \8816 [641] = 41'h00000000000;
+    \8816 [642] = 41'h00000000000;
+    \8816 [643] = 41'h00000000000;
+    \8816 [644] = 41'h00000000000;
+    \8816 [645] = 41'h000300880bd;
+    \8816 [646] = 41'h00000000000;
+    \8816 [647] = 41'h00000000000;
+    \8816 [648] = 41'h00320040a7e;
+    \8816 [649] = 41'h00000000000;
+    \8816 [650] = 41'h00330040a7e;
+    \8816 [651] = 41'h00000000000;
+    \8816 [652] = 41'h00000000000;
+    \8816 [653] = 41'h00000000000;
+    \8816 [654] = 41'h00000000000;
+    \8816 [655] = 41'h00000000000;
+    \8816 [656] = 41'h00000240a75;
+    \8816 [657] = 41'h00000000000;
+    \8816 [658] = 41'h00000000000;
+    \8816 [659] = 41'h00000000000;
+    \8816 [660] = 41'h00000000000;
+    \8816 [661] = 41'h00000000000;
+    \8816 [662] = 41'h00000000000;
+    \8816 [663] = 41'h00000000000;
+    \8816 [664] = 41'h00000000000;
+    \8816 [665] = 41'h00000000000;
+    \8816 [666] = 41'h00000000000;
+    \8816 [667] = 41'h00000000000;
+    \8816 [668] = 41'h00000000000;
+    \8816 [669] = 41'h00000000000;
+    \8816 [670] = 41'h00000000000;
+    \8816 [671] = 41'h00000000000;
+    \8816 [672] = 41'h00000000000;
+    \8816 [673] = 41'h00000000000;
+    \8816 [674] = 41'h00000000000;
+    \8816 [675] = 41'h00000000000;
+    \8816 [676] = 41'h00000000000;
+    \8816 [677] = 41'h00000000000;
+    \8816 [678] = 41'h00000000000;
+    \8816 [679] = 41'h00000000000;
+    \8816 [680] = 41'h00120040a7e;
+    \8816 [681] = 41'h00000000000;
+    \8816 [682] = 41'h00130040a7e;
+    \8816 [683] = 41'h00000000000;
+    \8816 [684] = 41'h00000048399;
+    \8816 [685] = 41'h00000000000;
+    \8816 [686] = 41'h00000000000;
+    \8816 [687] = 41'h00000000000;
+    \8816 [688] = 41'h00000240a75;
+    \8816 [689] = 41'h00000000000;
+    \8816 [690] = 41'h00000000000;
+    \8816 [691] = 41'h00000000000;
+    \8816 [692] = 41'h00000000000;
+    \8816 [693] = 41'h00000000000;
+    \8816 [694] = 41'h00000000000;
+    \8816 [695] = 41'h00000000000;
+    \8816 [696] = 41'h00000000000;
+    \8816 [697] = 41'h00000000000;
+    \8816 [698] = 41'h00000000000;
+    \8816 [699] = 41'h00000000000;
+    \8816 [700] = 41'h00000000000;
+    \8816 [701] = 41'h00000000000;
+    \8816 [702] = 41'h00000000000;
+    \8816 [703] = 41'h00000000000;
+    \8816 [704] = 41'h00000000000;
+    \8816 [705] = 41'h00000000000;
+    \8816 [706] = 41'h00000000000;
+    \8816 [707] = 41'h040000888f1;
+    \8816 [708] = 41'h00000000000;
+    \8816 [709] = 41'h000000880f5;
+    \8816 [710] = 41'h00000000000;
+    \8816 [711] = 41'h00000000000;
+    \8816 [712] = 41'h00220040a7e;
+    \8816 [713] = 41'h00000000000;
+    \8816 [714] = 41'h00000000000;
+    \8816 [715] = 41'h00000000000;
+    \8816 [716] = 41'h00000000000;
+    \8816 [717] = 41'h000000088ea;
+    \8816 [718] = 41'h00000000000;
+    \8816 [719] = 41'h00000000000;
+    \8816 [720] = 41'h00000240a75;
+    \8816 [721] = 41'h00000000000;
+    \8816 [722] = 41'h00000000000;
+    \8816 [723] = 41'h00000000000;
+    \8816 [724] = 41'h00000000000;
+    \8816 [725] = 41'h00000000000;
+    \8816 [726] = 41'h00000000000;
+    \8816 [727] = 41'h00000000000;
+    \8816 [728] = 41'h00000000000;
+    \8816 [729] = 41'h00000000000;
+    \8816 [730] = 41'h00000000000;
+    \8816 [731] = 41'h00000000000;
+    \8816 [732] = 41'h00000000000;
+    \8816 [733] = 41'h00000000000;
+    \8816 [734] = 41'h00000000000;
+    \8816 [735] = 41'h00000000000;
+    \8816 [736] = 41'h00000000000;
+    \8816 [737] = 41'h00000000000;
+    \8816 [738] = 41'h00000000000;
+    \8816 [739] = 41'h040010888f1;
+    \8816 [740] = 41'h00000000000;
+    \8816 [741] = 41'h000008880f5;
+    \8816 [742] = 41'h00000000000;
+    \8816 [743] = 41'h00000000000;
+    \8816 [744] = 41'h00020040a7e;
+    \8816 [745] = 41'h10000000049;
+    \8816 [746] = 41'h00000000000;
+    \8816 [747] = 41'h00000000000;
+    \8816 [748] = 41'h00000000000;
+    \8816 [749] = 41'h000000088ea;
+    \8816 [750] = 41'h00000000000;
+    \8816 [751] = 41'h00000000000;
+    \8816 [752] = 41'h00000240a75;
+    \8816 [753] = 41'h00000000000;
+    \8816 [754] = 41'h00000000000;
+    \8816 [755] = 41'h00000000000;
+    \8816 [756] = 41'h0080004099d;
+    \8816 [757] = 41'h04000040909;
+    \8816 [758] = 41'h0000004099d;
+    \8816 [759] = 41'h00000000000;
+    \8816 [760] = 41'h00000000000;
+    \8816 [761] = 41'h00000000000;
+    \8816 [762] = 41'h00000000000;
+    \8816 [763] = 41'h00000000000;
+    \8816 [764] = 41'h00000000000;
+    \8816 [765] = 41'h00000000000;
+    \8816 [766] = 41'h00000000000;
+    \8816 [767] = 41'h00000000000;
+    \8816 [768] = 41'h00000000000;
+    \8816 [769] = 41'h00000000000;
+    \8816 [770] = 41'h00000000000;
+    \8816 [771] = 41'h00000088021;
+    \8816 [772] = 41'h00000000000;
+    \8816 [773] = 41'h00000000000;
+    \8816 [774] = 41'h00000000000;
+    \8816 [775] = 41'h00000000000;
+    \8816 [776] = 41'h00210008a82;
+    \8816 [777] = 41'h1000000004d;
+    \8816 [778] = 41'h00000000000;
+    \8816 [779] = 41'h00000000000;
+    \8816 [780] = 41'h00000000000;
+    \8816 [781] = 41'h00000000000;
+    \8816 [782] = 41'h00000000000;
+    \8816 [783] = 41'h00000000000;
+    \8816 [784] = 41'h00000240a75;
+    \8816 [785] = 41'h00000000000;
+    \8816 [786] = 41'h00000000000;
+    \8816 [787] = 41'h00000000000;
+    \8816 [788] = 41'h058000409ad;
+    \8816 [789] = 41'h0400a045109;
+    \8816 [790] = 41'h050000409ad;
+    \8816 [791] = 41'h0400a845109;
+    \8816 [792] = 41'h00000000000;
+    \8816 [793] = 41'h00000000000;
+    \8816 [794] = 41'h00000000000;
+    \8816 [795] = 41'h00000000000;
+    \8816 [796] = 41'h00000000000;
+    \8816 [797] = 41'h00000000000;
+    \8816 [798] = 41'h00000000000;
+    \8816 [799] = 41'h0000040092d;
+    \8816 [800] = 41'h00000000000;
+    \8816 [801] = 41'h00000000000;
+    \8816 [802] = 41'h00000000000;
+    \8816 [803] = 41'h00000000000;
+    \8816 [804] = 41'h00000000000;
+    \8816 [805] = 41'h00000000000;
+    \8816 [806] = 41'h00000000000;
+    \8816 [807] = 41'h00000000000;
+    \8816 [808] = 41'h00010008a82;
+    \8816 [809] = 41'h02440008a82;
+    \8816 [810] = 41'h00000000000;
+    \8816 [811] = 41'h00000000000;
+    \8816 [812] = 41'h00000000000;
+    \8816 [813] = 41'h00000000000;
+    \8816 [814] = 41'h00000000000;
+    \8816 [815] = 41'h00000000000;
+    \8816 [816] = 41'h00000240a75;
+    \8816 [817] = 41'h00000000000;
+    \8816 [818] = 41'h00000000000;
+    \8816 [819] = 41'h00000000000;
+    \8816 [820] = 41'h00000000000;
+    \8816 [821] = 41'h0400a040109;
+    \8816 [822] = 41'h00000000000;
+    \8816 [823] = 41'h0400a840109;
+    \8816 [824] = 41'h00000000000;
+    \8816 [825] = 41'h00000000000;
+    \8816 [826] = 41'h00000000000;
+    \8816 [827] = 41'h00000000000;
+    \8816 [828] = 41'h00000000000;
+    \8816 [829] = 41'h00000000000;
+    \8816 [830] = 41'h00000000000;
+    \8816 [831] = 41'h00000400931;
+    \8816 [832] = 41'h00000000000;
+    \8816 [833] = 41'h00000000000;
+    \8816 [834] = 41'h00000000000;
+    \8816 [835] = 41'h00000000000;
+    \8816 [836] = 41'h00000000000;
+    \8816 [837] = 41'h000400880c1;
+    \8816 [838] = 41'h00000000000;
+    \8816 [839] = 41'h00000000000;
+    \8816 [840] = 41'h00230008a82;
+    \8816 [841] = 41'h00000000000;
+    \8816 [842] = 41'h00240008a82;
+    \8816 [843] = 41'h00000000000;
+    \8816 [844] = 41'h00000000000;
+    \8816 [845] = 41'h100000080a5;
+    \8816 [846] = 41'h00000000000;
+    \8816 [847] = 41'h00000000000;
+    \8816 [848] = 41'h00000240a75;
+    \8816 [849] = 41'h00000000000;
+    \8816 [850] = 41'h00000000000;
+    \8816 [851] = 41'h00000000000;
+    \8816 [852] = 41'h00000000000;
+    \8816 [853] = 41'h0400c040909;
+    \8816 [854] = 41'h00000000000;
+    \8816 [855] = 41'h00000000000;
+    \8816 [856] = 41'h00000000000;
+    \8816 [857] = 41'h00000000000;
+    \8816 [858] = 41'h00000000000;
+    \8816 [859] = 41'h00000000000;
+    \8816 [860] = 41'h00000000000;
+    \8816 [861] = 41'h00000000000;
+    \8816 [862] = 41'h00000000000;
+    \8816 [863] = 41'h00000000000;
+    \8816 [864] = 41'h00000000000;
+    \8816 [865] = 41'h00000000000;
+    \8816 [866] = 41'h00000000000;
+    \8816 [867] = 41'h00000000000;
+    \8816 [868] = 41'h00000000000;
+    \8816 [869] = 41'h000300880c1;
+    \8816 [870] = 41'h00000000000;
+    \8816 [871] = 41'h00000000000;
+    \8816 [872] = 41'h00030008a82;
+    \8816 [873] = 41'h02430008a82;
+    \8816 [874] = 41'h00040008a82;
+    \8816 [875] = 41'h00000000000;
+    \8816 [876] = 41'h00000000000;
+    \8816 [877] = 41'h108000080a5;
+    \8816 [878] = 41'h00000000000;
+    \8816 [879] = 41'h000004080a1;
+    \8816 [880] = 41'h00000240a75;
+    \8816 [881] = 41'h00000000000;
+    \8816 [882] = 41'h00000000000;
+    \8816 [883] = 41'h00000000000;
+    \8816 [884] = 41'h00000000000;
+    \8816 [885] = 41'h0400a040909;
+    \8816 [886] = 41'h00000000000;
+    \8816 [887] = 41'h0400a840909;
+    \8816 [888] = 41'h00000000000;
+    \8816 [889] = 41'h00000000000;
+    \8816 [890] = 41'h00000000000;
+    \8816 [891] = 41'h00000000000;
+    \8816 [892] = 41'h00000000000;
+    \8816 [893] = 41'h00000000000;
+    \8816 [894] = 41'h00000000000;
+    \8816 [895] = 41'h000002400d9;
+    \8816 [896] = 41'h00000000000;
+    \8816 [897] = 41'h00000000000;
+    \8816 [898] = 41'h00000000000;
+    \8816 [899] = 41'h040010888b9;
+    \8816 [900] = 41'h00000000000;
+    \8816 [901] = 41'h000100880bd;
+    \8816 [902] = 41'h00000000000;
+    \8816 [903] = 41'h00000000000;
+    \8816 [904] = 41'h00210040a7e;
+    \8816 [905] = 41'h00000000000;
+    \8816 [906] = 41'h00000000000;
+    \8816 [907] = 41'h00420040a7e;
+    \8816 [908] = 41'h00000000000;
+    \8816 [909] = 41'h00000000000;
+    \8816 [910] = 41'h00000000000;
+    \8816 [911] = 41'h00000000000;
+    \8816 [912] = 41'h00000240a75;
+    \8816 [913] = 41'h00000000000;
+    \8816 [914] = 41'h00000000000;
+    \8816 [915] = 41'h00000000000;
+    \8816 [916] = 41'h00000000000;
+    \8816 [917] = 41'h00000000000;
+    \8816 [918] = 41'h00000000000;
+    \8816 [919] = 41'h04006840109;
+    \8816 [920] = 41'h00000000000;
+    \8816 [921] = 41'h00000000000;
+    \8816 [922] = 41'h00000000000;
+    \8816 [923] = 41'h00000000000;
+    \8816 [924] = 41'h00000000000;
+    \8816 [925] = 41'h00000000000;
+    \8816 [926] = 41'h00000000000;
+    \8816 [927] = 41'h00000000000;
+    \8816 [928] = 41'h00000000000;
+    \8816 [929] = 41'h00000000000;
+    \8816 [930] = 41'h00000000000;
+    \8816 [931] = 41'h00000000000;
+    \8816 [932] = 41'h00000000000;
+    \8816 [933] = 41'h00000000000;
+    \8816 [934] = 41'h00000000000;
+    \8816 [935] = 41'h00000000000;
+    \8816 [936] = 41'h00010040a7e;
+    \8816 [937] = 41'h10000000041;
+    \8816 [938] = 41'h00000000000;
+    \8816 [939] = 41'h00440040a7e;
+    \8816 [940] = 41'h10000040095;
+    \8816 [941] = 41'h00000000000;
+    \8816 [942] = 41'h00000000000;
+    \8816 [943] = 41'h00000000000;
+    \8816 [944] = 41'h00000240a75;
+    \8816 [945] = 41'h00000000000;
+    \8816 [946] = 41'h00000000000;
+    \8816 [947] = 41'h00000000000;
+    \8816 [948] = 41'h058000409b5;
+    \8816 [949] = 41'h000000409f9;
+    \8816 [950] = 41'h050000409b1;
+    \8816 [951] = 41'h00000000000;
+    \8816 [952] = 41'h00000000000;
+    \8816 [953] = 41'h00000000000;
+    \8816 [954] = 41'h00000000000;
+    \8816 [955] = 41'h100000009ed;
+    \8816 [956] = 41'h00000000000;
+    \8816 [957] = 41'h00000000000;
+    \8816 [958] = 41'h00000000000;
+    \8816 [959] = 41'h00000000000;
+    \8816 [960] = 41'h00000000000;
+    \8816 [961] = 41'h00000000000;
+    \8816 [962] = 41'h00000000000;
+    \8816 [963] = 41'h0400088880d;
+    \8816 [964] = 41'h00000000000;
+    \8816 [965] = 41'h04000088035;
+    \8816 [966] = 41'h00000000000;
+    \8816 [967] = 41'h00000000000;
+    \8816 [968] = 41'h00230040a7e;
+    \8816 [969] = 41'h10000000045;
+    \8816 [970] = 41'h00240040a7e;
+    \8816 [971] = 41'h00410040a7e;
+    \8816 [972] = 41'h00000000000;
+    \8816 [973] = 41'h00000000000;
+    \8816 [974] = 41'h00000000000;
+    \8816 [975] = 41'h00000000000;
+    \8816 [976] = 41'h00000240a75;
+    \8816 [977] = 41'h00000000000;
+    \8816 [978] = 41'h00000000000;
+    \8816 [979] = 41'h00000000000;
+    \8816 [980] = 41'h00000000000;
+    \8816 [981] = 41'h00000000000;
+    \8816 [982] = 41'h00000000000;
+    \8816 [983] = 41'h04006840909;
+    \8816 [984] = 41'h00000000000;
+    \8816 [985] = 41'h00000000000;
+    \8816 [986] = 41'h00000000000;
+    \8816 [987] = 41'h00000000000;
+    \8816 [988] = 41'h00000000000;
+    \8816 [989] = 41'h00000000000;
+    \8816 [990] = 41'h00000000000;
+    \8816 [991] = 41'h00006c00925;
+    \8816 [992] = 41'h00000000000;
+    \8816 [993] = 41'h10000000005;
+    \8816 [994] = 41'h00000000000;
+    \8816 [995] = 41'h0400008880d;
+    \8816 [996] = 41'h040000888dd;
+    \8816 [997] = 41'h04800088035;
+    \8816 [998] = 41'h00000000000;
+    \8816 [999] = 41'h048000888dd;
+    \8816 [1000] = 41'h00030040a7e;
+    \8816 [1001] = 41'h10000000071;
+    \8816 [1002] = 41'h00040040a7e;
+    \8816 [1003] = 41'h00430040a7e;
+    \8816 [1004] = 41'h00000240091;
+    \8816 [1005] = 41'h00000000000;
+    \8816 [1006] = 41'h00000000000;
+    \8816 [1007] = 41'h00000000000;
+    \8816 [1008] = 41'h10000240a75;
+    \8816 [1009] = 41'h00000000000;
+    \8816 [1010] = 41'h00000000000;
+    \8816 [1011] = 41'h00000000000;
+    \8816 [1012] = 41'h048000409b5;
+    \8816 [1013] = 41'h04008040909;
+    \8816 [1014] = 41'h040000409b1;
+    \8816 [1015] = 41'h0400e840909;
+    \8816 [1016] = 41'h00000000000;
+    \8816 [1017] = 41'h00000000000;
+    \8816 [1018] = 41'h00000000000;
+    \8816 [1019] = 41'h108000009ed;
+    \8816 [1020] = 41'h00000000000;
+    \8816 [1021] = 41'h00000000000;
+    \8816 [1022] = 41'h00000000000;
+    \8816 [1023] = 41'h01006c00925;
+  end
+  assign _131_ = \8816 [_031_];
+  reg [0:0] \8818  [1023:0];
+  initial begin
+    \8818 [0] = 1'h0;
+    \8818 [1] = 1'h0;
+    \8818 [2] = 1'h0;
+    \8818 [3] = 1'h0;
+    \8818 [4] = 1'h0;
+    \8818 [5] = 1'h0;
+    \8818 [6] = 1'h0;
+    \8818 [7] = 1'h0;
+    \8818 [8] = 1'h0;
+    \8818 [9] = 1'h0;
+    \8818 [10] = 1'h0;
+    \8818 [11] = 1'h0;
+    \8818 [12] = 1'h0;
+    \8818 [13] = 1'h0;
+    \8818 [14] = 1'h0;
+    \8818 [15] = 1'h0;
+    \8818 [16] = 1'h0;
+    \8818 [17] = 1'h0;
+    \8818 [18] = 1'h0;
+    \8818 [19] = 1'h0;
+    \8818 [20] = 1'h0;
+    \8818 [21] = 1'h0;
+    \8818 [22] = 1'h0;
+    \8818 [23] = 1'h0;
+    \8818 [24] = 1'h0;
+    \8818 [25] = 1'h0;
+    \8818 [26] = 1'h0;
+    \8818 [27] = 1'h0;
+    \8818 [28] = 1'h0;
+    \8818 [29] = 1'h0;
+    \8818 [30] = 1'h0;
+    \8818 [31] = 1'h0;
+    \8818 [32] = 1'h0;
+    \8818 [33] = 1'h0;
+    \8818 [34] = 1'h0;
+    \8818 [35] = 1'h0;
+    \8818 [36] = 1'h0;
+    \8818 [37] = 1'h0;
+    \8818 [38] = 1'h0;
+    \8818 [39] = 1'h0;
+    \8818 [40] = 1'h0;
+    \8818 [41] = 1'h0;
+    \8818 [42] = 1'h0;
+    \8818 [43] = 1'h0;
+    \8818 [44] = 1'h0;
+    \8818 [45] = 1'h0;
+    \8818 [46] = 1'h0;
+    \8818 [47] = 1'h0;
+    \8818 [48] = 1'h0;
+    \8818 [49] = 1'h0;
+    \8818 [50] = 1'h0;
+    \8818 [51] = 1'h0;
+    \8818 [52] = 1'h0;
+    \8818 [53] = 1'h0;
+    \8818 [54] = 1'h0;
+    \8818 [55] = 1'h0;
+    \8818 [56] = 1'h0;
+    \8818 [57] = 1'h0;
+    \8818 [58] = 1'h0;
+    \8818 [59] = 1'h0;
+    \8818 [60] = 1'h0;
+    \8818 [61] = 1'h0;
+    \8818 [62] = 1'h0;
+    \8818 [63] = 1'h0;
+    \8818 [64] = 1'h0;
+    \8818 [65] = 1'h0;
+    \8818 [66] = 1'h0;
+    \8818 [67] = 1'h0;
+    \8818 [68] = 1'h0;
+    \8818 [69] = 1'h0;
+    \8818 [70] = 1'h0;
+    \8818 [71] = 1'h0;
+    \8818 [72] = 1'h0;
+    \8818 [73] = 1'h0;
+    \8818 [74] = 1'h0;
+    \8818 [75] = 1'h0;
+    \8818 [76] = 1'h0;
+    \8818 [77] = 1'h0;
+    \8818 [78] = 1'h0;
+    \8818 [79] = 1'h0;
+    \8818 [80] = 1'h0;
+    \8818 [81] = 1'h0;
+    \8818 [82] = 1'h0;
+    \8818 [83] = 1'h0;
+    \8818 [84] = 1'h0;
+    \8818 [85] = 1'h0;
+    \8818 [86] = 1'h0;
+    \8818 [87] = 1'h0;
+    \8818 [88] = 1'h0;
+    \8818 [89] = 1'h0;
+    \8818 [90] = 1'h0;
+    \8818 [91] = 1'h0;
+    \8818 [92] = 1'h0;
+    \8818 [93] = 1'h0;
+    \8818 [94] = 1'h0;
+    \8818 [95] = 1'h0;
+    \8818 [96] = 1'h0;
+    \8818 [97] = 1'h0;
+    \8818 [98] = 1'h0;
+    \8818 [99] = 1'h0;
+    \8818 [100] = 1'h0;
+    \8818 [101] = 1'h0;
+    \8818 [102] = 1'h0;
+    \8818 [103] = 1'h0;
+    \8818 [104] = 1'h0;
+    \8818 [105] = 1'h0;
+    \8818 [106] = 1'h0;
+    \8818 [107] = 1'h0;
+    \8818 [108] = 1'h0;
+    \8818 [109] = 1'h0;
+    \8818 [110] = 1'h0;
+    \8818 [111] = 1'h0;
+    \8818 [112] = 1'h0;
+    \8818 [113] = 1'h0;
+    \8818 [114] = 1'h0;
+    \8818 [115] = 1'h0;
+    \8818 [116] = 1'h0;
+    \8818 [117] = 1'h0;
+    \8818 [118] = 1'h0;
+    \8818 [119] = 1'h0;
+    \8818 [120] = 1'h0;
+    \8818 [121] = 1'h0;
+    \8818 [122] = 1'h0;
+    \8818 [123] = 1'h0;
+    \8818 [124] = 1'h0;
+    \8818 [125] = 1'h0;
+    \8818 [126] = 1'h0;
+    \8818 [127] = 1'h0;
+    \8818 [128] = 1'h0;
+    \8818 [129] = 1'h0;
+    \8818 [130] = 1'h0;
+    \8818 [131] = 1'h0;
+    \8818 [132] = 1'h0;
+    \8818 [133] = 1'h0;
+    \8818 [134] = 1'h0;
+    \8818 [135] = 1'h0;
+    \8818 [136] = 1'h0;
+    \8818 [137] = 1'h0;
+    \8818 [138] = 1'h0;
+    \8818 [139] = 1'h0;
+    \8818 [140] = 1'h0;
+    \8818 [141] = 1'h0;
+    \8818 [142] = 1'h0;
+    \8818 [143] = 1'h0;
+    \8818 [144] = 1'h0;
+    \8818 [145] = 1'h0;
+    \8818 [146] = 1'h0;
+    \8818 [147] = 1'h0;
+    \8818 [148] = 1'h0;
+    \8818 [149] = 1'h0;
+    \8818 [150] = 1'h0;
+    \8818 [151] = 1'h0;
+    \8818 [152] = 1'h0;
+    \8818 [153] = 1'h0;
+    \8818 [154] = 1'h0;
+    \8818 [155] = 1'h0;
+    \8818 [156] = 1'h0;
+    \8818 [157] = 1'h0;
+    \8818 [158] = 1'h0;
+    \8818 [159] = 1'h0;
+    \8818 [160] = 1'h0;
+    \8818 [161] = 1'h0;
+    \8818 [162] = 1'h0;
+    \8818 [163] = 1'h0;
+    \8818 [164] = 1'h0;
+    \8818 [165] = 1'h0;
+    \8818 [166] = 1'h0;
+    \8818 [167] = 1'h0;
+    \8818 [168] = 1'h0;
+    \8818 [169] = 1'h0;
+    \8818 [170] = 1'h0;
+    \8818 [171] = 1'h0;
+    \8818 [172] = 1'h0;
+    \8818 [173] = 1'h0;
+    \8818 [174] = 1'h0;
+    \8818 [175] = 1'h0;
+    \8818 [176] = 1'h0;
+    \8818 [177] = 1'h0;
+    \8818 [178] = 1'h0;
+    \8818 [179] = 1'h0;
+    \8818 [180] = 1'h0;
+    \8818 [181] = 1'h0;
+    \8818 [182] = 1'h0;
+    \8818 [183] = 1'h0;
+    \8818 [184] = 1'h0;
+    \8818 [185] = 1'h0;
+    \8818 [186] = 1'h0;
+    \8818 [187] = 1'h0;
+    \8818 [188] = 1'h0;
+    \8818 [189] = 1'h0;
+    \8818 [190] = 1'h0;
+    \8818 [191] = 1'h0;
+    \8818 [192] = 1'h0;
+    \8818 [193] = 1'h0;
+    \8818 [194] = 1'h0;
+    \8818 [195] = 1'h0;
+    \8818 [196] = 1'h0;
+    \8818 [197] = 1'h0;
+    \8818 [198] = 1'h0;
+    \8818 [199] = 1'h0;
+    \8818 [200] = 1'h0;
+    \8818 [201] = 1'h0;
+    \8818 [202] = 1'h0;
+    \8818 [203] = 1'h0;
+    \8818 [204] = 1'h0;
+    \8818 [205] = 1'h0;
+    \8818 [206] = 1'h0;
+    \8818 [207] = 1'h0;
+    \8818 [208] = 1'h0;
+    \8818 [209] = 1'h0;
+    \8818 [210] = 1'h0;
+    \8818 [211] = 1'h0;
+    \8818 [212] = 1'h0;
+    \8818 [213] = 1'h0;
+    \8818 [214] = 1'h0;
+    \8818 [215] = 1'h0;
+    \8818 [216] = 1'h0;
+    \8818 [217] = 1'h0;
+    \8818 [218] = 1'h0;
+    \8818 [219] = 1'h0;
+    \8818 [220] = 1'h0;
+    \8818 [221] = 1'h0;
+    \8818 [222] = 1'h0;
+    \8818 [223] = 1'h0;
+    \8818 [224] = 1'h0;
+    \8818 [225] = 1'h0;
+    \8818 [226] = 1'h0;
+    \8818 [227] = 1'h0;
+    \8818 [228] = 1'h0;
+    \8818 [229] = 1'h0;
+    \8818 [230] = 1'h0;
+    \8818 [231] = 1'h0;
+    \8818 [232] = 1'h0;
+    \8818 [233] = 1'h0;
+    \8818 [234] = 1'h0;
+    \8818 [235] = 1'h0;
+    \8818 [236] = 1'h0;
+    \8818 [237] = 1'h0;
+    \8818 [238] = 1'h0;
+    \8818 [239] = 1'h0;
+    \8818 [240] = 1'h0;
+    \8818 [241] = 1'h0;
+    \8818 [242] = 1'h0;
+    \8818 [243] = 1'h0;
+    \8818 [244] = 1'h0;
+    \8818 [245] = 1'h0;
+    \8818 [246] = 1'h0;
+    \8818 [247] = 1'h0;
+    \8818 [248] = 1'h0;
+    \8818 [249] = 1'h0;
+    \8818 [250] = 1'h0;
+    \8818 [251] = 1'h0;
+    \8818 [252] = 1'h0;
+    \8818 [253] = 1'h0;
+    \8818 [254] = 1'h0;
+    \8818 [255] = 1'h0;
+    \8818 [256] = 1'h0;
+    \8818 [257] = 1'h0;
+    \8818 [258] = 1'h0;
+    \8818 [259] = 1'h0;
+    \8818 [260] = 1'h0;
+    \8818 [261] = 1'h0;
+    \8818 [262] = 1'h0;
+    \8818 [263] = 1'h0;
+    \8818 [264] = 1'h0;
+    \8818 [265] = 1'h0;
+    \8818 [266] = 1'h0;
+    \8818 [267] = 1'h0;
+    \8818 [268] = 1'h0;
+    \8818 [269] = 1'h0;
+    \8818 [270] = 1'h0;
+    \8818 [271] = 1'h0;
+    \8818 [272] = 1'h0;
+    \8818 [273] = 1'h0;
+    \8818 [274] = 1'h0;
+    \8818 [275] = 1'h0;
+    \8818 [276] = 1'h0;
+    \8818 [277] = 1'h0;
+    \8818 [278] = 1'h0;
+    \8818 [279] = 1'h0;
+    \8818 [280] = 1'h0;
+    \8818 [281] = 1'h0;
+    \8818 [282] = 1'h0;
+    \8818 [283] = 1'h0;
+    \8818 [284] = 1'h0;
+    \8818 [285] = 1'h0;
+    \8818 [286] = 1'h0;
+    \8818 [287] = 1'h0;
+    \8818 [288] = 1'h0;
+    \8818 [289] = 1'h0;
+    \8818 [290] = 1'h0;
+    \8818 [291] = 1'h0;
+    \8818 [292] = 1'h0;
+    \8818 [293] = 1'h0;
+    \8818 [294] = 1'h0;
+    \8818 [295] = 1'h0;
+    \8818 [296] = 1'h0;
+    \8818 [297] = 1'h0;
+    \8818 [298] = 1'h0;
+    \8818 [299] = 1'h0;
+    \8818 [300] = 1'h0;
+    \8818 [301] = 1'h0;
+    \8818 [302] = 1'h0;
+    \8818 [303] = 1'h0;
+    \8818 [304] = 1'h0;
+    \8818 [305] = 1'h0;
+    \8818 [306] = 1'h0;
+    \8818 [307] = 1'h0;
+    \8818 [308] = 1'h0;
+    \8818 [309] = 1'h0;
+    \8818 [310] = 1'h0;
+    \8818 [311] = 1'h0;
+    \8818 [312] = 1'h0;
+    \8818 [313] = 1'h0;
+    \8818 [314] = 1'h0;
+    \8818 [315] = 1'h1;
+    \8818 [316] = 1'h0;
+    \8818 [317] = 1'h0;
+    \8818 [318] = 1'h0;
+    \8818 [319] = 1'h0;
+    \8818 [320] = 1'h0;
+    \8818 [321] = 1'h0;
+    \8818 [322] = 1'h0;
+    \8818 [323] = 1'h0;
+    \8818 [324] = 1'h0;
+    \8818 [325] = 1'h0;
+    \8818 [326] = 1'h0;
+    \8818 [327] = 1'h0;
+    \8818 [328] = 1'h0;
+    \8818 [329] = 1'h0;
+    \8818 [330] = 1'h0;
+    \8818 [331] = 1'h0;
+    \8818 [332] = 1'h0;
+    \8818 [333] = 1'h0;
+    \8818 [334] = 1'h0;
+    \8818 [335] = 1'h0;
+    \8818 [336] = 1'h0;
+    \8818 [337] = 1'h0;
+    \8818 [338] = 1'h0;
+    \8818 [339] = 1'h0;
+    \8818 [340] = 1'h0;
+    \8818 [341] = 1'h0;
+    \8818 [342] = 1'h0;
+    \8818 [343] = 1'h0;
+    \8818 [344] = 1'h0;
+    \8818 [345] = 1'h0;
+    \8818 [346] = 1'h0;
+    \8818 [347] = 1'h0;
+    \8818 [348] = 1'h0;
+    \8818 [349] = 1'h0;
+    \8818 [350] = 1'h0;
+    \8818 [351] = 1'h0;
+    \8818 [352] = 1'h0;
+    \8818 [353] = 1'h0;
+    \8818 [354] = 1'h0;
+    \8818 [355] = 1'h0;
+    \8818 [356] = 1'h0;
+    \8818 [357] = 1'h0;
+    \8818 [358] = 1'h0;
+    \8818 [359] = 1'h0;
+    \8818 [360] = 1'h0;
+    \8818 [361] = 1'h0;
+    \8818 [362] = 1'h0;
+    \8818 [363] = 1'h0;
+    \8818 [364] = 1'h0;
+    \8818 [365] = 1'h0;
+    \8818 [366] = 1'h0;
+    \8818 [367] = 1'h0;
+    \8818 [368] = 1'h0;
+    \8818 [369] = 1'h0;
+    \8818 [370] = 1'h0;
+    \8818 [371] = 1'h0;
+    \8818 [372] = 1'h0;
+    \8818 [373] = 1'h0;
+    \8818 [374] = 1'h0;
+    \8818 [375] = 1'h0;
+    \8818 [376] = 1'h0;
+    \8818 [377] = 1'h0;
+    \8818 [378] = 1'h0;
+    \8818 [379] = 1'h0;
+    \8818 [380] = 1'h0;
+    \8818 [381] = 1'h0;
+    \8818 [382] = 1'h0;
+    \8818 [383] = 1'h0;
+    \8818 [384] = 1'h0;
+    \8818 [385] = 1'h0;
+    \8818 [386] = 1'h0;
+    \8818 [387] = 1'h0;
+    \8818 [388] = 1'h0;
+    \8818 [389] = 1'h0;
+    \8818 [390] = 1'h0;
+    \8818 [391] = 1'h0;
+    \8818 [392] = 1'h0;
+    \8818 [393] = 1'h0;
+    \8818 [394] = 1'h0;
+    \8818 [395] = 1'h0;
+    \8818 [396] = 1'h0;
+    \8818 [397] = 1'h0;
+    \8818 [398] = 1'h0;
+    \8818 [399] = 1'h0;
+    \8818 [400] = 1'h0;
+    \8818 [401] = 1'h0;
+    \8818 [402] = 1'h0;
+    \8818 [403] = 1'h0;
+    \8818 [404] = 1'h0;
+    \8818 [405] = 1'h0;
+    \8818 [406] = 1'h0;
+    \8818 [407] = 1'h0;
+    \8818 [408] = 1'h0;
+    \8818 [409] = 1'h0;
+    \8818 [410] = 1'h0;
+    \8818 [411] = 1'h0;
+    \8818 [412] = 1'h0;
+    \8818 [413] = 1'h0;
+    \8818 [414] = 1'h0;
+    \8818 [415] = 1'h0;
+    \8818 [416] = 1'h0;
+    \8818 [417] = 1'h0;
+    \8818 [418] = 1'h0;
+    \8818 [419] = 1'h0;
+    \8818 [420] = 1'h0;
+    \8818 [421] = 1'h0;
+    \8818 [422] = 1'h0;
+    \8818 [423] = 1'h0;
+    \8818 [424] = 1'h0;
+    \8818 [425] = 1'h0;
+    \8818 [426] = 1'h0;
+    \8818 [427] = 1'h0;
+    \8818 [428] = 1'h0;
+    \8818 [429] = 1'h0;
+    \8818 [430] = 1'h0;
+    \8818 [431] = 1'h0;
+    \8818 [432] = 1'h0;
+    \8818 [433] = 1'h0;
+    \8818 [434] = 1'h0;
+    \8818 [435] = 1'h0;
+    \8818 [436] = 1'h0;
+    \8818 [437] = 1'h0;
+    \8818 [438] = 1'h0;
+    \8818 [439] = 1'h0;
+    \8818 [440] = 1'h0;
+    \8818 [441] = 1'h0;
+    \8818 [442] = 1'h0;
+    \8818 [443] = 1'h0;
+    \8818 [444] = 1'h0;
+    \8818 [445] = 1'h0;
+    \8818 [446] = 1'h0;
+    \8818 [447] = 1'h1;
+    \8818 [448] = 1'h0;
+    \8818 [449] = 1'h0;
+    \8818 [450] = 1'h0;
+    \8818 [451] = 1'h0;
+    \8818 [452] = 1'h0;
+    \8818 [453] = 1'h0;
+    \8818 [454] = 1'h0;
+    \8818 [455] = 1'h0;
+    \8818 [456] = 1'h0;
+    \8818 [457] = 1'h0;
+    \8818 [458] = 1'h0;
+    \8818 [459] = 1'h0;
+    \8818 [460] = 1'h0;
+    \8818 [461] = 1'h0;
+    \8818 [462] = 1'h0;
+    \8818 [463] = 1'h0;
+    \8818 [464] = 1'h0;
+    \8818 [465] = 1'h0;
+    \8818 [466] = 1'h0;
+    \8818 [467] = 1'h0;
+    \8818 [468] = 1'h0;
+    \8818 [469] = 1'h0;
+    \8818 [470] = 1'h0;
+    \8818 [471] = 1'h0;
+    \8818 [472] = 1'h0;
+    \8818 [473] = 1'h0;
+    \8818 [474] = 1'h0;
+    \8818 [475] = 1'h0;
+    \8818 [476] = 1'h0;
+    \8818 [477] = 1'h0;
+    \8818 [478] = 1'h0;
+    \8818 [479] = 1'h0;
+    \8818 [480] = 1'h0;
+    \8818 [481] = 1'h0;
+    \8818 [482] = 1'h0;
+    \8818 [483] = 1'h0;
+    \8818 [484] = 1'h0;
+    \8818 [485] = 1'h0;
+    \8818 [486] = 1'h0;
+    \8818 [487] = 1'h0;
+    \8818 [488] = 1'h0;
+    \8818 [489] = 1'h0;
+    \8818 [490] = 1'h0;
+    \8818 [491] = 1'h0;
+    \8818 [492] = 1'h0;
+    \8818 [493] = 1'h0;
+    \8818 [494] = 1'h1;
+    \8818 [495] = 1'h1;
+    \8818 [496] = 1'h0;
+    \8818 [497] = 1'h0;
+    \8818 [498] = 1'h0;
+    \8818 [499] = 1'h0;
+    \8818 [500] = 1'h0;
+    \8818 [501] = 1'h0;
+    \8818 [502] = 1'h0;
+    \8818 [503] = 1'h0;
+    \8818 [504] = 1'h0;
+    \8818 [505] = 1'h0;
+    \8818 [506] = 1'h0;
+    \8818 [507] = 1'h0;
+    \8818 [508] = 1'h0;
+    \8818 [509] = 1'h0;
+    \8818 [510] = 1'h0;
+    \8818 [511] = 1'h1;
+    \8818 [512] = 1'h0;
+    \8818 [513] = 1'h0;
+    \8818 [514] = 1'h0;
+    \8818 [515] = 1'h0;
+    \8818 [516] = 1'h0;
+    \8818 [517] = 1'h0;
+    \8818 [518] = 1'h0;
+    \8818 [519] = 1'h0;
+    \8818 [520] = 1'h0;
+    \8818 [521] = 1'h0;
+    \8818 [522] = 1'h0;
+    \8818 [523] = 1'h0;
+    \8818 [524] = 1'h0;
+    \8818 [525] = 1'h0;
+    \8818 [526] = 1'h0;
+    \8818 [527] = 1'h0;
+    \8818 [528] = 1'h0;
+    \8818 [529] = 1'h0;
+    \8818 [530] = 1'h0;
+    \8818 [531] = 1'h0;
+    \8818 [532] = 1'h0;
+    \8818 [533] = 1'h0;
+    \8818 [534] = 1'h0;
+    \8818 [535] = 1'h0;
+    \8818 [536] = 1'h0;
+    \8818 [537] = 1'h0;
+    \8818 [538] = 1'h0;
+    \8818 [539] = 1'h0;
+    \8818 [540] = 1'h0;
+    \8818 [541] = 1'h0;
+    \8818 [542] = 1'h0;
+    \8818 [543] = 1'h0;
+    \8818 [544] = 1'h0;
+    \8818 [545] = 1'h0;
+    \8818 [546] = 1'h0;
+    \8818 [547] = 1'h0;
+    \8818 [548] = 1'h0;
+    \8818 [549] = 1'h0;
+    \8818 [550] = 1'h0;
+    \8818 [551] = 1'h0;
+    \8818 [552] = 1'h0;
+    \8818 [553] = 1'h0;
+    \8818 [554] = 1'h0;
+    \8818 [555] = 1'h0;
+    \8818 [556] = 1'h0;
+    \8818 [557] = 1'h0;
+    \8818 [558] = 1'h0;
+    \8818 [559] = 1'h0;
+    \8818 [560] = 1'h0;
+    \8818 [561] = 1'h0;
+    \8818 [562] = 1'h0;
+    \8818 [563] = 1'h0;
+    \8818 [564] = 1'h0;
+    \8818 [565] = 1'h0;
+    \8818 [566] = 1'h0;
+    \8818 [567] = 1'h0;
+    \8818 [568] = 1'h0;
+    \8818 [569] = 1'h0;
+    \8818 [570] = 1'h0;
+    \8818 [571] = 1'h0;
+    \8818 [572] = 1'h0;
+    \8818 [573] = 1'h0;
+    \8818 [574] = 1'h0;
+    \8818 [575] = 1'h0;
+    \8818 [576] = 1'h0;
+    \8818 [577] = 1'h0;
+    \8818 [578] = 1'h0;
+    \8818 [579] = 1'h0;
+    \8818 [580] = 1'h0;
+    \8818 [581] = 1'h0;
+    \8818 [582] = 1'h0;
+    \8818 [583] = 1'h0;
+    \8818 [584] = 1'h0;
+    \8818 [585] = 1'h0;
+    \8818 [586] = 1'h0;
+    \8818 [587] = 1'h0;
+    \8818 [588] = 1'h0;
+    \8818 [589] = 1'h0;
+    \8818 [590] = 1'h0;
+    \8818 [591] = 1'h0;
+    \8818 [592] = 1'h0;
+    \8818 [593] = 1'h0;
+    \8818 [594] = 1'h0;
+    \8818 [595] = 1'h0;
+    \8818 [596] = 1'h0;
+    \8818 [597] = 1'h0;
+    \8818 [598] = 1'h0;
+    \8818 [599] = 1'h0;
+    \8818 [600] = 1'h0;
+    \8818 [601] = 1'h0;
+    \8818 [602] = 1'h0;
+    \8818 [603] = 1'h0;
+    \8818 [604] = 1'h0;
+    \8818 [605] = 1'h0;
+    \8818 [606] = 1'h0;
+    \8818 [607] = 1'h0;
+    \8818 [608] = 1'h0;
+    \8818 [609] = 1'h0;
+    \8818 [610] = 1'h0;
+    \8818 [611] = 1'h0;
+    \8818 [612] = 1'h0;
+    \8818 [613] = 1'h0;
+    \8818 [614] = 1'h0;
+    \8818 [615] = 1'h0;
+    \8818 [616] = 1'h0;
+    \8818 [617] = 1'h0;
+    \8818 [618] = 1'h0;
+    \8818 [619] = 1'h0;
+    \8818 [620] = 1'h0;
+    \8818 [621] = 1'h0;
+    \8818 [622] = 1'h0;
+    \8818 [623] = 1'h0;
+    \8818 [624] = 1'h0;
+    \8818 [625] = 1'h0;
+    \8818 [626] = 1'h0;
+    \8818 [627] = 1'h0;
+    \8818 [628] = 1'h0;
+    \8818 [629] = 1'h0;
+    \8818 [630] = 1'h0;
+    \8818 [631] = 1'h0;
+    \8818 [632] = 1'h0;
+    \8818 [633] = 1'h0;
+    \8818 [634] = 1'h0;
+    \8818 [635] = 1'h0;
+    \8818 [636] = 1'h0;
+    \8818 [637] = 1'h0;
+    \8818 [638] = 1'h0;
+    \8818 [639] = 1'h0;
+    \8818 [640] = 1'h0;
+    \8818 [641] = 1'h0;
+    \8818 [642] = 1'h0;
+    \8818 [643] = 1'h0;
+    \8818 [644] = 1'h0;
+    \8818 [645] = 1'h0;
+    \8818 [646] = 1'h0;
+    \8818 [647] = 1'h0;
+    \8818 [648] = 1'h0;
+    \8818 [649] = 1'h0;
+    \8818 [650] = 1'h0;
+    \8818 [651] = 1'h0;
+    \8818 [652] = 1'h0;
+    \8818 [653] = 1'h0;
+    \8818 [654] = 1'h0;
+    \8818 [655] = 1'h0;
+    \8818 [656] = 1'h0;
+    \8818 [657] = 1'h0;
+    \8818 [658] = 1'h0;
+    \8818 [659] = 1'h0;
+    \8818 [660] = 1'h0;
+    \8818 [661] = 1'h0;
+    \8818 [662] = 1'h0;
+    \8818 [663] = 1'h0;
+    \8818 [664] = 1'h0;
+    \8818 [665] = 1'h0;
+    \8818 [666] = 1'h0;
+    \8818 [667] = 1'h0;
+    \8818 [668] = 1'h0;
+    \8818 [669] = 1'h0;
+    \8818 [670] = 1'h0;
+    \8818 [671] = 1'h0;
+    \8818 [672] = 1'h0;
+    \8818 [673] = 1'h0;
+    \8818 [674] = 1'h0;
+    \8818 [675] = 1'h0;
+    \8818 [676] = 1'h0;
+    \8818 [677] = 1'h0;
+    \8818 [678] = 1'h0;
+    \8818 [679] = 1'h0;
+    \8818 [680] = 1'h0;
+    \8818 [681] = 1'h0;
+    \8818 [682] = 1'h0;
+    \8818 [683] = 1'h0;
+    \8818 [684] = 1'h0;
+    \8818 [685] = 1'h0;
+    \8818 [686] = 1'h0;
+    \8818 [687] = 1'h0;
+    \8818 [688] = 1'h0;
+    \8818 [689] = 1'h0;
+    \8818 [690] = 1'h0;
+    \8818 [691] = 1'h0;
+    \8818 [692] = 1'h0;
+    \8818 [693] = 1'h0;
+    \8818 [694] = 1'h0;
+    \8818 [695] = 1'h0;
+    \8818 [696] = 1'h0;
+    \8818 [697] = 1'h0;
+    \8818 [698] = 1'h0;
+    \8818 [699] = 1'h0;
+    \8818 [700] = 1'h0;
+    \8818 [701] = 1'h0;
+    \8818 [702] = 1'h0;
+    \8818 [703] = 1'h0;
+    \8818 [704] = 1'h0;
+    \8818 [705] = 1'h0;
+    \8818 [706] = 1'h0;
+    \8818 [707] = 1'h0;
+    \8818 [708] = 1'h0;
+    \8818 [709] = 1'h0;
+    \8818 [710] = 1'h0;
+    \8818 [711] = 1'h0;
+    \8818 [712] = 1'h0;
+    \8818 [713] = 1'h0;
+    \8818 [714] = 1'h0;
+    \8818 [715] = 1'h0;
+    \8818 [716] = 1'h0;
+    \8818 [717] = 1'h0;
+    \8818 [718] = 1'h0;
+    \8818 [719] = 1'h0;
+    \8818 [720] = 1'h0;
+    \8818 [721] = 1'h0;
+    \8818 [722] = 1'h0;
+    \8818 [723] = 1'h0;
+    \8818 [724] = 1'h0;
+    \8818 [725] = 1'h0;
+    \8818 [726] = 1'h0;
+    \8818 [727] = 1'h0;
+    \8818 [728] = 1'h0;
+    \8818 [729] = 1'h0;
+    \8818 [730] = 1'h0;
+    \8818 [731] = 1'h0;
+    \8818 [732] = 1'h0;
+    \8818 [733] = 1'h0;
+    \8818 [734] = 1'h0;
+    \8818 [735] = 1'h0;
+    \8818 [736] = 1'h0;
+    \8818 [737] = 1'h0;
+    \8818 [738] = 1'h0;
+    \8818 [739] = 1'h0;
+    \8818 [740] = 1'h0;
+    \8818 [741] = 1'h0;
+    \8818 [742] = 1'h0;
+    \8818 [743] = 1'h0;
+    \8818 [744] = 1'h0;
+    \8818 [745] = 1'h0;
+    \8818 [746] = 1'h0;
+    \8818 [747] = 1'h0;
+    \8818 [748] = 1'h0;
+    \8818 [749] = 1'h0;
+    \8818 [750] = 1'h0;
+    \8818 [751] = 1'h0;
+    \8818 [752] = 1'h0;
+    \8818 [753] = 1'h0;
+    \8818 [754] = 1'h0;
+    \8818 [755] = 1'h0;
+    \8818 [756] = 1'h0;
+    \8818 [757] = 1'h0;
+    \8818 [758] = 1'h0;
+    \8818 [759] = 1'h0;
+    \8818 [760] = 1'h0;
+    \8818 [761] = 1'h0;
+    \8818 [762] = 1'h0;
+    \8818 [763] = 1'h0;
+    \8818 [764] = 1'h0;
+    \8818 [765] = 1'h0;
+    \8818 [766] = 1'h0;
+    \8818 [767] = 1'h0;
+    \8818 [768] = 1'h0;
+    \8818 [769] = 1'h0;
+    \8818 [770] = 1'h0;
+    \8818 [771] = 1'h0;
+    \8818 [772] = 1'h0;
+    \8818 [773] = 1'h0;
+    \8818 [774] = 1'h0;
+    \8818 [775] = 1'h0;
+    \8818 [776] = 1'h0;
+    \8818 [777] = 1'h0;
+    \8818 [778] = 1'h0;
+    \8818 [779] = 1'h0;
+    \8818 [780] = 1'h0;
+    \8818 [781] = 1'h0;
+    \8818 [782] = 1'h0;
+    \8818 [783] = 1'h0;
+    \8818 [784] = 1'h0;
+    \8818 [785] = 1'h0;
+    \8818 [786] = 1'h0;
+    \8818 [787] = 1'h0;
+    \8818 [788] = 1'h0;
+    \8818 [789] = 1'h0;
+    \8818 [790] = 1'h0;
+    \8818 [791] = 1'h0;
+    \8818 [792] = 1'h0;
+    \8818 [793] = 1'h0;
+    \8818 [794] = 1'h0;
+    \8818 [795] = 1'h0;
+    \8818 [796] = 1'h0;
+    \8818 [797] = 1'h0;
+    \8818 [798] = 1'h0;
+    \8818 [799] = 1'h0;
+    \8818 [800] = 1'h0;
+    \8818 [801] = 1'h0;
+    \8818 [802] = 1'h0;
+    \8818 [803] = 1'h0;
+    \8818 [804] = 1'h0;
+    \8818 [805] = 1'h0;
+    \8818 [806] = 1'h0;
+    \8818 [807] = 1'h0;
+    \8818 [808] = 1'h0;
+    \8818 [809] = 1'h0;
+    \8818 [810] = 1'h0;
+    \8818 [811] = 1'h0;
+    \8818 [812] = 1'h0;
+    \8818 [813] = 1'h0;
+    \8818 [814] = 1'h0;
+    \8818 [815] = 1'h0;
+    \8818 [816] = 1'h0;
+    \8818 [817] = 1'h0;
+    \8818 [818] = 1'h0;
+    \8818 [819] = 1'h0;
+    \8818 [820] = 1'h0;
+    \8818 [821] = 1'h0;
+    \8818 [822] = 1'h0;
+    \8818 [823] = 1'h0;
+    \8818 [824] = 1'h0;
+    \8818 [825] = 1'h0;
+    \8818 [826] = 1'h0;
+    \8818 [827] = 1'h0;
+    \8818 [828] = 1'h0;
+    \8818 [829] = 1'h0;
+    \8818 [830] = 1'h0;
+    \8818 [831] = 1'h0;
+    \8818 [832] = 1'h0;
+    \8818 [833] = 1'h0;
+    \8818 [834] = 1'h0;
+    \8818 [835] = 1'h0;
+    \8818 [836] = 1'h0;
+    \8818 [837] = 1'h0;
+    \8818 [838] = 1'h0;
+    \8818 [839] = 1'h0;
+    \8818 [840] = 1'h0;
+    \8818 [841] = 1'h0;
+    \8818 [842] = 1'h0;
+    \8818 [843] = 1'h0;
+    \8818 [844] = 1'h0;
+    \8818 [845] = 1'h0;
+    \8818 [846] = 1'h0;
+    \8818 [847] = 1'h0;
+    \8818 [848] = 1'h0;
+    \8818 [849] = 1'h0;
+    \8818 [850] = 1'h0;
+    \8818 [851] = 1'h0;
+    \8818 [852] = 1'h0;
+    \8818 [853] = 1'h0;
+    \8818 [854] = 1'h0;
+    \8818 [855] = 1'h0;
+    \8818 [856] = 1'h0;
+    \8818 [857] = 1'h0;
+    \8818 [858] = 1'h0;
+    \8818 [859] = 1'h0;
+    \8818 [860] = 1'h0;
+    \8818 [861] = 1'h0;
+    \8818 [862] = 1'h0;
+    \8818 [863] = 1'h0;
+    \8818 [864] = 1'h0;
+    \8818 [865] = 1'h0;
+    \8818 [866] = 1'h0;
+    \8818 [867] = 1'h0;
+    \8818 [868] = 1'h0;
+    \8818 [869] = 1'h0;
+    \8818 [870] = 1'h0;
+    \8818 [871] = 1'h0;
+    \8818 [872] = 1'h0;
+    \8818 [873] = 1'h0;
+    \8818 [874] = 1'h0;
+    \8818 [875] = 1'h0;
+    \8818 [876] = 1'h0;
+    \8818 [877] = 1'h0;
+    \8818 [878] = 1'h0;
+    \8818 [879] = 1'h0;
+    \8818 [880] = 1'h0;
+    \8818 [881] = 1'h0;
+    \8818 [882] = 1'h0;
+    \8818 [883] = 1'h0;
+    \8818 [884] = 1'h0;
+    \8818 [885] = 1'h0;
+    \8818 [886] = 1'h0;
+    \8818 [887] = 1'h0;
+    \8818 [888] = 1'h0;
+    \8818 [889] = 1'h0;
+    \8818 [890] = 1'h0;
+    \8818 [891] = 1'h0;
+    \8818 [892] = 1'h0;
+    \8818 [893] = 1'h0;
+    \8818 [894] = 1'h0;
+    \8818 [895] = 1'h0;
+    \8818 [896] = 1'h0;
+    \8818 [897] = 1'h0;
+    \8818 [898] = 1'h0;
+    \8818 [899] = 1'h0;
+    \8818 [900] = 1'h0;
+    \8818 [901] = 1'h0;
+    \8818 [902] = 1'h0;
+    \8818 [903] = 1'h0;
+    \8818 [904] = 1'h0;
+    \8818 [905] = 1'h0;
+    \8818 [906] = 1'h0;
+    \8818 [907] = 1'h0;
+    \8818 [908] = 1'h0;
+    \8818 [909] = 1'h0;
+    \8818 [910] = 1'h0;
+    \8818 [911] = 1'h0;
+    \8818 [912] = 1'h0;
+    \8818 [913] = 1'h0;
+    \8818 [914] = 1'h0;
+    \8818 [915] = 1'h0;
+    \8818 [916] = 1'h0;
+    \8818 [917] = 1'h0;
+    \8818 [918] = 1'h0;
+    \8818 [919] = 1'h0;
+    \8818 [920] = 1'h0;
+    \8818 [921] = 1'h0;
+    \8818 [922] = 1'h0;
+    \8818 [923] = 1'h0;
+    \8818 [924] = 1'h0;
+    \8818 [925] = 1'h0;
+    \8818 [926] = 1'h0;
+    \8818 [927] = 1'h0;
+    \8818 [928] = 1'h1;
+    \8818 [929] = 1'h1;
+    \8818 [930] = 1'h1;
+    \8818 [931] = 1'h1;
+    \8818 [932] = 1'h1;
+    \8818 [933] = 1'h1;
+    \8818 [934] = 1'h1;
+    \8818 [935] = 1'h1;
+    \8818 [936] = 1'h1;
+    \8818 [937] = 1'h1;
+    \8818 [938] = 1'h1;
+    \8818 [939] = 1'h1;
+    \8818 [940] = 1'h1;
+    \8818 [941] = 1'h1;
+    \8818 [942] = 1'h1;
+    \8818 [943] = 1'h1;
+    \8818 [944] = 1'h1;
+    \8818 [945] = 1'h1;
+    \8818 [946] = 1'h1;
+    \8818 [947] = 1'h1;
+    \8818 [948] = 1'h1;
+    \8818 [949] = 1'h1;
+    \8818 [950] = 1'h1;
+    \8818 [951] = 1'h1;
+    \8818 [952] = 1'h1;
+    \8818 [953] = 1'h1;
+    \8818 [954] = 1'h1;
+    \8818 [955] = 1'h1;
+    \8818 [956] = 1'h1;
+    \8818 [957] = 1'h1;
+    \8818 [958] = 1'h1;
+    \8818 [959] = 1'h1;
+    \8818 [960] = 1'h0;
+    \8818 [961] = 1'h0;
+    \8818 [962] = 1'h0;
+    \8818 [963] = 1'h0;
+    \8818 [964] = 1'h0;
+    \8818 [965] = 1'h0;
+    \8818 [966] = 1'h0;
+    \8818 [967] = 1'h0;
+    \8818 [968] = 1'h0;
+    \8818 [969] = 1'h0;
+    \8818 [970] = 1'h0;
+    \8818 [971] = 1'h0;
+    \8818 [972] = 1'h0;
+    \8818 [973] = 1'h0;
+    \8818 [974] = 1'h0;
+    \8818 [975] = 1'h0;
+    \8818 [976] = 1'h0;
+    \8818 [977] = 1'h1;
+    \8818 [978] = 1'h1;
+    \8818 [979] = 1'h0;
+    \8818 [980] = 1'h0;
+    \8818 [981] = 1'h0;
+    \8818 [982] = 1'h1;
+    \8818 [983] = 1'h1;
+    \8818 [984] = 1'h1;
+    \8818 [985] = 1'h1;
+    \8818 [986] = 1'h0;
+    \8818 [987] = 1'h1;
+    \8818 [988] = 1'h0;
+    \8818 [989] = 1'h0;
+    \8818 [990] = 1'h1;
+    \8818 [991] = 1'h0;
+    \8818 [992] = 1'h0;
+    \8818 [993] = 1'h0;
+    \8818 [994] = 1'h0;
+    \8818 [995] = 1'h0;
+    \8818 [996] = 1'h0;
+    \8818 [997] = 1'h0;
+    \8818 [998] = 1'h0;
+    \8818 [999] = 1'h0;
+    \8818 [1000] = 1'h0;
+    \8818 [1001] = 1'h0;
+    \8818 [1002] = 1'h0;
+    \8818 [1003] = 1'h0;
+    \8818 [1004] = 1'h0;
+    \8818 [1005] = 1'h0;
+    \8818 [1006] = 1'h0;
+    \8818 [1007] = 1'h0;
+    \8818 [1008] = 1'h0;
+    \8818 [1009] = 1'h0;
+    \8818 [1010] = 1'h0;
+    \8818 [1011] = 1'h0;
+    \8818 [1012] = 1'h0;
+    \8818 [1013] = 1'h0;
+    \8818 [1014] = 1'h0;
+    \8818 [1015] = 1'h0;
+    \8818 [1016] = 1'h0;
+    \8818 [1017] = 1'h0;
+    \8818 [1018] = 1'h0;
+    \8818 [1019] = 1'h0;
+    \8818 [1020] = 1'h0;
+    \8818 [1021] = 1'h0;
+    \8818 [1022] = 1'h0;
+    \8818 [1023] = 1'h1;
+  end
+  assign _133_ = \8818 [_074_];
+  reg [40:0] \8820  [7:0];
+  initial begin
+    \8820 [0] = 41'h10000000079;
+    \8820 [1] = 41'h00000000000;
+    \8820 [2] = 41'h00000006bc5;
+    \8820 [3] = 41'h080002c6b1d;
+    \8820 [4] = 41'h00000000000;
+    \8820 [5] = 41'h00000000000;
+    \8820 [6] = 41'h04000044409;
+    \8820 [7] = 41'h00000600039;
+  end
+  assign _135_ = \8820 [_076_];
+  reg [40:0] \8822  [15:0];
+  initial begin
+    \8822 [0] = 41'h00000000000;
+    \8822 [1] = 41'h00000000000;
+    \8822 [2] = 41'h00000000000;
+    \8822 [3] = 41'h00000000000;
+    \8822 [4] = 41'h00000000000;
+    \8822 [5] = 41'h00000000000;
+    \8822 [6] = 41'h040000888d1;
+    \8822 [7] = 41'h040000888cd;
+    \8822 [8] = 41'h0400008d9c9;
+    \8822 [9] = 41'h0400008d9c9;
+    \8822 [10] = 41'h0400008d8c9;
+    \8822 [11] = 41'h0400008d8c9;
+    \8822 [12] = 41'h0400008d8d1;
+    \8822 [13] = 41'h0400008d8d1;
+    \8822 [14] = 41'h0400008d8cd;
+    \8822 [15] = 41'h0400008d8cd;
+  end
+  assign _137_ = \8822 [_086_];
+  reg [40:0] \8824  [3:0];
+  initial begin
+    \8824 [0] = 41'h00000000000;
+    \8824 [1] = 41'h00130044a7e;
+    \8824 [2] = 41'h00240044a7e;
+    \8824 [3] = 41'h00040044a7e;
+  end
+  assign _139_ = \8824 [_092_];
+  reg [40:0] \8826  [3:0];
+  initial begin
+    \8826 [0] = 41'h00000000000;
+    \8826 [1] = 41'h00000000000;
+    \8826 [2] = 41'h0024000ca82;
+    \8826 [3] = 41'h0004000ca82;
+  end
+  assign _141_ = \8826 [_095_];
+  assign _000_ = ~ stall_in;
+  assign _001_ = _000_ ? s : r;
+  assign _002_ = _000_ ? 1'h0 : s[0];
+  assign _003_ = _000_ ? si : ri;
+  assign _004_ = _110_ & r[0];
+  assign _005_ = _004_ & stall_in;
+  assign _006_ = ~ r[0];
+  assign _007_ = ~ stall_in;
+  assign _008_ = _006_ | _007_;
+  assign _009_ = _008_ ? { _101_, _100_, _099_, _098_, f_in[98:3], f_in[1], _110_ } : r;
+  assign _010_ = _008_ ? { _105_, _111_ } : ri;
+  assign _011_ = s[0] ? _001_ : _009_;
+  assign _012_ = s[0] ? _002_ : _005_;
+  assign _013_ = s[0] ? s[153:1] : { _101_, _100_, _099_, _098_, f_in[98:3], f_in[1] };
+  assign _014_ = s[0] ? _003_ : _010_;
+  assign _015_ = s[0] ? si : { _105_, _111_ };
+  assign _016_ = flush_in ? 1'h0 : _011_[0];
+  assign _017_ = flush_in ? r[153:1] : _011_[153:1];
+  assign _018_ = flush_in ? 1'h0 : _012_;
+  assign _019_ = flush_in ? s[153:1] : _013_;
+  assign _020_ = flush_in ? ri : _014_;
+  assign _021_ = flush_in ? si : _015_;
+  assign _022_ = rst ? 154'h000000000000000000000000000000000000000 : { _017_, _016_ };
+  assign _023_ = rst ? 154'h000000000000000000000000000000000000000 : { _019_, _018_ };
+  assign _024_ = rst ? 44'h00000000000 : _020_;
+  assign _025_ = rst ? 44'h00000000000 : _021_;
+  always @(posedge clk)
+    r <= _022_;
+  always @(posedge clk)
+    s <= _023_;
+  always @(posedge clk)
+    ri <= _024_;
+  always @(posedge clk)
+    si <= _025_;
+  assign _026_ = 6'h3f - f_in[98:93];
+  assign _027_ = 11'h7ff - { f_in[72:67], f_in[77:73] };
+  assign _028_ = ~ _127_;
+  assign _029_ = 6'h3f - f_in[72:67];
+  assign _030_ = { 25'h0000000, f_in[98:93] } == 31'h00000004;
+  assign _031_ = 10'h3ff - f_in[77:68];
+  assign _032_ = { f_in[82:78], f_in[87:83] } == 10'h008;
+  assign _033_ = { f_in[82:78], f_in[87:83] } == 10'h009;
+  assign _034_ = { f_in[82:78], f_in[87:83] } == 10'h01a;
+  assign _035_ = { f_in[82:78], f_in[87:83] } == 10'h01b;
+  assign _036_ = { f_in[82:78], f_in[87:83] } == 10'h13a;
+  assign _037_ = { f_in[82:78], f_in[87:83] } == 10'h13b;
+  assign _038_ = { f_in[82:78], f_in[87:83] } == 10'h110;
+  assign _039_ = { f_in[82:78], f_in[87:83] } == 10'h111;
+  assign _040_ = { f_in[82:78], f_in[87:83] } == 10'h112;
+  assign _041_ = { f_in[82:78], f_in[87:83] } == 10'h113;
+  assign _042_ = { f_in[82:78], f_in[87:83] } == 10'h103;
+  assign _043_ = _041_ | _042_;
+  assign _044_ = { f_in[82:78], f_in[87:83] } == 10'h130;
+  assign _045_ = { f_in[82:78], f_in[87:83] } == 10'h131;
+  assign _046_ = { f_in[82:78], f_in[87:83] } == 10'h001;
+  assign _047_ = { f_in[82:78], f_in[87:83] } == 10'h32f;
+  function [0:0] \8524 ;
+    input [0:0] a;
+    input [13:0] b;
+    input [13:0] s;
+    (* parallel_case *)
+    casez (s)
+      14'b?????????????1:
+        \8524  = b[0:0];
+      14'b????????????1?:
+        \8524  = b[1:1];
+      14'b???????????1??:
+        \8524  = b[2:2];
+      14'b??????????1???:
+        \8524  = b[3:3];
+      14'b?????????1????:
+        \8524  = b[4:4];
+      14'b????????1?????:
+        \8524  = b[5:5];
+      14'b???????1??????:
+        \8524  = b[6:6];
+      14'b??????1???????:
+        \8524  = b[7:7];
+      14'b?????1????????:
+        \8524  = b[8:8];
+      14'b????1?????????:
+        \8524  = b[9:9];
+      14'b???1??????????:
+        \8524  = b[10:10];
+      14'b??1???????????:
+        \8524  = b[11:11];
+      14'b?1????????????:
+        \8524  = b[12:12];
+      14'b1?????????????:
+        \8524  = b[13:13];
+      default:
+        \8524  = a;
+    endcase
+  endfunction
+  assign _048_ = \8524 (1'h0, 14'h3fff, { _047_, _046_, _045_, _044_, _043_, _040_, _039_, _038_, _037_, _036_, _035_, _034_, _033_, _032_ });
+  function [6:0] \8530 ;
+    input [6:0] a;
+    input [97:0] b;
+    input [13:0] s;
+    (* parallel_case *)
+    casez (s)
+      14'b?????????????1:
+        \8530  = b[6:0];
+      14'b????????????1?:
+        \8530  = b[13:7];
+      14'b???????????1??:
+        \8530  = b[20:14];
+      14'b??????????1???:
+        \8530  = b[27:21];
+      14'b?????????1????:
+        \8530  = b[34:28];
+      14'b????????1?????:
+        \8530  = b[41:35];
+      14'b???????1??????:
+        \8530  = b[48:42];
+      14'b??????1???????:
+        \8530  = b[55:49];
+      14'b?????1????????:
+        \8530  = b[62:56];
+      14'b????1?????????:
+        \8530  = b[69:63];
+      14'b???1??????????:
+        \8530  = b[76:70];
+      14'b??1???????????:
+        \8530  = b[83:77];
+      14'b?1????????????:
+        \8530  = b[90:84];
+      14'b1?????????????:
+        \8530  = b[97:91];
+      default:
+        \8530  = a;
+    endcase
+  endfunction
+  assign _049_ = \8530 (7'h00, 98'hxxxxxxxxxxxxxxxxxxxxxxxxx, { _047_, _046_, _045_, _044_, _043_, _040_, _039_, _038_, _037_, _036_, _035_, _034_, _033_, _032_ });
+  function [4:0] \8546 ;
+    input [4:0] a;
+    input [69:0] b;
+    input [13:0] s;
+    (* parallel_case *)
+    casez (s)
+      14'b?????????????1:
+        \8546  = b[4:0];
+      14'b????????????1?:
+        \8546  = b[9:5];
+      14'b???????????1??:
+        \8546  = b[14:10];
+      14'b??????????1???:
+        \8546  = b[19:15];
+      14'b?????????1????:
+        \8546  = b[24:20];
+      14'b????????1?????:
+        \8546  = b[29:25];
+      14'b???????1??????:
+        \8546  = b[34:30];
+      14'b??????1???????:
+        \8546  = b[39:35];
+      14'b?????1????????:
+        \8546  = b[44:40];
+      14'b????1?????????:
+        \8546  = b[49:45];
+      14'b???1??????????:
+        \8546  = b[54:50];
+      14'b??1???????????:
+        \8546  = b[59:55];
+      14'b?1????????????:
+        \8546  = b[64:60];
+      14'b1?????????????:
+        \8546  = b[69:65];
+      default:
+        \8546  = a;
+    endcase
+  endfunction
+  assign _050_ = \8546 (5'h00, 70'h1ac5a928398a418820, { _047_, _046_, _045_, _044_, _043_, _040_, _039_, _038_, _037_, _036_, _035_, _034_, _033_, _032_ });
+  assign _051_ = _048_ ? _050_ : 5'hxx;
+  assign _052_ = _048_ ? { 2'h1, _051_ } : _049_;
+  assign _053_ = f_in[77:68] & 10'h37f;
+  assign _054_ = _053_ == 10'h153;
+  assign _055_ = ~ _052_[5];
+  assign _056_ = { f_in[82:78], f_in[87:83] } == 10'h013;
+  assign _057_ = { f_in[82:78], f_in[87:83] } == 10'h012;
+  assign _058_ = _056_ | _057_;
+  assign _059_ = { f_in[82:78], f_in[87:83] } == 10'h030;
+  assign _060_ = _058_ | _059_;
+  assign _061_ = { f_in[82:78], f_in[87:83] } == 10'h2d0;
+  assign _062_ = _060_ | _061_;
+  function [1:0] \8589 ;
+    input [1:0] a;
+    input [1:0] b;
+    input [0:0] s;
+    (* parallel_case *)
+    casez (s)
+      1'b1:
+        \8589  = b[1:0];
+      default:
+        \8589  = a;
+    endcase
+  endfunction
+  assign _063_ = \8589 (2'h0, 2'h2, _062_);
+  function [0:0] \8591 ;
+    input [0:0] a;
+    input [0:0] b;
+    input [0:0] s;
+    (* parallel_case *)
+    casez (s)
+      1'b1:
+        \8591  = b[0:0];
+      default:
+        \8591  = a;
+    endcase
+  endfunction
+  assign _064_ = \8591 (1'h0, 1'h1, _062_);
+  assign _065_ = _055_ ? _063_ : 2'h0;
+  assign _066_ = _055_ ? { 1'h1, _064_ } : 2'h0;
+  assign _067_ = _054_ ? _065_ : 2'h0;
+  assign _068_ = _054_ ? _066_ : 2'h0;
+  assign _069_ = { 25'h0000000, f_in[98:93] } == 31'h0000001f;
+  assign _070_ = ~ f_in[90];
+  assign _071_ = _070_ ? 7'h21 : 7'h00;
+  assign _072_ = { 25'h0000000, f_in[98:93] } == 31'h00000010;
+  assign _073_ = { 25'h0000000, f_in[98:93] } == 31'h00000012;
+  assign _074_ = 10'h3ff - { f_in[72:68], f_in[77:73] };
+  assign _075_ = ~ _133_;
+  assign _076_ = 3'h7 - { f_in[72], f_in[70:69] };
+  assign _077_ = ~ f_in[69];
+  assign _078_ = ~ f_in[90];
+  assign _079_ = _078_ ? 7'h21 : 7'h00;
+  assign _080_ = ~ f_in[77];
+  assign _081_ = ~ f_in[73];
+  assign _082_ = _081_ ? 7'h21 : 7'h2d;
+  assign _083_ = _080_ ? 7'h20 : _082_;
+  assign _084_ = _077_ ? { _083_, _079_ } : 14'h1123;
+  assign _085_ = { 25'h0000000, f_in[98:93] } == 31'h00000013;
+  assign _086_ = 4'hf - f_in[71:68];
+  assign _087_ = { 25'h0000000, f_in[98:93] } == 31'h0000001e;
+  assign _088_ = f_in[98:67] & 32'd4294967295;
+  assign _089_ = _088_ == 32'd1610612736;
+  assign _090_ = _089_ ? 42'h0000000000b : 42'h00000000000;
+  assign _091_ = { 25'h0000000, f_in[98:93] } == 31'h00000030;
+  assign _092_ = 2'h3 - f_in[68:67];
+  assign _093_ = { 25'h0000000, f_in[98:93] } == 31'h0000003a;
+  assign _094_ = { 25'h0000000, f_in[98:93] } == 31'h0000003b;
+  assign _095_ = 2'h3 - f_in[68:67];
+  assign _096_ = { 25'h0000000, f_in[98:93] } == 31'h0000003e;
+  assign _097_ = { 25'h0000000, f_in[98:93] } == 31'h0000003f;
+  function [6:0] \8714 ;
+    input [6:0] a;
+    input [76:0] b;
+    input [10:0] s;
+    (* parallel_case *)
+    casez (s)
+      11'b??????????1:
+        \8714  = b[6:0];
+      11'b?????????1?:
+        \8714  = b[13:7];
+      11'b????????1??:
+        \8714  = b[20:14];
+      11'b???????1???:
+        \8714  = b[27:21];
+      11'b??????1????:
+        \8714  = b[34:28];
+      11'b?????1?????:
+        \8714  = b[41:35];
+      11'b????1??????:
+        \8714  = b[48:42];
+      11'b???1???????:
+        \8714  = b[55:49];
+      11'b??1????????:
+        \8714  = b[62:56];
+      11'b?1?????????:
+        \8714  = b[69:63];
+      11'b1??????????:
+        \8714  = b[76:70];
+      default:
+        \8714  = a;
+    endcase
+  endfunction
+  assign _098_ = \8714 (7'h00, { 42'h00000000000, _084_[6:0], 7'h00, _071_, _052_, 7'h00 }, { _097_, _096_, _094_, _093_, _091_, _087_, _085_, _073_, _072_, _069_, _030_ });
+  function [6:0] \8717 ;
+    input [6:0] a;
+    input [76:0] b;
+    input [10:0] s;
+    (* parallel_case *)
+    casez (s)
+      11'b??????????1:
+        \8717  = b[6:0];
+      11'b?????????1?:
+        \8717  = b[13:7];
+      11'b????????1??:
+        \8717  = b[20:14];
+      11'b???????1???:
+        \8717  = b[27:21];
+      11'b??????1????:
+        \8717  = b[34:28];
+      11'b?????1?????:
+        \8717  = b[41:35];
+      11'b????1??????:
+        \8717  = b[48:42];
+      11'b???1???????:
+        \8717  = b[55:49];
+      11'b??1????????:
+        \8717  = b[62:56];
+      11'b?1?????????:
+        \8717  = b[69:63];
+      11'b1??????????:
+        \8717  = b[76:70];
+      default:
+        \8717  = a;
+    endcase
+  endfunction
+  assign _099_ = \8717 (7'h00, { 42'h00000000000, _084_[13:7], 28'h0000000 }, { _097_, _096_, _094_, _093_, _091_, _087_, _085_, _073_, _072_, _069_, _030_ });
+  function [40:0] \8718 ;
+    input [40:0] a;
+    input [450:0] b;
+    input [10:0] s;
+    (* parallel_case *)
+    casez (s)
+      11'b??????????1:
+        \8718  = b[40:0];
+      11'b?????????1?:
+        \8718  = b[81:41];
+      11'b????????1??:
+        \8718  = b[122:82];
+      11'b???????1???:
+        \8718  = b[163:123];
+      11'b??????1????:
+        \8718  = b[204:164];
+      11'b?????1?????:
+        \8718  = b[245:205];
+      11'b????1??????:
+        \8718  = b[286:246];
+      11'b???1???????:
+        \8718  = b[327:287];
+      11'b??1????????:
+        \8718  = b[368:328];
+      11'b?1?????????:
+        \8718  = b[409:369];
+      11'b1??????????:
+        \8718  = b[450:410];
+      default:
+        \8718  = a;
+    endcase
+  endfunction
+  assign _100_ = \8718 (_125_, { _125_, _141_, _125_, _139_, _125_, _137_, _135_, _125_, _125_, _131_, _129_ }, { _097_, _096_, _094_, _093_, _091_, _087_, _085_, _073_, _072_, _069_, _030_ });
+  function [0:0] \8719 ;
+    input [0:0] a;
+    input [10:0] b;
+    input [10:0] s;
+    (* parallel_case *)
+    casez (s)
+      11'b??????????1:
+        \8719  = b[0:0];
+      11'b?????????1?:
+        \8719  = b[1:1];
+      11'b????????1??:
+        \8719  = b[2:2];
+      11'b???????1???:
+        \8719  = b[3:3];
+      11'b??????1????:
+        \8719  = b[4:4];
+      11'b?????1?????:
+        \8719  = b[5:5];
+      11'b????1??????:
+        \8719  = b[6:6];
+      11'b???1???????:
+        \8719  = b[7:7];
+      11'b??1????????:
+        \8719  = b[8:8];
+      11'b?1?????????:
+        \8719  = b[9:9];
+      11'b1??????????:
+        \8719  = b[10:10];
+      default:
+        \8719  = a;
+    endcase
+  endfunction
+  assign _101_ = \8719 (1'h0, { 8'h01, f_in[82], 2'h0 }, { _097_, _096_, _094_, _093_, _091_, _087_, _085_, _073_, _072_, _069_, _030_ });
+  function [0:0] \8723 ;
+    input [0:0] a;
+    input [10:0] b;
+    input [10:0] s;
+    (* parallel_case *)
+    casez (s)
+      11'b??????????1:
+        \8723  = b[0:0];
+      11'b?????????1?:
+        \8723  = b[1:1];
+      11'b????????1??:
+        \8723  = b[2:2];
+      11'b???????1???:
+        \8723  = b[3:3];
+      11'b??????1????:
+        \8723  = b[4:4];
+      11'b?????1?????:
+        \8723  = b[5:5];
+      11'b????1??????:
+        \8723  = b[6:6];
+      11'b???1???????:
+        \8723  = b[7:7];
+      11'b??1????????:
+        \8723  = b[8:8];
+      11'b?1?????????:
+        \8723  = b[9:9];
+      11'b1??????????:
+        \8723  = b[10:10];
+      default:
+        \8723  = a;
+    endcase
+  endfunction
+  assign _102_ = \8723 (1'h0, { 4'h0, _090_[0], 1'h0, _075_, 3'h0, _028_ }, { _097_, _096_, _094_, _093_, _091_, _087_, _085_, _073_, _072_, _069_, _030_ });
+  function [1:0] \8726 ;
+    input [1:0] a;
+    input [21:0] b;
+    input [10:0] s;
+    (* parallel_case *)
+    casez (s)
+      11'b??????????1:
+        \8726  = b[1:0];
+      11'b?????????1?:
+        \8726  = b[3:2];
+      11'b????????1??:
+        \8726  = b[5:4];
+      11'b???????1???:
+        \8726  = b[7:6];
+      11'b??????1????:
+        \8726  = b[9:8];
+      11'b?????1?????:
+        \8726  = b[11:10];
+      11'b????1??????:
+        \8726  = b[13:12];
+      11'b???1???????:
+        \8726  = b[15:14];
+      11'b??1????????:
+        \8726  = b[17:16];
+      11'b?1?????????:
+        \8726  = b[19:18];
+      11'b1??????????:
+        \8726  = b[21:20];
+      default:
+        \8726  = a;
+    endcase
+  endfunction
+  assign _103_ = \8726 (2'h0, { 8'h00, _090_[2:1], 8'h00, _067_, 2'h0 }, { _097_, _096_, _094_, _093_, _091_, _087_, _085_, _073_, _072_, _069_, _030_ });
+  function [38:0] \8729 ;
+    input [38:0] a;
+    input [428:0] b;
+    input [10:0] s;
+    (* parallel_case *)
+    casez (s)
+      11'b??????????1:
+        \8729  = b[38:0];
+      11'b?????????1?:
+        \8729  = b[77:39];
+      11'b????????1??:
+        \8729  = b[116:78];
+      11'b???????1???:
+        \8729  = b[155:117];
+      11'b??????1????:
+        \8729  = b[194:156];
+      11'b?????1?????:
+        \8729  = b[233:195];
+      11'b????1??????:
+        \8729  = b[272:234];
+      11'b???1???????:
+        \8729  = b[311:273];
+      11'b??1????????:
+        \8729  = b[350:312];
+      11'b?1?????????:
+        \8729  = b[389:351];
+      11'b1??????????:
+        \8729  = b[428:390];
+      default:
+        \8729  = a;
+    endcase
+  endfunction
+  assign _104_ = \8729 (39'h0000000000, { 156'h000000000000000000000000000000000000000, _090_[41:3], 234'h00000000000000000000000000000000000000000000000000000000000 }, { _097_, _096_, _094_, _093_, _091_, _087_, _085_, _073_, _072_, _069_, _030_ });
+  function [1:0] \8731 ;
+    input [1:0] a;
+    input [21:0] b;
+    input [10:0] s;
+    (* parallel_case *)
+    casez (s)
+      11'b??????????1:
+        \8731  = b[1:0];
+      11'b?????????1?:
+        \8731  = b[3:2];
+      11'b????????1??:
+        \8731  = b[5:4];
+      11'b???????1???:
+        \8731  = b[7:6];
+      11'b??????1????:
+        \8731  = b[9:8];
+      11'b?????1?????:
+        \8731  = b[11:10];
+      11'b????1??????:
+        \8731  = b[13:12];
+      11'b???1???????:
+        \8731  = b[15:14];
+      11'b??1????????:
+        \8731  = b[17:16];
+      11'b?1?????????:
+        \8731  = b[19:18];
+      11'b1??????????:
+        \8731  = b[21:20];
+      default:
+        \8731  = a;
+    endcase
+  endfunction
+  assign _105_ = \8731 (2'h0, { 18'h00000, _068_, 2'h0 }, { _097_, _096_, _094_, _093_, _091_, _087_, _085_, _073_, _072_, _069_, _030_ });
+  function [23:0] \8740 ;
+    input [23:0] a;
+    input [263:0] b;
+    input [10:0] s;
+    (* parallel_case *)
+    casez (s)
+      11'b??????????1:
+        \8740  = b[23:0];
+      11'b?????????1?:
+        \8740  = b[47:24];
+      11'b????????1??:
+        \8740  = b[71:48];
+      11'b???????1???:
+        \8740  = b[95:72];
+      11'b??????1????:
+        \8740  = b[119:96];
+      11'b?????1?????:
+        \8740  = b[143:120];
+      11'b????1??????:
+        \8740  = b[167:144];
+      11'b???1???????:
+        \8740  = b[191:168];
+      11'b??1????????:
+        \8740  = b[215:192];
+      11'b?1?????????:
+        \8740  = b[239:216];
+      11'b1??????????:
+        \8740  = b[263:240];
+      default:
+        \8740  = a;
+    endcase
+  endfunction
+  assign _106_ = \8740 (24'h000000, { 168'h000000000000000000000000000000000000000000, f_in[92:69], f_in[82], f_in[82], f_in[82], f_in[82], f_in[82], f_in[82], f_in[82], f_in[82], f_in[82], f_in[82], f_in[82:69], 48'h000000000000 }, { _097_, _096_, _094_, _093_, _091_, _087_, _085_, _073_, _072_, _069_, _030_ });
+  assign _107_ = ri[8:3] == 6'h3f;
+  assign _108_ = ri[0] & _107_;
+  assign _109_ = _108_ ? 1'h0 : 1'h1;
+  assign _110_ = f_in[2] ? _109_ : f_in[0];
+  assign _111_ = f_in[2] ? 42'h000000001fd : { _104_, _103_, _102_ };
+  assign _112_ = f_in[68] ? 62'h0000000000000000 : f_in[66:5];
+  assign _113_ = _112_ + { _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_[23], _106_ };
+  assign _114_ = _101_ & f_in[0];
+  assign _115_ = ~ flush_in;
+  assign _116_ = _114_ & _115_;
+  assign _117_ = ~ s[0];
+  assign _118_ = _116_ & _117_;
+  assign _119_ = ri[42] ? ri[2:1] : r[113:112];
+  assign _120_ = ri[0] ? ri[2:1] : _119_;
+  assign _121_ = ri[0] ? ri[41] : r[152];
+  assign _122_ = ri[43] ? 1'h1 : _121_;
+  assign _123_ = ri[0] ? ri[40:3] : r[151:114];
+  assign busy_out = s[0];
+  assign flush_out = _118_;
+  assign f_out = { _113_, 2'h0, _118_ };
+  assign d_out = { r[153], _122_, _123_, _120_, r[111:0] };
+  assign log_out = 13'hzzzz;
+endmodule
+
+module decode2_0_0e356ba505631fbf715758bed27d503f8b260e3a(clk, rst, complete_in, busy_in, flush_in, d_in, r_in, c_in, stall_out, stopped_out, e_out, r_out, c_out, log_out);
+  wire _00_;
+  wire _01_;
+  wire _02_;
+  wire _03_;
+  wire _04_;
+  wire [379:0] _05_;
+  wire _06_;
+  wire [6:0] _07_;
+  wire _08_;
+  wire _09_;
+  wire [6:0] _10_;
+  wire _11_;
+  wire [6:0] _12_;
+  wire _13_;
+  wire _14_;
+  wire [6:0] _15_;
+  wire _16_;
+  wire [6:0] _17_;
+  wire _18_;
+  wire _19_;
+  wire [6:0] _20_;
+  wire _21_;
+  wire _22_;
+  wire [6:0] _23_;
+  wire _24_;
+  wire _25_;
+  wire _26_;
+  wire _27_;
+  wire _28_;
+  wire _29_;
+  wire _30_;
+  wire [71:0] _31_;
+  wire [71:0] _32_;
+  wire [71:0] _33_;
+  wire _34_;
+  wire _35_;
+  wire _36_;
+  wire _37_;
+  wire _38_;
+  wire _39_;
+  wire _40_;
+  wire _41_;
+  wire _42_;
+  wire _43_;
+  wire _44_;
+  wire _45_;
+  wire _46_;
+  wire _47_;
+  wire _48_;
+  wire [71:0] _49_;
+  wire _50_;
+  wire _51_;
+  wire _52_;
+  wire _53_;
+  wire _54_;
+  wire [71:0] _55_;
+  wire _56_;
+  wire _57_;
+  wire _58_;
+  wire _59_;
+  wire _60_;
+  wire [7:0] _61_;
+  wire _62_;
+  wire _63_;
+  wire _64_;
+  wire _65_;
+  wire _66_;
+  wire _67_;
+  wire _68_;
+  wire _69_;
+  wire [3:0] _70_;
+  wire _71_;
+  wire _72_;
+  wire _73_;
+  wire _74_;
+  wire _75_;
+  wire _76_;
+  wire _77_;
+  wire _78_;
+  wire _79_;
+  wire _80_;
+  wire _81_;
+  wire _82_;
+  wire _83_;
+  wire _84_;
+  wire _85_;
+  wire _86_;
+  wire _87_;
+  wire _88_;
+  wire _89_;
+  wire _90_;
+  wire _91_;
+  input busy_in;
+  input [36:0] c_in;
+  output c_out;
+  input clk;
+  input complete_in;
+  wire control_valid_out;
+  wire cr_bypass;
+  wire cr_bypass_avail;
+  wire cr_write_valid;
+  input [153:0] d_in;
+  wire deferred;
+  output [379:0] e_out;
+  input flush_in;
+  wire gpr_a_bypass;
+  wire gpr_b_bypass;
+  wire gpr_bypassable;
+  wire gpr_c_bypass;
+  output [9:0] log_out;
+  reg [379:0] r;
+  input [191:0] r_in;
+  output [23:0] r_out;
+  wire [379:0] rin;
+  input rst;
+  output stall_out;
+  output stopped_out;
+  wire [6:0] update_gpr_write_reg;
+  wire update_gpr_write_valid;
+  assign deferred = r[0] & busy_in;
+  assign _02_ = rst | flush_in;
+  assign _03_ = ~ deferred;
+  assign _04_ = _02_ | _03_;
+  assign _05_ = _04_ ? rin : r;
+  always @(posedge clk)
+    r <= _05_;
+  assign _06_ = d_in[122:120] == 3'h3;
+  assign _07_ = _06_ ? d_in[104:98] : _10_;
+  assign _08_ = d_in[122:120] == 3'h5;
+  assign _09_ = _08_ & 1'h0;
+  assign _10_ = _09_ ? { 2'h2, d_in[86:82] } : { 2'h0, d_in[86:82] };
+  assign _11_ = d_in[126:123] == 4'hd;
+  assign _12_ = _11_ ? d_in[111:105] : _15_;
+  assign _13_ = d_in[126:123] == 4'he;
+  assign _14_ = _13_ & 1'h0;
+  assign _15_ = _14_ ? { 2'h2, d_in[81:77] } : { 2'h0, d_in[81:77] };
+  assign _16_ = d_in[129:127] == 3'h2;
+  assign _17_ = _16_ ? { 2'h0, d_in[76:72] } : _20_;
+  assign _18_ = d_in[129:127] == 3'h3;
+  assign _19_ = _18_ & 1'h0;
+  assign _20_ = _19_ ? { 2'h2, d_in[76:72] } : _23_;
+  assign _21_ = d_in[129:127] == 3'h4;
+  assign _22_ = _21_ & 1'h0;
+  assign _23_ = _22_ ? { 2'h2, d_in[91:87] } : { 2'h0, d_in[91:87] };
+  assign _24_ = d_in[122:120] == 3'h1;
+  assign _25_ = d_in[122:120] == 3'h2;
+  assign _26_ = d_in[86:82] != 5'h00;
+  assign _27_ = _25_ & _26_;
+  assign _28_ = _24_ | _27_;
+  assign _29_ = d_in[122:120] == 3'h3;
+  assign _30_ = d_in[122:120] == 3'h4;
+  assign _31_ = _30_ ? { d_in[65:2], 8'h00 } : 72'h000000000000000000;
+  assign _32_ = _29_ ? { r_in[63:0], d_in[104:98], d_in[103] } : _31_;
+  assign _33_ = _28_ ? { r_in[63:0], 2'h0, d_in[86:82], 1'h1 } : _32_;
+  assign _34_ = d_in[126:123] == 4'h1;
+  assign _35_ = d_in[126:123] == 4'he;
+  assign _36_ = d_in[126:123] == 4'h2;
+  assign _37_ = d_in[126:123] == 4'h3;
+  assign _38_ = d_in[126:123] == 4'h4;
+  assign _39_ = d_in[126:123] == 4'h5;
+  assign _40_ = d_in[126:123] == 4'h6;
+  assign _41_ = d_in[126:123] == 4'h7;
+  assign _42_ = d_in[126:123] == 4'h9;
+  assign _43_ = d_in[126:123] == 4'h8;
+  assign _44_ = d_in[126:123] == 4'ha;
+  assign _45_ = d_in[126:123] == 4'hb;
+  assign _46_ = d_in[126:123] == 4'hc;
+  assign _47_ = d_in[126:123] == 4'hd;
+  assign _48_ = d_in[126:123] == 4'h0;
+  function [71:0] \9268 ;
+    input [71:0] a;
+    input [1079:0] b;
+    input [14:0] s;
+    (* parallel_case *)
+    casez (s)
+      15'b??????????????1:
+        \9268  = b[71:0];
+      15'b?????????????1?:
+        \9268  = b[143:72];
+      15'b????????????1??:
+        \9268  = b[215:144];
+      15'b???????????1???:
+        \9268  = b[287:216];
+      15'b??????????1????:
+        \9268  = b[359:288];
+      15'b?????????1?????:
+        \9268  = b[431:360];
+      15'b????????1??????:
+        \9268  = b[503:432];
+      15'b???????1???????:
+        \9268  = b[575:504];
+      15'b??????1????????:
+        \9268  = b[647:576];
+      15'b?????1?????????:
+        \9268  = b[719:648];
+      15'b????1??????????:
+        \9268  = b[791:720];
+      15'b???1???????????:
+        \9268  = b[863:792];
+      15'b??1????????????:
+        \9268  = b[935:864];
+      15'b?1?????????????:
+        \9268  = b[1007:936];
+      15'b1??????????????:
+        \9268  = b[1079:1008];
+      default:
+        \9268  = a;
+    endcase
+  endfunction
+  assign _49_ = \9268 (72'hxxxxxxxxxxxxxxxxxx, { 72'h000000000000000000, r_in[127:64], d_in[111:105], d_in[110], 59'h000000000000000, d_in[81:77], 66'h00000000000000000, d_in[67], d_in[81:77], 80'h00ffffffffffffffff00, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:72], d_in[86:82], d_in[66], 24'h000400, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:68], 10'h000, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:68], 10'h000, d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91:68], 42'h00000000000, d_in[81:66], 24'h000000, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:66], 24'h000000, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:66], 56'h00000000000000, d_in[81:66], 80'h00000000000000000000, r_in[127:64], 2'h0, d_in[81:77], 1'h1 }, { _48_, _47_, _46_, _45_, _44_, _43_, _42_, _41_, _40_, _39_, _38_, _37_, _36_, _35_, _34_ });
+  assign _50_ = d_in[129:127] == 3'h1;
+  assign _51_ = d_in[129:127] == 3'h2;
+  assign _52_ = d_in[129:127] == 3'h4;
+  assign _53_ = d_in[129:127] == 3'h3;
+  assign _54_ = d_in[129:127] == 3'h0;
+  function [71:0] \9324 ;
+    input [71:0] a;
+    input [359:0] b;
+    input [4:0] s;
+    (* parallel_case *)
+    casez (s)
+      5'b????1:
+        \9324  = b[71:0];
+      5'b???1?:
+        \9324  = b[143:72];
+      5'b??1??:
+        \9324  = b[215:144];
+      5'b?1???:
+        \9324  = b[287:216];
+      5'b1????:
+        \9324  = b[359:288];
+      default:
+        \9324  = a;
+    endcase
+  endfunction
+  assign _55_ = \9324 (72'hxxxxxxxxxxxxxxxxxx, { 216'h000000000000000000000000000000000000000000000000000000, r_in[191:128], 2'h0, d_in[76:72], 1'h1, r_in[191:128], 2'h0, d_in[91:87], 1'h1 }, { _54_, _53_, _52_, _51_, _50_ });
+  assign _56_ = d_in[132:130] == 3'h1;
+  assign _57_ = d_in[132:130] == 3'h2;
+  assign _58_ = d_in[132:130] == 3'h4;
+  assign _59_ = d_in[132:130] == 3'h3;
+  assign _60_ = d_in[132:130] == 3'h0;
+  function [7:0] \9385 ;
+    input [7:0] a;
+    input [39:0] b;
+    input [4:0] s;
+    (* parallel_case *)
+    casez (s)
+      5'b????1:
+        \9385  = b[7:0];
+      5'b???1?:
+        \9385  = b[15:8];
+      5'b??1??:
+        \9385  = b[23:16];
+      5'b?1???:
+        \9385  = b[31:24];
+      5'b1????:
+        \9385  = b[39:32];
+      default:
+        \9385  = a;
+    endcase
+  endfunction
+  assign _61_ = \9385 (8'hxx, { 8'h00, d_in[104:98], d_in[103], 10'h000, d_in[86:82], 3'h4, d_in[91:87], 1'h1 }, { _60_, _59_, _58_, _57_, _56_ });
+  assign _62_ = _33_[0] & d_in[0];
+  assign _63_ = _49_[0] & d_in[0];
+  assign _64_ = _55_[0] & d_in[0];
+  assign _65_ = d_in[142:140] == 3'h1;
+  assign _66_ = d_in[142:140] == 3'h2;
+  assign _67_ = d_in[142:140] == 3'h3;
+  assign _68_ = d_in[142:140] == 3'h4;
+  assign _69_ = d_in[142:140] == 3'h0;
+  function [3:0] \9414 ;
+    input [3:0] a;
+    input [19:0] b;
+    input [4:0] s;
+    (* parallel_case *)
+    casez (s)
+      5'b????1:
+        \9414  = b[3:0];
+      5'b???1?:
+        \9414  = b[7:4];
+      5'b??1??:
+        \9414  = b[11:8];
+      5'b?1???:
+        \9414  = b[15:12];
+      5'b1????:
+        \9414  = b[19:16];
+      default:
+        \9414  = a;
+    endcase
+  endfunction
+  assign _70_ = \9414 (4'hx, 20'h08421, { _69_, _68_, _67_, _66_, _65_ });
+  assign _71_ = d_in[150:149] == 2'h2;
+  assign _72_ = d_in[150:149] == 2'h1;
+  assign _73_ = d_in[150:149] == 2'h0;
+  function [0:0] \9463 ;
+    input [0:0] a;
+    input [2:0] b;
+    input [2:0] s;
+    (* parallel_case *)
+    casez (s)
+      3'b??1:
+        \9463  = b[0:0];
+      3'b?1?:
+        \9463  = b[1:1];
+      3'b1??:
+        \9463  = b[2:2];
+      default:
+        \9463  = a;
+    endcase
+  endfunction
+  assign _74_ = \9463 (1'hx, { 2'h1, d_in[66] }, { _73_, _72_, _71_ });
+  assign _75_ = d_in[119:114] == 6'h2d;
+  assign _76_ = d_in[119:114] == 6'h2c;
+  assign _77_ = _75_ | _76_;
+  assign _78_ = ~ _77_;
+  assign _79_ = d_in[150:149] == 2'h2;
+  function [0:0] \9493 ;
+    input [0:0] a;
+    input [0:0] b;
+    input [0:0] s;
+    (* parallel_case *)
+    casez (s)
+      1'b1:
+        \9493  = b[0:0];
+      default:
+        \9493  = a;
+    endcase
+  endfunction
+  assign _80_ = \9493 (1'h0, d_in[76], _79_);
+  assign _81_ = _78_ ? _80_ : 1'h0;
+  assign _82_ = d_in[151] ? d_in[66] : 1'h0;
+  assign _83_ = d_in[113:112] == 2'h1;
+  assign _84_ = 1'h1 & _83_;
+  assign gpr_bypassable = _84_ ? 1'h1 : 1'h0;
+  assign update_gpr_write_valid = _82_ ? 1'h1 : d_in[145];
+  assign update_gpr_write_reg = _82_ ? 7'h20 : _33_[7:1];
+  assign _85_ = d_in[150:149] == 2'h2;
+  assign _86_ = d_in[150:149] == 2'h1;
+  assign _87_ = d_in[150:149] == 2'h0;
+  function [0:0] \9604 ;
+    input [0:0] a;
+    input [2:0] b;
+    input [2:0] s;
+    (* parallel_case *)
+    casez (s)
+      3'b??1:
+        \9604  = b[0:0];
+      3'b?1?:
+        \9604  = b[1:1];
+      3'b1??:
+        \9604  = b[2:2];
+      default:
+        \9604  = a;
+    endcase
+  endfunction
+  assign _88_ = \9604 (1'hx, { 2'h1, d_in[66] }, { _87_, _86_, _85_ });
+  assign cr_write_valid = d_in[134] | _88_;
+  assign _89_ = d_in[113:112] == 2'h1;
+  assign _90_ = 1'h1 & _89_;
+  assign cr_bypass_avail = _90_ ? d_in[134] : 1'h0;
+  assign _91_ = rst | flush_in;
+  assign rin = _91_ ? 380'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : { d_in[153], d_in[146:143], _70_, d_in[97:66], d_in[148:147], d_in[134], 1'h0, d_in[139:135], _81_, _74_, _82_, c_in[36:32], cr_bypass, c_in[31:0], gpr_c_bypass, gpr_b_bypass, gpr_a_bypass, _55_[71:8], _49_[71:8], _33_[71:8], _49_[7:1], _33_[7:1], _61_[7:1], d_in[65:2], d_in[119:112], control_valid_out };
+  control_1 control_0 (
+    .busy_in(busy_in),
+    .clk(clk),
+    .complete_in(complete_in),
+    .cr_bypass(cr_bypass),
+    .cr_bypassable(cr_bypass_avail),
+    .cr_read_in(d_in[133]),
+    .cr_write_in(cr_write_valid),
+    .deferred(deferred),
+    .flush_in(flush_in),
+    .gpr_a_read_in(_33_[7:1]),
+    .gpr_a_read_valid_in(_33_[0]),
+    .gpr_b_read_in(_49_[7:1]),
+    .gpr_b_read_valid_in(_49_[0]),
+    .gpr_bypass_a(gpr_a_bypass),
+    .gpr_bypass_b(gpr_b_bypass),
+    .gpr_bypass_c(gpr_c_bypass),
+    .gpr_bypassable(gpr_bypassable),
+    .gpr_c_read_in(_55_[7:1]),
+    .gpr_c_read_valid_in(_55_[0]),
+    .gpr_write_in(_61_[7:1]),
+    .gpr_write_valid_in(_61_[0]),
+    .rst(rst),
+    .sgl_pipe_in(d_in[152]),
+    .stall_out(_00_),
+    .stop_mark_in(d_in[1]),
+    .stopped_out(_01_),
+    .update_gpr_write_reg(update_gpr_write_reg),
+    .update_gpr_write_valid(update_gpr_write_valid),
+    .valid_in(d_in[0]),
+    .valid_out(control_valid_out)
+  );
+  assign stall_out = _00_;
+  assign stopped_out = _01_;
+  assign e_out = r;
+  assign r_out = { _17_, _64_, _12_, _63_, _07_, _62_ };
+  assign c_out = d_in[133];
+  assign log_out = 10'hzzz;
+endmodule
+
+module divider(clk, rst, d_in, d_out);
+  wire [128:0] _00_;
+  wire _01_;
+  wire _02_;
+  wire _03_;
+  wire _04_;
+  wire _05_;
+  wire [63:0] _06_;
+  wire [6:0] _07_;
+  wire _08_;
+  wire _09_;
+  wire _10_;
+  wire _11_;
+  wire [6:0] _12_;
+  wire _13_;
+  wire [6:0] _14_;
+  wire [128:0] _15_;
+  wire [63:0] _16_;
+  wire [6:0] _17_;
+  wire _18_;
+  wire [128:0] _19_;
+  wire [63:0] _20_;
+  wire [6:0] _21_;
+  wire _22_;
+  wire [128:0] _23_;
+  wire [63:0] _24_;
+  wire _25_;
+  wire [6:0] _26_;
+  wire _27_;
+  wire _28_;
+  wire [128:0] _29_;
+  wire [63:0] _30_;
+  wire [63:0] _31_;
+  wire _32_;
+  wire [6:0] _33_;
+  wire _34_;
+  wire _35_;
+  wire _36_;
+  wire _37_;
+  wire _38_;
+  wire _39_;
+  wire [128:0] _40_;
+  wire [63:0] _41_;
+  wire [63:0] _42_;
+  wire _43_;
+  wire [6:0] _44_;
+  wire _45_;
+  wire _46_;
+  wire _47_;
+  wire _48_;
+  wire _49_;
+  wire _50_;
+  wire [64:0] _51_;
+  wire _52_;
+  wire _53_;
+  wire _54_;
+  wire _55_;
+  wire _56_;
+  wire _57_;
+  wire _58_;
+  wire _59_;
+  wire _60_;
+  wire _61_;
+  wire [63:0] _62_;
+  wire _63_;
+  wire _64_;
+  reg [65:0] _65_;
+  input clk;
+  reg [6:0] count;
+  input [133:0] d_in;
+  output [65:0] d_out;
+  reg [128:0] dend;
+  wire did_ovf;
+  reg [63:0] div;
+  reg is_32bit;
+  reg is_modulus;
+  reg is_signed;
+  reg neg_result;
+  wire [63:0] oresult;
+  reg overflow;
+  reg ovf32;
+  reg [63:0] quot;
+  wire [63:0] result;
+  input rst;
+  reg running;
+  wire [64:0] sresult;
+  assign _00_ = d_in[131] ? { 1'h0, d_in[64:1], 64'h0000000000000000 } : { 65'h00000000000000000, d_in[64:1] };
+  assign _01_ = count == 7'h3f;
+  assign _02_ = _25_ ? 1'h0 : running;
+  assign _03_ = dend[127:64] >= div;
+  assign _04_ = dend[128] | _03_;
+  assign _05_ = ovf32 | quot[31];
+  assign _06_ = dend[127:64] - div;
+  assign _07_ = count + 7'h01;
+  assign _08_ = dend[128:57] == 72'h000000000000000000;
+  assign _09_ = count[6:3] != 4'h7;
+  assign _10_ = _08_ & _09_;
+  assign _11_ = | { ovf32, quot[31:24] };
+  assign _12_ = count + 7'h08;
+  assign _13_ = ovf32 | quot[31];
+  assign _14_ = count + 7'h01;
+  assign _15_ = _10_ ? { dend[120:0], 8'h00 } : { dend[127:0], 1'h0 };
+  assign _16_ = _10_ ? { quot[55:0], 8'h00 } : { quot[62:0], 1'h0 };
+  assign _17_ = _10_ ? _12_ : _14_;
+  assign _18_ = _10_ ? _11_ : _13_;
+  assign _19_ = _04_ ? { _06_, dend[63:0], 1'h0 } : _15_;
+  assign _20_ = _04_ ? { quot[62:0], 1'h1 } : _16_;
+  assign _21_ = _04_ ? _07_ : _17_;
+  assign _22_ = _04_ ? _05_ : _18_;
+  assign _23_ = running ? _19_ : dend;
+  assign _24_ = running ? _20_ : quot;
+  assign _25_ = running & _01_;
+  assign _26_ = running ? _21_ : 7'h00;
+  assign _27_ = running ? quot[63] : overflow;
+  assign _28_ = running ? _22_ : ovf32;
+  assign _29_ = d_in[0] ? _00_ : _23_;
+  assign _30_ = d_in[0] ? d_in[128:65] : div;
+  assign _31_ = d_in[0] ? 64'h0000000000000000 : _24_;
+  assign _32_ = d_in[0] ? 1'h1 : _02_;
+  assign _33_ = d_in[0] ? 7'h7f : _26_;
+  assign _34_ = d_in[0] ? d_in[133] : neg_result;
+  assign _35_ = d_in[0] ? d_in[132] : is_modulus;
+  assign _36_ = d_in[0] ? d_in[130] : is_32bit;
+  assign _37_ = d_in[0] ? d_in[129] : is_signed;
+  assign _38_ = d_in[0] ? 1'h0 : _27_;
+  assign _39_ = d_in[0] ? 1'h0 : _28_;
+  assign _40_ = rst ? 129'h000000000000000000000000000000000 : _29_;
+  assign _41_ = rst ? 64'h0000000000000000 : _30_;
+  assign _42_ = rst ? 64'h0000000000000000 : _31_;
+  assign _43_ = rst ? 1'h0 : _32_;
+  assign _44_ = rst ? 7'h00 : _33_;
+  assign _45_ = rst ? neg_result : _34_;
+  assign _46_ = rst ? is_modulus : _35_;
+  assign _47_ = rst ? is_32bit : _36_;
+  assign _48_ = rst ? is_signed : _37_;
+  assign _49_ = rst ? overflow : _38_;
+  assign _50_ = rst ? ovf32 : _39_;
+  always @(posedge clk)
+    dend <= _40_;
+  always @(posedge clk)
+    div <= _41_;
+  always @(posedge clk)
+    quot <= _42_;
+  always @(posedge clk)
+    running <= _43_;
+  always @(posedge clk)
+    count <= _44_;
+  always @(posedge clk)
+    neg_result <= _45_;
+  always @(posedge clk)
+    is_modulus <= _46_;
+  always @(posedge clk)
+    is_32bit <= _47_;
+  always @(posedge clk)
+    is_signed <= _48_;
+  always @(posedge clk)
+    overflow <= _49_;
+  always @(posedge clk)
+    ovf32 <= _50_;
+  assign result = is_modulus ? dend[128:65] : quot;
+  assign _51_ = - $signed({ 1'h0, result });
+  assign sresult = neg_result ? _51_ : { 1'h0, result };
+  assign _52_ = ~ is_32bit;
+  assign _53_ = sresult[64] ^ sresult[63];
+  assign _54_ = is_signed & _53_;
+  assign _55_ = overflow | _54_;
+  assign _56_ = sresult[32] != sresult[31];
+  assign _57_ = ovf32 | _56_;
+  assign _58_ = _57_ ? 1'h1 : 1'h0;
+  assign _59_ = is_signed ? _58_ : ovf32;
+  assign did_ovf = _52_ ? _55_ : _59_;
+  assign _60_ = ~ is_modulus;
+  assign _61_ = is_32bit & _60_;
+  assign _62_ = _61_ ? { 32'h00000000, sresult[31:0] } : sresult[63:0];
+  assign oresult = did_ovf ? 64'h0000000000000000 : _62_;
+  assign _63_ = count == 7'h40;
+  assign _64_ = _63_ ? 1'h1 : 1'h0;
+  always @(posedge clk)
+    _65_ <= { did_ovf, oresult, _64_ };
+  assign d_out = _65_;
+endmodule
+
+module dmi_dtm_jtag_8_64(sys_clk, sys_reset, dmi_din, dmi_ack, jtag_tck, jtag_tdi, jtag_tms, jtag_trst, dmi_addr, dmi_dout, dmi_req, dmi_wr, jtag_tdo);
+  wire _00_;
+  wire _01_;
+  wire _02_;
+  wire _03_;
+  wire _04_;
+  wire _05_;
+  wire _06_;
+  wire _07_;
+  wire _08_;
+  wire _09_;
+  wire _10_;
+  wire _11_;
+  wire _12_;
+  wire _13_;
+  wire _14_;
+  wire _15_;
+  wire [1:0] _16_;
+  wire [1:0] _17_;
+  wire [71:0] _18_;
+  wire _19_;
+  wire _20_;
+  wire _21_;
+  wire _22_;
+  wire [63:0] _23_;
+  wire [63:0] _24_;
+  wire [63:0] _25_;
+  wire [63:0] _26_;
+  wire [7:0] _27_;
+  wire [1:0] _28_;
+  wire _29_;
+  wire [73:0] _30_;
+  wire [73:0] _31_;
+  wire [73:0] _32_;
+  wire _33_;
+  wire capture;
+  input dmi_ack;
+  reg dmi_ack_0;
+  reg dmi_ack_1;
+  output [7:0] dmi_addr;
+  input [63:0] dmi_din;
+  output [63:0] dmi_dout;
+  output dmi_req;
+  output dmi_wr;
+  wire jtag_bsy;
+  reg jtag_req;
+  reg jtag_req_0;
+  reg jtag_req_1;
+  input jtag_tck;
+  input jtag_tdi;
+  output jtag_tdo;
+  input jtag_tms;
+  input jtag_trst;
+  wire op_valid;
+  reg [73:0] request;
+  wire [1:0] rsp_op;
+  wire sel;
+  wire shift;
+  reg [73:0] shiftr;
+  input sys_clk;
+  input sys_reset;
+  wire tdi;
+  wire update;
+  assign _06_ = sys_reset ? 1'h0 : jtag_req;
+  assign _07_ = sys_reset ? 1'h0 : jtag_req_0;
+  always @(posedge sys_clk)
+    jtag_req_0 <= _06_;
+  always @(posedge sys_clk)
+    jtag_req_1 <= _07_;
+  always @(posedge jtag_tck, posedge jtag_trst)
+    if (jtag_trst) dmi_ack_0 <= 1'h0;
+    else dmi_ack_0 <= dmi_ack;
+  always @(posedge jtag_tck, posedge jtag_trst)
+    if (jtag_trst) dmi_ack_1 <= 1'h0;
+    else dmi_ack_1 <= dmi_ack_0;
+  assign jtag_bsy = jtag_req | dmi_ack_1;
+  assign _08_ = shiftr[1:0] == 2'h1;
+  assign _09_ = shiftr[1:0] == 2'h2;
+  function [0:0] \6934 ;
+    input [0:0] a;
+    input [1:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \6934  = b[0:0];
+      2'b1?:
+        \6934  = b[1:1];
+      default:
+        \6934  = a;
+    endcase
+  endfunction
+  assign op_valid = \6934 (1'h0, 2'h3, { _09_, _08_ });
+  assign rsp_op = jtag_bsy ? 2'h3 : 2'h0;
+  assign _10_ = request[1:0] == 2'h2;
+  assign _11_ = _10_ ? 1'h1 : 1'h0;
+  assign _12_ = jtag_trst | sys_reset;
+  assign _13_ = update & op_valid;
+  assign _14_ = ~ jtag_bsy;
+  assign _15_ = _20_ ? 1'h1 : jtag_req;
+  assign _16_ = shift ? shiftr[2:1] : shiftr[1:0];
+  assign _17_ = _13_ ? 2'h3 : _16_;
+  assign _18_ = shift ? { tdi, shiftr[73:3] } : shiftr[73:2];
+  assign _19_ = _13_ & _14_;
+  assign _20_ = _13_ & _14_;
+  assign _21_ = jtag_req & dmi_ack_1;
+  assign _22_ = request[1:0] == 2'h1;
+  assign _23_ = _19_ ? shiftr[65:2] : request[65:2];
+  assign _24_ = _22_ ? dmi_din : _23_;
+  assign _25_ = _19_ ? shiftr[65:2] : request[65:2];
+  assign _26_ = _21_ ? _24_ : _25_;
+  assign _27_ = _19_ ? shiftr[73:66] : request[73:66];
+  assign _28_ = _19_ ? shiftr[1:0] : request[1:0];
+  assign _29_ = _21_ ? 1'h0 : _15_;
+  assign _30_ = capture ? { request[73:2], rsp_op } : { _18_, _17_ };
+  assign _31_ = sel ? _30_ : shiftr;
+  always @(posedge jtag_tck, posedge _12_)
+    if (_12_) shiftr <= 74'h0000000000000000000;
+    else shiftr <= _31_;
+  assign _32_ = sel ? { _27_, _26_, _28_ } : request;
+  always @(posedge jtag_tck, posedge _12_)
+    if (_12_) request <= 74'h0000000000000000000;
+    else request <= _32_;
+  assign _33_ = sel ? _29_ : jtag_req;
+  always @(posedge jtag_tck, posedge _12_)
+    if (_12_) jtag_req <= 1'h0;
+    else jtag_req <= _33_;
+  tap_top tap_top0 (
+    .bs_chain_tdi_i(1'h0),
+    .capture_dr_o(capture),
+    .debug_select_o(sel),
+    .debug_tdi_i(shiftr[0]),
+    .extest_select_o(_03_),
+    .mbist_select_o(_05_),
+    .mbist_tdi_i(1'h0),
+    .pause_dr_o(_02_),
+    .sample_preload_select_o(_04_),
+    .shift_dr_o(shift),
+    .tck_pad_i(jtag_tck),
+    .tdi_pad_i(jtag_tdi),
+    .tdo_o(tdi),
+    .tdo_pad_o(_00_),
+    .tdo_padoe_o(_01_),
+    .tms_pad_i(jtag_tms),
+    .trst_pad_i(jtag_trst),
+    .update_dr_o(update)
+  );
+  assign dmi_addr = request[73:66];
+  assign dmi_dout = request[65:2];
+  assign dmi_req = jtag_req_1;
+  assign dmi_wr = _11_;
+  assign jtag_tdo = _00_;
+endmodule
+
+module execute1_0_0e356ba505631fbf715758bed27d503f8b260e3a(
+`ifdef USE_POWER_PINS
+        vccd1, vssd1,
+`endif
+ clk, rst, e_in, l_in, fp_in, ext_irq_in, log_rd_data, log_wr_addr, flush_out, busy_out, l_out, f_out, fp_out, e_out, dbg_msr_out, icache_inval, terminate_out, log_out, log_rd_addr);
+`ifdef USE_POWER_PINS
+  inout vccd1;        // User area 1 1.8V supply
+  inout vssd1;        // User area 1 digital ground
+`endif
+  wire _0000_;
+  wire _0001_;
+  wire _0002_;
+  wire _0003_;
+  wire _0004_;
+  wire _0005_;
+  wire [455:0] _0006_;
+  wire [127:0] _0007_;
+  wire [63:0] _0008_;
+  wire [63:0] _0009_;
+  wire _0010_;
+  wire [63:0] _0011_;
+  wire [4:0] _0012_;
+  wire _0013_;
+  wire _0014_;
+  wire [3:0] _0015_;
+  wire [3:0] _0016_;
+  wire [3:0] _0017_;
+  wire [3:0] _0018_;
+  wire [3:0] _0019_;
+  wire [3:0] _0020_;
+  wire [3:0] _0021_;
+  wire [3:0] _0022_;
+  wire _0023_;
+  wire [63:0] _0024_;
+  wire [63:0] _0025_;
+  wire _0026_;
+  wire _0027_;
+  wire _0028_;
+  wire _0029_;
+  wire _0030_;
+  wire [64:0] _0031_;
+  wire [64:0] _0032_;
+  wire _0033_;
+  wire _0034_;
+  wire _0035_;
+  wire _0036_;
+  wire _0037_;
+  wire [63:0] _0038_;
+  wire [63:0] _0039_;
+  wire _0040_;
+  wire [63:0] _0041_;
+  wire [63:0] _0042_;
+  wire _0043_;
+  wire _0044_;
+  wire _0045_;
+  wire [63:0] _0046_;
+  wire [127:0] _0047_;
+  wire _0048_;
+  wire [127:0] _0049_;
+  wire [127:0] _0050_;
+  wire _0051_;
+  wire _0052_;
+  wire _0053_;
+  wire _0054_;
+  wire _0055_;
+  wire _0056_;
+  wire _0057_;
+  wire _0058_;
+  wire [63:0] _0059_;
+  wire [127:0] _0060_;
+  wire [127:0] _0061_;
+  wire _0062_;
+  wire [63:0] _0063_;
+  wire [63:0] _0064_;
+  wire [63:0] _0065_;
+  wire _0066_;
+  wire [63:0] _0067_;
+  wire _0068_;
+  wire [63:0] _0069_;
+  wire _0070_;
+  wire _0071_;
+  wire _0072_;
+  wire _0073_;
+  wire [63:0] _0074_;
+  wire _0075_;
+  wire _0076_;
+  wire _0077_;
+  wire _0078_;
+  wire _0079_;
+  wire _0080_;
+  wire _0081_;
+  wire _0082_;
+  wire [63:0] _0083_;
+  wire [63:0] _0084_;
+  wire _0085_;
+  wire _0086_;
+  wire [5:0] _0087_;
+  wire _0088_;
+  wire _0089_;
+  wire _0090_;
+  wire _0091_;
+  wire _0092_;
+  wire _0093_;
+  wire _0094_;
+  wire _0095_;
+  wire _0096_;
+  wire _0097_;
+  wire _0098_;
+  wire _0099_;
+  wire _0100_;
+  wire _0101_;
+  wire _0102_;
+  wire _0103_;
+  wire _0104_;
+  wire _0105_;
+  wire _0106_;
+  wire _0107_;
+  wire _0108_;
+  wire _0109_;
+  wire _0110_;
+  wire _0111_;
+  wire [5:0] _0112_;
+  wire _0113_;
+  wire _0114_;
+  wire _0115_;
+  wire _0116_;
+  wire _0117_;
+  wire _0118_;
+  wire _0119_;
+  wire _0120_;
+  wire _0121_;
+  wire _0122_;
+  wire _0123_;
+  wire _0124_;
+  wire _0125_;
+  wire _0126_;
+  wire _0127_;
+  wire [63:0] _0128_;
+  wire _0129_;
+  wire _0130_;
+  wire _0131_;
+  wire _0132_;
+  wire _0133_;
+  wire _0134_;
+  wire _0135_;
+  wire _0136_;
+  wire _0137_;
+  wire _0138_;
+  wire _0139_;
+  wire _0140_;
+  wire _0141_;
+  wire _0142_;
+  wire _0143_;
+  wire _0144_;
+  wire _0145_;
+  wire _0146_;
+  wire _0147_;
+  wire _0148_;
+  wire _0149_;
+  wire _0150_;
+  wire _0151_;
+  wire [115:0] _0152_;
+  wire _0153_;
+  wire [1:0] _0154_;
+  wire [1:0] _0155_;
+  wire [1:0] _0156_;
+  wire _0157_;
+  wire [72:0] _0158_;
+  wire [193:0] _0159_;
+  wire _0160_;
+  wire _0161_;
+  wire _0162_;
+  wire _0163_;
+  wire _0164_;
+  wire _0165_;
+  wire _0166_;
+  wire _0167_;
+  wire _0168_;
+  wire [193:0] _0169_;
+  wire _0170_;
+  wire _0171_;
+  wire _0172_;
+  wire [31:0] _0173_;
+  wire _0174_;
+  wire _0175_;
+  wire [31:0] _0176_;
+  wire _0177_;
+  wire _0178_;
+  wire _0179_;
+  wire _0180_;
+  wire _0181_;
+  wire _0182_;
+  wire _0183_;
+  wire _0184_;
+  wire _0185_;
+  wire _0186_;
+  wire _0187_;
+  wire _0188_;
+  wire _0189_;
+  wire _0190_;
+  wire [4:0] _0191_;
+  wire [4:0] _0192_;
+  wire _0193_;
+  wire [3:0] _0194_;
+  wire _0195_;
+  wire _0196_;
+  wire _0197_;
+  wire _0198_;
+  wire _0199_;
+  wire _0200_;
+  wire _0201_;
+  wire _0202_;
+  wire [7:0] _0203_;
+  wire [4:0] _0204_;
+  wire _0205_;
+  wire _0206_;
+  wire _0207_;
+  wire [40:0] _0208_;
+  wire [63:0] _0209_;
+  wire _0210_;
+  wire _0211_;
+  wire [74:0] _0212_;
+  wire [40:0] _0213_;
+  wire [77:0] _0214_;
+  wire [63:0] _0215_;
+  wire _0216_;
+  wire _0217_;
+  wire _0218_;
+  wire _0219_;
+  wire _0220_;
+  wire _0221_;
+  wire _0222_;
+  wire _0223_;
+  wire _0224_;
+  wire _0225_;
+  wire [3:0] _0226_;
+  wire _0227_;
+  wire _0228_;
+  wire _0229_;
+  wire [3:0] _0230_;
+  wire _0231_;
+  wire _0232_;
+  wire _0233_;
+  wire [3:0] _0234_;
+  wire _0235_;
+  wire _0236_;
+  wire _0237_;
+  wire [3:0] _0238_;
+  wire _0239_;
+  wire _0240_;
+  wire _0241_;
+  wire [3:0] _0242_;
+  wire _0243_;
+  wire _0244_;
+  wire _0245_;
+  wire [3:0] _0246_;
+  wire _0247_;
+  wire _0248_;
+  wire _0249_;
+  wire [3:0] _0250_;
+  wire _0251_;
+  wire _0252_;
+  wire _0253_;
+  wire [3:0] _0254_;
+  wire _0255_;
+  wire _0256_;
+  wire _0257_;
+  wire [3:0] _0258_;
+  wire _0259_;
+  wire _0260_;
+  wire _0261_;
+  wire [3:0] _0262_;
+  wire _0263_;
+  wire _0264_;
+  wire _0265_;
+  wire [3:0] _0266_;
+  wire _0267_;
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+  wire _1060_;
+  wire _1061_;
+  wire _1062_;
+  wire _1063_;
+  wire _1064_;
+  wire _1065_;
+  wire _1066_;
+  wire [2:0] _1067_;
+  wire _1068_;
+  wire [64:0] _1069_;
+  wire [64:0] _1070_;
+  wire [64:0] _1071_;
+  wire [64:0] _1072_;
+  wire [64:0] _1073_;
+  wire [64:0] _1074_;
+  wire [18:0] _1075_;
+  wire [18:0] _1076_;
+  wire [18:0] _1077_;
+  wire [18:0] _1078_;
+  wire [18:0] _1079_;
+  wire [18:0] _1080_;
+  wire [63:0] _1081_;
+  wire _1082_;
+  wire _1083_;
+  wire _1084_;
+  wire [63:0] _1085_;
+  wire [63:0] _1086_;
+  wire [4:0] _1087_;
+  wire _1088_;
+  wire [63:0] _1089_;
+  wire [63:0] _1090_;
+  wire [63:0] _1091_;
+  wire _1092_;
+  wire _1093_;
+  wire _1094_;
+  wire [63:0] _1095_;
+  wire [63:0] _1096_;
+  wire [63:0] _1097_;
+  wire [6:0] _1098_;
+  wire [6:0] _1099_;
+  wire _1100_;
+  wire _1101_;
+  wire _1102_;
+  wire [40:0] _1103_;
+  wire _1104_;
+  wire _1105_;
+  wire _1106_;
+  wire _1107_;
+  wire _1108_;
+  wire [63:0] _1109_;
+  wire _1110_;
+  wire _1111_;
+  wire _1112_;
+  wire _1113_;
+  wire [1:0] _1114_;
+  wire _1115_;
+  wire _1116_;
+  wire _1117_;
+  wire _1118_;
+  wire [63:0] _1119_;
+  wire _1120_;
+  wire _1121_;
+  wire _1122_;
+  wire [1:0] _1123_;
+  wire _1124_;
+  wire _1125_;
+  wire _1126_;
+  wire _1127_;
+  wire [63:0] _1128_;
+  wire _1129_;
+  wire _1130_;
+  wire _1131_;
+  wire [1:0] _1132_;
+  wire _1133_;
+  wire _1134_;
+  wire _1135_;
+  wire _1136_;
+  wire [63:0] _1137_;
+  wire _1138_;
+  wire _1139_;
+  wire _1140_;
+  wire [1:0] _1141_;
+  wire _1142_;
+  wire _1143_;
+  wire _1144_;
+  wire _1145_;
+  wire _1146_;
+  wire _1147_;
+  wire _1148_;
+  wire _1149_;
+  wire _1150_;
+  wire [7:0] _1151_;
+  wire [63:0] _1152_;
+  wire _1153_;
+  wire _1154_;
+  wire [4:0] _1155_;
+  wire _1156_;
+  wire _1157_;
+  wire _1158_;
+  wire _1159_;
+  wire _1160_;
+  wire _1161_;
+  wire _1162_;
+  wire _1163_;
+  wire _1164_;
+  wire _1165_;
+  wire _1166_;
+  wire [63:0] _1167_;
+  wire _1168_;
+  wire _1169_;
+  wire _1170_;
+  wire _1171_;
+  wire _1172_;
+  wire _1173_;
+  wire _1174_;
+  wire _1175_;
+  wire _1176_;
+  wire _1177_;
+  wire _1178_;
+  wire _1179_;
+  wire _1180_;
+  wire _1181_;
+  wire _1182_;
+  wire _1183_;
+  wire _1184_;
+  wire _1185_;
+  wire _1186_;
+  wire _1187_;
+  wire _1188_;
+  wire _1189_;
+  wire _1190_;
+  wire _1191_;
+  wire _1192_;
+  wire _1193_;
+  wire _1194_;
+  wire _1195_;
+  wire _1196_;
+  wire _1197_;
+  wire _1198_;
+  wire _1199_;
+  wire _1200_;
+  wire _1201_;
+  wire _1202_;
+  wire _1203_;
+  wire _1204_;
+  wire _1205_;
+  wire _1206_;
+  wire _1207_;
+  wire _1208_;
+  wire _1209_;
+  wire _1210_;
+  wire _1211_;
+  wire _1212_;
+  wire _1213_;
+  wire _1214_;
+  wire _1215_;
+  wire _1216_;
+  wire _1217_;
+  wire _1218_;
+  wire _1219_;
+  wire _1220_;
+  wire _1221_;
+  wire _1222_;
+  wire _1223_;
+  wire _1224_;
+  wire _1225_;
+  wire _1226_;
+  wire _1227_;
+  wire _1228_;
+  wire _1229_;
+  wire _1230_;
+  wire _1231_;
+  wire _1232_;
+  wire _1233_;
+  wire _1234_;
+  wire _1235_;
+  wire _1236_;
+  wire _1237_;
+  wire _1238_;
+  wire _1239_;
+  wire _1240_;
+  wire _1241_;
+  wire _1242_;
+  wire _1243_;
+  wire _1244_;
+  wire _1245_;
+  wire _1246_;
+  wire _1247_;
+  wire _1248_;
+  wire _1249_;
+  wire _1250_;
+  wire _1251_;
+  wire _1252_;
+  wire _1253_;
+  wire _1254_;
+  wire _1255_;
+  wire _1256_;
+  wire _1257_;
+  wire _1258_;
+  wire _1259_;
+  wire _1260_;
+  wire _1261_;
+  wire _1262_;
+  wire _1263_;
+  wire _1264_;
+  wire _1265_;
+  wire _1266_;
+  wire _1267_;
+  wire _1268_;
+  wire _1269_;
+  wire _1270_;
+  wire _1271_;
+  wire _1272_;
+  wire _1273_;
+  wire _1274_;
+  wire _1275_;
+  wire _1276_;
+  wire _1277_;
+  wire _1278_;
+  wire _1279_;
+  wire _1280_;
+  wire _1281_;
+  wire _1282_;
+  wire _1283_;
+  wire _1284_;
+  wire _1285_;
+  wire _1286_;
+  wire _1287_;
+  wire _1288_;
+  wire _1289_;
+  wire _1290_;
+  wire _1291_;
+  wire _1292_;
+  wire _1293_;
+  wire _1294_;
+  wire _1295_;
+  wire _1296_;
+  wire _1297_;
+  wire _1298_;
+  wire _1299_;
+  wire _1300_;
+  wire _1301_;
+  wire _1302_;
+  wire _1303_;
+  wire _1304_;
+  wire _1305_;
+  wire _1306_;
+  wire _1307_;
+  wire _1308_;
+  wire _1309_;
+  wire _1310_;
+  wire _1311_;
+  wire _1312_;
+  wire _1313_;
+  wire _1314_;
+  wire _1315_;
+  wire _1316_;
+  wire _1317_;
+  wire _1318_;
+  wire _1319_;
+  wire _1320_;
+  wire _1321_;
+  wire _1322_;
+  wire _1323_;
+  wire _1324_;
+  wire _1325_;
+  wire _1326_;
+  wire _1327_;
+  wire _1328_;
+  wire _1329_;
+  wire _1330_;
+  wire _1331_;
+  wire _1332_;
+  wire _1333_;
+  wire _1334_;
+  wire _1335_;
+  wire _1336_;
+  wire _1337_;
+  wire _1338_;
+  wire _1339_;
+  wire _1340_;
+  wire _1341_;
+  wire _1342_;
+  wire _1343_;
+  wire _1344_;
+  wire _1345_;
+  wire _1346_;
+  wire _1347_;
+  wire _1348_;
+  wire _1349_;
+  wire _1350_;
+  wire _1351_;
+  wire _1352_;
+  wire _1353_;
+  wire _1354_;
+  wire _1355_;
+  wire _1356_;
+  wire _1357_;
+  wire _1358_;
+  wire _1359_;
+  wire _1360_;
+  wire _1361_;
+  wire _1362_;
+  wire _1363_;
+  wire _1364_;
+  wire _1365_;
+  wire _1366_;
+  wire _1367_;
+  wire _1368_;
+  wire _1369_;
+  wire _1370_;
+  wire _1371_;
+  wire _1372_;
+  wire _1373_;
+  wire _1374_;
+  wire _1375_;
+  wire _1376_;
+  wire _1377_;
+  wire _1378_;
+  wire _1379_;
+  wire _1380_;
+  wire _1381_;
+  wire _1382_;
+  wire _1383_;
+  wire _1384_;
+  wire _1385_;
+  wire _1386_;
+  wire _1387_;
+  wire _1388_;
+  wire _1389_;
+  wire _1390_;
+  wire _1391_;
+  wire _1392_;
+  wire _1393_;
+  wire _1394_;
+  wire [63:0] a_in;
+  wire [63:0] b_in;
+  output busy_out;
+  wire [63:0] c_in;
+  input clk;
+  wire [63:0] countzero_result;
+  wire [31:0] cr_in;
+  reg [320:0] ctrl = 321'h000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  output [63:0] dbg_msr_out;
+  wire [65:0] divider_to_x;
+  input [379:0] e_in;
+  output [193:0] e_out;
+  input ext_irq_in;
+  output [68:0] f_out;
+  output flush_out;
+  input [3:0] fp_in;
+  output [306:0] fp_out;
+  output icache_inval;
+  input [8:0] l_in;
+  output [325:0] l_out;
+  output [14:0] log_out;
+  output [31:0] log_rd_addr;
+  input [63:0] log_rd_data;
+  input [31:0] log_wr_addr;
+  wire [63:0] logical_result;
+  wire [129:0] multiply_to_x;
+  reg [455:0] r;
+  wire [63:0] random_cond;
+  wire random_err;
+  wire [63:0] random_raw;
+  wire right_shift;
+  wire rot_clear_left;
+  wire rot_clear_right;
+  wire rot_sign_ext;
+  wire rotator_carry;
+  wire [63:0] rotator_result;
+  input rst;
+  output terminate_out;
+  wire valid_in;
+  reg [0:0] \$mem$\14259  [63:0];
+  reg [0:0] \14259  [63:0];
+  initial begin
+    \14259 [0] = 1'h0;
+    \14259 [1] = 1'h0;
+    \14259 [2] = 1'h0;
+    \14259 [3] = 1'h0;
+    \14259 [4] = 1'h0;
+    \14259 [5] = 1'h1;
+    \14259 [6] = 1'h0;
+    \14259 [7] = 1'h0;
+    \14259 [8] = 1'h0;
+    \14259 [9] = 1'h0;
+    \14259 [10] = 1'h0;
+    \14259 [11] = 1'h0;
+    \14259 [12] = 1'h0;
+    \14259 [13] = 1'h0;
+    \14259 [14] = 1'h1;
+    \14259 [15] = 1'h0;
+    \14259 [16] = 1'h0;
+    \14259 [17] = 1'h0;
+    \14259 [18] = 1'h0;
+    \14259 [19] = 1'h0;
+    \14259 [20] = 1'h0;
+    \14259 [21] = 1'h0;
+    \14259 [22] = 1'h1;
+    \14259 [23] = 1'h0;
+    \14259 [24] = 1'h0;
+    \14259 [25] = 1'h0;
+    \14259 [26] = 1'h1;
+    \14259 [27] = 1'h0;
+    \14259 [28] = 1'h0;
+    \14259 [29] = 1'h0;
+    \14259 [30] = 1'h0;
+    \14259 [31] = 1'h0;
+    \14259 [32] = 1'h0;
+    \14259 [33] = 1'h0;
+    \14259 [34] = 1'h0;
+    \14259 [35] = 1'h0;
+    \14259 [36] = 1'h0;
+    \14259 [37] = 1'h0;
+    \14259 [38] = 1'h0;
+    \14259 [39] = 1'h0;
+    \14259 [40] = 1'h0;
+    \14259 [41] = 1'h0;
+    \14259 [42] = 1'h0;
+    \14259 [43] = 1'h0;
+    \14259 [44] = 1'h0;
+    \14259 [45] = 1'h0;
+    \14259 [46] = 1'h0;
+    \14259 [47] = 1'h0;
+    \14259 [48] = 1'h0;
+    \14259 [49] = 1'h0;
+    \14259 [50] = 1'h0;
+    \14259 [51] = 1'h0;
+    \14259 [52] = 1'h0;
+    \14259 [53] = 1'h0;
+    \14259 [54] = 1'h0;
+    \14259 [55] = 1'h0;
+    \14259 [56] = 1'h0;
+    \14259 [57] = 1'h0;
+    \14259 [58] = 1'h0;
+    \14259 [59] = 1'h1;
+    \14259 [60] = 1'h0;
+    \14259 [61] = 1'h0;
+    \14259 [62] = 1'h0;
+    \14259 [63] = 1'h0;
+  end
+  assign _1168_ = \14259 [_0112_];
+  assign _1251_ = _0355_[0] ? cr_in[1] : cr_in[0];
+  assign _1252_ = _0355_[0] ? cr_in[5] : cr_in[4];
+  assign _1253_ = _0355_[0] ? cr_in[9] : cr_in[8];
+  assign _1254_ = _0355_[0] ? cr_in[13] : cr_in[12];
+  assign _1255_ = _0355_[0] ? cr_in[17] : cr_in[16];
+  assign _1256_ = _0355_[0] ? cr_in[21] : cr_in[20];
+  assign _1257_ = _0355_[0] ? cr_in[25] : cr_in[24];
+  assign _1258_ = _0355_[0] ? cr_in[29] : cr_in[28];
+  assign _1259_ = _0355_[2] ? _1170_ : _1169_;
+  assign _1260_ = _0355_[2] ? _1174_ : _1173_;
+  assign _1261_ = _0373_[0] ? cr_in[1] : cr_in[0];
+  assign _1262_ = _0373_[0] ? cr_in[5] : cr_in[4];
+  assign _1263_ = _0373_[0] ? cr_in[9] : cr_in[8];
+  assign _1264_ = _0373_[0] ? cr_in[13] : cr_in[12];
+  assign _1265_ = _0373_[0] ? cr_in[17] : cr_in[16];
+  assign _1266_ = _0373_[0] ? cr_in[21] : cr_in[20];
+  assign _1267_ = _0373_[0] ? cr_in[25] : cr_in[24];
+  assign _1268_ = _0373_[0] ? cr_in[29] : cr_in[28];
+  assign _1269_ = _0373_[2] ? _1181_ : _1180_;
+  assign _1270_ = _0373_[2] ? _1185_ : _1184_;
+  assign _1271_ = _0392_[0] ? cr_in[1] : cr_in[0];
+  assign _1272_ = _0392_[0] ? cr_in[5] : cr_in[4];
+  assign _1273_ = _0392_[0] ? cr_in[9] : cr_in[8];
+  assign _1274_ = _0392_[0] ? cr_in[13] : cr_in[12];
+  assign _1275_ = _0392_[0] ? cr_in[17] : cr_in[16];
+  assign _1276_ = _0392_[0] ? cr_in[21] : cr_in[20];
+  assign _1277_ = _0392_[0] ? cr_in[25] : cr_in[24];
+  assign _1278_ = _0392_[0] ? cr_in[29] : cr_in[28];
+  assign _1279_ = _0392_[2] ? _1192_ : _1191_;
+  assign _1280_ = _0392_[2] ? _1196_ : _1195_;
+  assign _1281_ = _0422_[0] ? cr_in[1] : cr_in[0];
+  assign _1282_ = _0422_[0] ? cr_in[5] : cr_in[4];
+  assign _1283_ = _0422_[0] ? cr_in[9] : cr_in[8];
+  assign _1284_ = _0422_[0] ? cr_in[13] : cr_in[12];
+  assign _1285_ = _0422_[0] ? cr_in[17] : cr_in[16];
+  assign _1286_ = _0422_[0] ? cr_in[21] : cr_in[20];
+  assign _1287_ = _0422_[0] ? cr_in[25] : cr_in[24];
+  assign _1288_ = _0422_[0] ? cr_in[29] : cr_in[28];
+  assign _1289_ = _0422_[2] ? _1203_ : _1202_;
+  assign _1290_ = _0422_[2] ? _1207_ : _1206_;
+  assign _1291_ = _0423_[0] ? cr_in[1] : cr_in[0];
+  assign _1292_ = _0423_[0] ? cr_in[5] : cr_in[4];
+  assign _1293_ = _0423_[0] ? cr_in[9] : cr_in[8];
+  assign _1294_ = _0423_[0] ? cr_in[13] : cr_in[12];
+  assign _1295_ = _0423_[0] ? cr_in[17] : cr_in[16];
+  assign _1296_ = _0423_[0] ? cr_in[21] : cr_in[20];
+  assign _1297_ = _0423_[0] ? cr_in[25] : cr_in[24];
+  assign _1298_ = _0423_[0] ? cr_in[29] : cr_in[28];
+  assign _1299_ = _0423_[2] ? _1214_ : _1213_;
+  assign _1300_ = _0423_[2] ? _1218_ : _1217_;
+  assign _1301_ = _0424_[0] ? e_in[341] : e_in[340];
+  assign _1302_ = _0424_[0] ? e_in[345] : e_in[344];
+  assign _1303_ = _0737_[0] ? cr_in[1] : cr_in[0];
+  assign _1304_ = _0737_[0] ? cr_in[5] : cr_in[4];
+  assign _1305_ = _0737_[0] ? cr_in[9] : cr_in[8];
+  assign _1306_ = _0737_[0] ? cr_in[13] : cr_in[12];
+  assign _1307_ = _0737_[0] ? cr_in[17] : cr_in[16];
+  assign _1308_ = _0737_[0] ? cr_in[21] : cr_in[20];
+  assign _1309_ = _0737_[0] ? cr_in[25] : cr_in[24];
+  assign _1310_ = _0737_[0] ? cr_in[29] : cr_in[28];
+  assign _1311_ = _0737_[2] ? _1230_ : _1229_;
+  assign _1312_ = _0737_[2] ? _1234_ : _1233_;
+  assign _1313_ = _0738_[0] ? cr_in[1] : cr_in[0];
+  assign _1314_ = _0738_[0] ? cr_in[5] : cr_in[4];
+  assign _1315_ = _0738_[0] ? cr_in[9] : cr_in[8];
+  assign _1316_ = _0738_[0] ? cr_in[13] : cr_in[12];
+  assign _1317_ = _0738_[0] ? cr_in[17] : cr_in[16];
+  assign _1318_ = _0738_[0] ? cr_in[21] : cr_in[20];
+  assign _1319_ = _0738_[0] ? cr_in[25] : cr_in[24];
+  assign _1320_ = _0738_[0] ? cr_in[29] : cr_in[28];
+  assign _1321_ = _0738_[2] ? _1241_ : _1240_;
+  assign _1322_ = _0738_[2] ? _1245_ : _1244_;
+  assign _1323_ = _0355_[0] ? cr_in[3] : cr_in[2];
+  assign _1324_ = _0355_[0] ? cr_in[7] : cr_in[6];
+  assign _1325_ = _0355_[0] ? cr_in[11] : cr_in[10];
+  assign _1326_ = _0355_[0] ? cr_in[15] : cr_in[14];
+  assign _1327_ = _0355_[0] ? cr_in[19] : cr_in[18];
+  assign _1328_ = _0355_[0] ? cr_in[23] : cr_in[22];
+  assign _1329_ = _0355_[0] ? cr_in[27] : cr_in[26];
+  assign _1330_ = _0355_[0] ? cr_in[31] : cr_in[30];
+  assign _1331_ = _0355_[2] ? _1172_ : _1171_;
+  assign _1332_ = _0355_[2] ? _1176_ : _1175_;
+  assign _1333_ = _0373_[0] ? cr_in[3] : cr_in[2];
+  assign _1334_ = _0373_[0] ? cr_in[7] : cr_in[6];
+  assign _1335_ = _0373_[0] ? cr_in[11] : cr_in[10];
+  assign _1336_ = _0373_[0] ? cr_in[15] : cr_in[14];
+  assign _1337_ = _0373_[0] ? cr_in[19] : cr_in[18];
+  assign _1338_ = _0373_[0] ? cr_in[23] : cr_in[22];
+  assign _1339_ = _0373_[0] ? cr_in[27] : cr_in[26];
+  assign _1340_ = _0373_[0] ? cr_in[31] : cr_in[30];
+  assign _1341_ = _0373_[2] ? _1183_ : _1182_;
+  assign _1342_ = _0373_[2] ? _1187_ : _1186_;
+  assign _1343_ = _0392_[0] ? cr_in[3] : cr_in[2];
+  assign _1344_ = _0392_[0] ? cr_in[7] : cr_in[6];
+  assign _1345_ = _0392_[0] ? cr_in[11] : cr_in[10];
+  assign _1346_ = _0392_[0] ? cr_in[15] : cr_in[14];
+  assign _1347_ = _0392_[0] ? cr_in[19] : cr_in[18];
+  assign _1348_ = _0392_[0] ? cr_in[23] : cr_in[22];
+  assign _1349_ = _0392_[0] ? cr_in[27] : cr_in[26];
+  assign _1350_ = _0392_[0] ? cr_in[31] : cr_in[30];
+  assign _1351_ = _0392_[2] ? _1194_ : _1193_;
+  assign _1352_ = _0392_[2] ? _1198_ : _1197_;
+  assign _1353_ = _0422_[0] ? cr_in[3] : cr_in[2];
+  assign _1354_ = _0422_[0] ? cr_in[7] : cr_in[6];
+  assign _1355_ = _0422_[0] ? cr_in[11] : cr_in[10];
+  assign _1356_ = _0422_[0] ? cr_in[15] : cr_in[14];
+  assign _1357_ = _0422_[0] ? cr_in[19] : cr_in[18];
+  assign _1358_ = _0422_[0] ? cr_in[23] : cr_in[22];
+  assign _1359_ = _0422_[0] ? cr_in[27] : cr_in[26];
+  assign _1360_ = _0422_[0] ? cr_in[31] : cr_in[30];
+  assign _1361_ = _0422_[2] ? _1205_ : _1204_;
+  assign _1362_ = _0422_[2] ? _1209_ : _1208_;
+  assign _1363_ = _0423_[0] ? cr_in[3] : cr_in[2];
+  assign _1364_ = _0423_[0] ? cr_in[7] : cr_in[6];
+  assign _1365_ = _0423_[0] ? cr_in[11] : cr_in[10];
+  assign _1366_ = _0423_[0] ? cr_in[15] : cr_in[14];
+  assign _1367_ = _0423_[0] ? cr_in[19] : cr_in[18];
+  assign _1368_ = _0423_[0] ? cr_in[23] : cr_in[22];
+  assign _1369_ = _0423_[0] ? cr_in[27] : cr_in[26];
+  assign _1370_ = _0423_[0] ? cr_in[31] : cr_in[30];
+  assign _1371_ = _0423_[2] ? _1216_ : _1215_;
+  assign _1372_ = _0423_[2] ? _1220_ : _1219_;
+  assign _1373_ = _0424_[0] ? e_in[343] : e_in[342];
+  assign _1374_ = _0424_[0] ? e_in[347] : e_in[346];
+  assign _1375_ = _0737_[0] ? cr_in[3] : cr_in[2];
+  assign _1376_ = _0737_[0] ? cr_in[7] : cr_in[6];
+  assign _1377_ = _0737_[0] ? cr_in[11] : cr_in[10];
+  assign _1378_ = _0737_[0] ? cr_in[15] : cr_in[14];
+  assign _1379_ = _0737_[0] ? cr_in[19] : cr_in[18];
+  assign _1380_ = _0737_[0] ? cr_in[23] : cr_in[22];
+  assign _1381_ = _0737_[0] ? cr_in[27] : cr_in[26];
+  assign _1382_ = _0737_[0] ? cr_in[31] : cr_in[30];
+  assign _1383_ = _0737_[2] ? _1232_ : _1231_;
+  assign _1384_ = _0737_[2] ? _1236_ : _1235_;
+  assign _1385_ = _0738_[0] ? cr_in[3] : cr_in[2];
+  assign _1386_ = _0738_[0] ? cr_in[7] : cr_in[6];
+  assign _1387_ = _0738_[0] ? cr_in[11] : cr_in[10];
+  assign _1388_ = _0738_[0] ? cr_in[15] : cr_in[14];
+  assign _1389_ = _0738_[0] ? cr_in[19] : cr_in[18];
+  assign _1390_ = _0738_[0] ? cr_in[23] : cr_in[22];
+  assign _1391_ = _0738_[0] ? cr_in[27] : cr_in[26];
+  assign _1392_ = _0738_[0] ? cr_in[31] : cr_in[30];
+  assign _1393_ = _0738_[2] ? _1243_ : _1242_;
+  assign _1394_ = _0738_[2] ? _1247_ : _1246_;
+  assign _1169_ = _0355_[1] ? _1323_ : _1251_;
+  assign _1170_ = _0355_[1] ? _1324_ : _1252_;
+  assign _1171_ = _0355_[1] ? _1325_ : _1253_;
+  assign _1172_ = _0355_[1] ? _1326_ : _1254_;
+  assign _1173_ = _0355_[1] ? _1327_ : _1255_;
+  assign _1174_ = _0355_[1] ? _1328_ : _1256_;
+  assign _1175_ = _0355_[1] ? _1329_ : _1257_;
+  assign _1176_ = _0355_[1] ? _1330_ : _1258_;
+  assign _1177_ = _0355_[3] ? _1331_ : _1259_;
+  assign _1178_ = _0355_[3] ? _1332_ : _1260_;
+  assign _1180_ = _0373_[1] ? _1333_ : _1261_;
+  assign _1181_ = _0373_[1] ? _1334_ : _1262_;
+  assign _1182_ = _0373_[1] ? _1335_ : _1263_;
+  assign _1183_ = _0373_[1] ? _1336_ : _1264_;
+  assign _1184_ = _0373_[1] ? _1337_ : _1265_;
+  assign _1185_ = _0373_[1] ? _1338_ : _1266_;
+  assign _1186_ = _0373_[1] ? _1339_ : _1267_;
+  assign _1187_ = _0373_[1] ? _1340_ : _1268_;
+  assign _1188_ = _0373_[3] ? _1341_ : _1269_;
+  assign _1189_ = _0373_[3] ? _1342_ : _1270_;
+  assign _1191_ = _0392_[1] ? _1343_ : _1271_;
+  assign _1192_ = _0392_[1] ? _1344_ : _1272_;
+  assign _1193_ = _0392_[1] ? _1345_ : _1273_;
+  assign _1194_ = _0392_[1] ? _1346_ : _1274_;
+  assign _1195_ = _0392_[1] ? _1347_ : _1275_;
+  assign _1196_ = _0392_[1] ? _1348_ : _1276_;
+  assign _1197_ = _0392_[1] ? _1349_ : _1277_;
+  assign _1198_ = _0392_[1] ? _1350_ : _1278_;
+  assign _1199_ = _0392_[3] ? _1351_ : _1279_;
+  assign _1200_ = _0392_[3] ? _1352_ : _1280_;
+  assign _1202_ = _0422_[1] ? _1353_ : _1281_;
+  assign _1203_ = _0422_[1] ? _1354_ : _1282_;
+  assign _1204_ = _0422_[1] ? _1355_ : _1283_;
+  assign _1205_ = _0422_[1] ? _1356_ : _1284_;
+  assign _1206_ = _0422_[1] ? _1357_ : _1285_;
+  assign _1207_ = _0422_[1] ? _1358_ : _1286_;
+  assign _1208_ = _0422_[1] ? _1359_ : _1287_;
+  assign _1209_ = _0422_[1] ? _1360_ : _1288_;
+  assign _1210_ = _0422_[3] ? _1361_ : _1289_;
+  assign _1211_ = _0422_[3] ? _1362_ : _1290_;
+  assign _1213_ = _0423_[1] ? _1363_ : _1291_;
+  assign _1214_ = _0423_[1] ? _1364_ : _1292_;
+  assign _1215_ = _0423_[1] ? _1365_ : _1293_;
+  assign _1216_ = _0423_[1] ? _1366_ : _1294_;
+  assign _1217_ = _0423_[1] ? _1367_ : _1295_;
+  assign _1218_ = _0423_[1] ? _1368_ : _1296_;
+  assign _1219_ = _0423_[1] ? _1369_ : _1297_;
+  assign _1220_ = _0423_[1] ? _1370_ : _1298_;
+  assign _1221_ = _0423_[3] ? _1371_ : _1299_;
+  assign _1222_ = _0423_[3] ? _1372_ : _1300_;
+  assign _1224_ = _0424_[1] ? _1373_ : _1301_;
+  assign _1225_ = _0424_[1] ? _1374_ : _1302_;
+  assign _1229_ = _0737_[1] ? _1375_ : _1303_;
+  assign _1230_ = _0737_[1] ? _1376_ : _1304_;
+  assign _1231_ = _0737_[1] ? _1377_ : _1305_;
+  assign _1232_ = _0737_[1] ? _1378_ : _1306_;
+  assign _1233_ = _0737_[1] ? _1379_ : _1307_;
+  assign _1234_ = _0737_[1] ? _1380_ : _1308_;
+  assign _1235_ = _0737_[1] ? _1381_ : _1309_;
+  assign _1236_ = _0737_[1] ? _1382_ : _1310_;
+  assign _1237_ = _0737_[3] ? _1383_ : _1311_;
+  assign _1238_ = _0737_[3] ? _1384_ : _1312_;
+  assign _1240_ = _0738_[1] ? _1385_ : _1313_;
+  assign _1241_ = _0738_[1] ? _1386_ : _1314_;
+  assign _1242_ = _0738_[1] ? _1387_ : _1315_;
+  assign _1243_ = _0738_[1] ? _1388_ : _1316_;
+  assign _1244_ = _0738_[1] ? _1389_ : _1317_;
+  assign _1245_ = _0738_[1] ? _1390_ : _1318_;
+  assign _1246_ = _0738_[1] ? _1391_ : _1319_;
+  assign _1247_ = _0738_[1] ? _1392_ : _1320_;
+  assign _1248_ = _0738_[3] ? _1393_ : _1321_;
+  assign _1249_ = _0738_[3] ? _1394_ : _1322_;
+  assign _0012_ = r[116] ? r[121:117] : e_in[326:322];
+  assign _0013_ = 1'h1 & e_in[321];
+  assign _0014_ = _0013_ & r[75];
+  assign _0015_ = r[76] ? r[87:84] : e_in[292:289];
+  assign _0016_ = r[77] ? r[91:88] : e_in[296:293];
+  assign _0017_ = r[78] ? r[95:92] : e_in[300:297];
+  assign _0018_ = r[79] ? r[99:96] : e_in[304:301];
+  assign _0019_ = r[80] ? r[103:100] : e_in[308:305];
+  assign _0020_ = r[81] ? r[107:104] : e_in[312:309];
+  assign _0021_ = r[82] ? r[111:108] : e_in[316:313];
+  assign _0022_ = r[83] ? r[115:112] : e_in[320:317];
+  assign cr_in = _0014_ ? { _0022_, _0021_, _0020_, _0019_, _0018_, _0017_, _0016_, _0015_ } : e_in[320:289];
+  assign _0023_ = ~ e_in[330];
+  assign _0024_ = ~ a_in;
+  assign _0025_ = _0023_ ? a_in : _0024_;
+  assign _0026_ = e_in[333:332] == 2'h0;
+  assign _0027_ = e_in[333:332] == 2'h1;
+  assign _0028_ = e_in[333:332] == 2'h2;
+  assign _0029_ = e_in[333:332] == 2'h3;
+  function [0:0] \10097 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \10097  = b[0:0];
+      4'b??1?:
+        \10097  = b[1:1];
+      4'b?1??:
+        \10097  = b[2:2];
+      4'b1???:
+        \10097  = b[3:3];
+      default:
+        \10097  = a;
+    endcase
+  endfunction
+  assign _0030_ = \10097 (1'hx, { 1'h1, _0012_[2], _0012_[0], 1'h0 }, { _0029_, _0028_, _0027_, _0026_ });
+  assign _0031_ = { 1'h0, _0025_ } + { 1'h0, b_in };
+  assign _0032_ = _0031_ + { 64'h0000000000000000, _0030_ };
+  assign _0033_ = e_in[337] ? a_in[31] : a_in[63];
+  assign _0034_ = e_in[337] ? b_in[31] : b_in[63];
+  assign _0035_ = e_in[338] ? _0033_ : 1'h0;
+  assign _0036_ = e_in[338] ? _0034_ : 1'h0;
+  assign _0037_ = ~ _0035_;
+  assign _0038_ = - $signed(a_in);
+  assign _0039_ = _0037_ ? a_in : _0038_;
+  assign _0040_ = ~ _0036_;
+  assign _0041_ = - $signed(b_in);
+  assign _0042_ = _0040_ ? b_in : _0041_;
+  assign _0043_ = e_in[8:3] == 6'h27;
+  assign _0044_ = _0043_ ? 1'h1 : 1'h0;
+  assign _0045_ = ~ e_in[365];
+  assign _0046_ = e_in[338] ? { c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63], c_in[63] } : 64'h0000000000000000;
+  assign _0047_ = _0045_ ? { _0046_, c_in } : 128'h00000000000000000000000000000000;
+  assign _0048_ = _0035_ ^ _0036_;
+  assign _0049_ = ~ _0047_;
+  assign _0050_ = _0048_ ? _0049_ : _0047_;
+  assign _0051_ = _0035_ ^ _0036_;
+  assign _0052_ = ~ _0044_;
+  assign _0053_ = _0036_ & _0052_;
+  assign _0054_ = _0035_ ^ _0053_;
+  assign _0055_ = ~ e_in[337];
+  assign _0056_ = e_in[8:3] == 6'h16;
+  assign _0057_ = _0056_ ? 1'h1 : 1'h0;
+  assign _0058_ = e_in[8:3] == 6'h16;
+  assign _0059_ = _0058_ ? { _0039_[31:0], 32'h00000000 } : { 32'h00000000, _0039_[31:0] };
+  assign _0060_ = _0055_ ? { _0042_, _0039_ } : { 32'h00000000, _0042_[31:0], 32'h00000000, _0039_[31:0] };
+  assign _0061_ = _0055_ ? { _0042_, _0039_ } : { 32'h00000000, _0042_[31:0], _0059_ };
+  assign _0062_ = _0055_ ? _0057_ : 1'h0;
+  assign _0063_ = ctrl[63:0] + 64'h0000000000000001;
+  assign _0064_ = ctrl[127:64] - 64'h0000000000000001;
+  assign _0065_ = ext_irq_in ? 64'h0000000000000500 : r[262:199];
+  assign _0066_ = ext_irq_in ? 1'h1 : 1'h0;
+  assign _0067_ = ctrl[127] ? 64'h0000000000000900 : _0065_;
+  assign _0068_ = ctrl[127] ? 1'h1 : _0066_;
+  assign _0069_ = ctrl[143] ? _0067_ : r[262:199];
+  assign _0070_ = ctrl[143] ? _0068_ : 1'h0;
+  assign _0071_ = ~ ctrl[142];
+  assign _0072_ = ~ ctrl[128];
+  assign _0073_ = ~ ctrl[191];
+  assign _0074_ = e_in[72:9] + 64'h0000000000000004;
+  assign _0075_ = e_in[8:3] == 6'h38;
+  assign right_shift = _0075_ ? 1'h1 : 1'h0;
+  assign _0076_ = e_in[8:3] == 6'h32;
+  assign _0077_ = e_in[8:3] == 6'h33;
+  assign _0078_ = _0076_ | _0077_;
+  assign rot_clear_left = _0078_ ? 1'h1 : 1'h0;
+  assign _0079_ = e_in[8:3] == 6'h32;
+  assign _0080_ = e_in[8:3] == 6'h34;
+  assign _0081_ = _0079_ | _0080_;
+  assign rot_clear_right = _0081_ ? 1'h1 : 1'h0;
+  assign _0082_ = e_in[8:3] == 6'h18;
+  assign rot_sign_ext = _0082_ ? 1'h1 : 1'h0;
+  assign _0083_ = valid_in ? e_in[72:9] : r[423:360];
+  assign _0084_ = valid_in ? e_in[72:9] : r[423:360];
+  assign _0085_ = ~ ctrl[191];
+  assign _0086_ = valid_in & ctrl[138];
+  assign _0087_ = valid_in ? e_in[8:3] : r[272:267];
+  assign _0088_ = ctrl[256] == 1'h1;
+  assign _0089_ = 1'h0 | r[266];
+  assign _0090_ = valid_in & _0089_;
+  assign _0091_ = r[272:267] == 6'h1f;
+  assign _0092_ = r[272:267] == 6'h1b;
+  assign _0093_ = _0091_ | _0092_;
+  assign _0094_ = r[272:267] == 6'h1c;
+  assign _0095_ = _0093_ | _0094_;
+  assign _0096_ = r[272:267] == 6'h12;
+  assign _0097_ = _0095_ | _0096_;
+  assign _0098_ = r[272:267] == 6'h11;
+  assign _0099_ = _0097_ | _0098_;
+  assign _0100_ = r[272:267] == 6'h10;
+  assign _0101_ = _0099_ | _0100_;
+  assign _0102_ = r[272:267] == 6'h20;
+  assign _0103_ = r[272:267] == 6'h14;
+  assign _0104_ = _0102_ | _0103_;
+  assign _0105_ = r[272:267] == 6'h13;
+  assign _0106_ = _0104_ | _0105_;
+  assign _0107_ = _0106_ ? 1'h1 : 1'h0;
+  assign _0108_ = _0101_ ? 1'h0 : _0107_;
+  assign _0109_ = _0101_ ? 1'h1 : 1'h0;
+  assign _0110_ = _0070_ & valid_in;
+  assign _0111_ = valid_in & ctrl[142];
+  assign _0112_ = 6'h3f - e_in[8:3];
+  assign _0113_ = _1168_ == 1'h1;
+  assign _0114_ = e_in[8:3] == 6'h26;
+  assign _0115_ = e_in[8:3] == 6'h2a;
+  assign _0116_ = _0114_ | _0115_;
+  assign _0117_ = _0116_ ? e_in[359] : 1'h0;
+  assign _0118_ = _0113_ ? 1'h1 : _0117_;
+  assign _0119_ = _0111_ & _0118_;
+  assign _0120_ = 1'h1 & valid_in;
+  assign _0121_ = e_in[8:3] == 6'h21;
+  assign _0122_ = e_in[8:3] == 6'h22;
+  assign _0123_ = _0121_ | _0122_;
+  assign _0124_ = _0120_ & _0123_;
+  assign _0125_ = e_in[2:1] == 2'h1;
+  assign _0126_ = valid_in & _0125_;
+  assign _0127_ = e_in[8:3] == 6'h00;
+  assign _0128_ = e_in[340] ? 64'h0000000000000c00 : _0069_;
+  assign _0129_ = e_in[340] ? 1'h1 : 1'h0;
+  assign _0130_ = e_in[340] ? 1'h1 : 1'h0;
+  assign _0131_ = e_in[340] ? 1'h0 : 1'h1;
+  assign _0132_ = e_in[8:3] == 6'h35;
+  assign _0133_ = e_in[349:340] == 10'h100;
+  assign _0134_ = _0133_ ? 1'h1 : 1'h0;
+  assign _0135_ = _0133_ ? 1'h0 : 1'h1;
+  assign _0136_ = e_in[8:3] == 6'h04;
+  assign _0137_ = e_in[8:3] == 6'h01;
+  assign _0138_ = e_in[8:3] == 6'h10;
+  assign _0139_ = _0137_ | _0138_;
+  assign _0140_ = e_in[8:3] == 6'h11;
+  assign _0141_ = _0139_ | _0140_;
+  assign _0142_ = e_in[8:3] == 6'h12;
+  assign _0143_ = _0141_ | _0142_;
+  assign _0144_ = e_in[8:3] == 6'h13;
+  assign _0145_ = _0143_ | _0144_;
+  assign _0146_ = e_in[8:3] == 6'h1c;
+  assign _0147_ = _0145_ | _0146_;
+  assign _0148_ = _0032_[32] ^ _0025_[32];
+  assign _0149_ = _0148_ ^ b_in[32];
+  assign _0150_ = e_in[8:3] == 6'h02;
+  assign _0151_ = e_in[333:332] != 2'h2;
+  assign _0152_ = _0151_ ? { 105'h000000000000000000000000000, e_in[79:73], 1'h0, _0085_, 2'h1 } : { 105'h000000000000000000000000000, e_in[79:73], 1'h0, _0085_, 2'h1 };
+  assign _0153_ = _0151_ ? 1'h1 : 1'h1;
+  assign _0154_ = r[116] ? r[118:117] : e_in[323:322];
+  assign _0155_ = _0151_ ? { _0149_, _0032_[64] } : _0154_;
+  assign _0156_ = _0151_ ? _0012_[3:2] : { _0149_, _0032_[64] };
+  assign _0157_ = r[116] ? r[121] : e_in[326];
+  assign _0158_ = _0151_ ? { _0083_, 8'h44, _0012_[4] } : { _0083_, 8'h44, _0157_ };
+  assign _0159_ = e_in[334] ? { _0158_, _0156_, _0155_, _0153_, _0152_ } : { _0083_, 8'h44, _0012_, 106'h000000000000000000000000000, e_in[79:73], 1'h0, _0085_, 2'h1 };
+  assign _0160_ = _0032_[64] ^ _0032_[63];
+  assign _0161_ = _0025_[63] ^ b_in[63];
+  assign _0162_ = ~ _0161_;
+  assign _0163_ = _0160_ & _0162_;
+  assign _0164_ = _0149_ ^ _0032_[31];
+  assign _0165_ = _0025_[31] ^ b_in[31];
+  assign _0166_ = ~ _0165_;
+  assign _0167_ = _0164_ & _0166_;
+  assign _0168_ = _0163_ ? 1'h1 : _0159_[121];
+  assign _0169_ = e_in[329] ? { _0159_[193:122], _0168_, _0167_, _0163_, _0159_[118:117], 1'h1, _0159_[115:0] } : _0159_;
+  assign _0170_ = e_in[8:3] == 6'h09;
+  assign _0171_ = ~ e_in[337];
+  assign _0172_ = _0170_ ? e_in[360] : _0171_;
+  assign _0173_ = a_in[31:0] ^ b_in[31:0];
+  assign _0174_ = | _0173_;
+  assign _0175_ = ~ _0174_;
+  assign _0176_ = a_in[63:32] ^ b_in[63:32];
+  assign _0177_ = | _0176_;
+  assign _0178_ = ~ _0177_;
+  assign _0179_ = ~ _0172_;
+  assign _0180_ = _0179_ | _0178_;
+  assign _0181_ = _0175_ & _0180_;
+  assign _0182_ = _0172_ ? a_in[63] : a_in[31];
+  assign _0183_ = _0172_ ? b_in[63] : b_in[31];
+  assign _0184_ = _0182_ != _0183_;
+  assign _0185_ = ~ _0172_;
+  assign _0186_ = _0185_ & _0149_;
+  assign _0187_ = _0172_ & _0032_[64];
+  assign _0188_ = _0186_ | _0187_;
+  assign _0189_ = ~ _0188_;
+  assign _0190_ = ~ _0188_;
+  assign _0191_ = _0184_ ? { _0182_, _0183_, 1'h0, _0183_, _0182_ } : { _0188_, _0189_, 1'h0, _0188_, _0190_ };
+  assign _0192_ = _0181_ ? 5'h04 : _0191_;
+  assign _0193_ = e_in[8:3] == 6'h09;
+  assign _0194_ = e_in[338] ? { _0192_[4:2], _0012_[4] } : { _0192_[1:0], _0192_[2], _0012_[4] };
+  assign _0195_ = e_in[364:362] == 3'h0;
+  assign _0196_ = e_in[364:362] == 3'h1;
+  assign _0197_ = e_in[364:362] == 3'h2;
+  assign _0198_ = e_in[364:362] == 3'h3;
+  assign _0199_ = e_in[364:362] == 3'h4;
+  assign _0200_ = e_in[364:362] == 3'h5;
+  assign _0201_ = e_in[364:362] == 3'h6;
+  assign _0202_ = e_in[364:362] == 3'h7;
+  function [7:0] \10795 ;
+    input [7:0] a;
+    input [63:0] b;
+    input [7:0] s;
+    (* parallel_case *)
+    casez (s)
+      8'b???????1:
+        \10795  = b[7:0];
+      8'b??????1?:
+        \10795  = b[15:8];
+      8'b?????1??:
+        \10795  = b[23:16];
+      8'b????1???:
+        \10795  = b[31:24];
+      8'b???1????:
+        \10795  = b[39:32];
+      8'b??1?????:
+        \10795  = b[47:40];
+      8'b?1??????:
+        \10795  = b[55:48];
+      8'b1???????:
+        \10795  = b[63:56];
+      default:
+        \10795  = a;
+    endcase
+  endfunction
+  assign _0203_ = \10795 (8'h00, 64'h0102040810204080, { _0202_, _0201_, _0200_, _0199_, _0198_, _0197_, _0196_, _0195_ });
+  assign _0204_ = _0192_ & e_in[364:360];
+  assign _0205_ = | _0204_;
+  assign _0206_ = _0205_ ? 1'h1 : 1'h0;
+  assign _0207_ = _0193_ ? 1'h0 : 1'h1;
+  assign _0208_ = _0193_ ? { _0194_, _0194_, _0194_, _0194_, _0194_, _0194_, _0194_, _0194_, _0203_, 1'h1 } : 41'h00000000000;
+  assign _0209_ = _0193_ ? _0069_ : 64'h0000000000000700;
+  assign _0210_ = _0193_ ? 1'h0 : _0206_;
+  assign _0211_ = _0150_ ? 1'h0 : _0207_;
+  assign _0212_ = _0150_ ? _0169_[74:0] : { 64'h0000000000000000, e_in[79:73], 1'h0, _0085_, 2'h1 };
+  assign _0213_ = _0150_ ? _0169_[115:75] : _0208_;
+  assign _0214_ = _0150_ ? _0169_[193:116] : { _0083_, 8'h44, _0012_, 1'h0 };
+  assign _0215_ = _0150_ ? _0069_ : _0209_;
+  assign _0216_ = _0150_ ? 1'h1 : 1'h0;
+  assign _0217_ = _0150_ ? 1'h0 : _0210_;
+  assign _0218_ = e_in[8:3] == 6'h02;
+  assign _0219_ = e_in[8:3] == 6'h09;
+  assign _0220_ = _0218_ | _0219_;
+  assign _0221_ = e_in[8:3] == 6'h3b;
+  assign _0222_ = _0220_ | _0221_;
+  assign _0223_ = a_in[4] ^ b_in[4];
+  assign _0224_ = _0223_ ^ _0032_[4];
+  assign _0225_ = ~ _0224_;
+  assign _0226_ = _0225_ ? 4'h6 : 4'h0;
+  assign _0227_ = a_in[8] ^ b_in[8];
+  assign _0228_ = _0227_ ^ _0032_[8];
+  assign _0229_ = ~ _0228_;
+  assign _0230_ = _0229_ ? 4'h6 : 4'h0;
+  assign _0231_ = a_in[12] ^ b_in[12];
+  assign _0232_ = _0231_ ^ _0032_[12];
+  assign _0233_ = ~ _0232_;
+  assign _0234_ = _0233_ ? 4'h6 : 4'h0;
+  assign _0235_ = a_in[16] ^ b_in[16];
+  assign _0236_ = _0235_ ^ _0032_[16];
+  assign _0237_ = ~ _0236_;
+  assign _0238_ = _0237_ ? 4'h6 : 4'h0;
+  assign _0239_ = a_in[20] ^ b_in[20];
+  assign _0240_ = _0239_ ^ _0032_[20];
+  assign _0241_ = ~ _0240_;
+  assign _0242_ = _0241_ ? 4'h6 : 4'h0;
+  assign _0243_ = a_in[24] ^ b_in[24];
+  assign _0244_ = _0243_ ^ _0032_[24];
+  assign _0245_ = ~ _0244_;
+  assign _0246_ = _0245_ ? 4'h6 : 4'h0;
+  assign _0247_ = a_in[28] ^ b_in[28];
+  assign _0248_ = _0247_ ^ _0032_[28];
+  assign _0249_ = ~ _0248_;
+  assign _0250_ = _0249_ ? 4'h6 : 4'h0;
+  assign _0251_ = a_in[32] ^ b_in[32];
+  assign _0252_ = _0251_ ^ _0032_[32];
+  assign _0253_ = ~ _0252_;
+  assign _0254_ = _0253_ ? 4'h6 : 4'h0;
+  assign _0255_ = a_in[36] ^ b_in[36];
+  assign _0256_ = _0255_ ^ _0032_[36];
+  assign _0257_ = ~ _0256_;
+  assign _0258_ = _0257_ ? 4'h6 : 4'h0;
+  assign _0259_ = a_in[40] ^ b_in[40];
+  assign _0260_ = _0259_ ^ _0032_[40];
+  assign _0261_ = ~ _0260_;
+  assign _0262_ = _0261_ ? 4'h6 : 4'h0;
+  assign _0263_ = a_in[44] ^ b_in[44];
+  assign _0264_ = _0263_ ^ _0032_[44];
+  assign _0265_ = ~ _0264_;
+  assign _0266_ = _0265_ ? 4'h6 : 4'h0;
+  assign _0267_ = a_in[48] ^ b_in[48];
+  assign _0268_ = _0267_ ^ _0032_[48];
+  assign _0269_ = ~ _0268_;
+  assign _0270_ = _0269_ ? 4'h6 : 4'h0;
+  assign _0271_ = a_in[52] ^ b_in[52];
+  assign _0272_ = _0271_ ^ _0032_[52];
+  assign _0273_ = ~ _0272_;
+  assign _0274_ = _0273_ ? 4'h6 : 4'h0;
+  assign _0275_ = a_in[56] ^ b_in[56];
+  assign _0276_ = _0275_ ^ _0032_[56];
+  assign _0277_ = ~ _0276_;
+  assign _0278_ = _0277_ ? 4'h6 : 4'h0;
+  assign _0279_ = a_in[60] ^ b_in[60];
+  assign _0280_ = _0279_ ^ _0032_[60];
+  assign _0281_ = ~ _0280_;
+  assign _0282_ = _0281_ ? 4'h6 : 4'h0;
+  assign _0283_ = ~ _0032_[64];
+  assign _0284_ = _0283_ ? 4'h6 : 4'h0;
+  assign _0285_ = e_in[8:3] == 6'h3e;
+  assign _0286_ = a_in[7:0] >= b_in[7:0];
+  assign _0287_ = a_in[7:0] <= b_in[15:8];
+  assign _0288_ = _0286_ & _0287_;
+  assign _0289_ = a_in[7:0] >= b_in[23:16];
+  assign _0290_ = e_in[360] & _0289_;
+  assign _0291_ = a_in[7:0] <= b_in[31:24];
+  assign _0292_ = _0290_ & _0291_;
+  assign _0293_ = _0292_ ? 1'h1 : 1'h0;
+  assign _0294_ = _0288_ ? 1'h1 : _0293_;
+  assign _0295_ = e_in[364:362] == 3'h0;
+  assign _0296_ = e_in[364:362] == 3'h1;
+  assign _0297_ = e_in[364:362] == 3'h2;
+  assign _0298_ = e_in[364:362] == 3'h3;
+  assign _0299_ = e_in[364:362] == 3'h4;
+  assign _0300_ = e_in[364:362] == 3'h5;
+  assign _0301_ = e_in[364:362] == 3'h6;
+  assign _0302_ = e_in[364:362] == 3'h7;
+  function [7:0] \11101 ;
+    input [7:0] a;
+    input [63:0] b;
+    input [7:0] s;
+    (* parallel_case *)
+    casez (s)
+      8'b???????1:
+        \11101  = b[7:0];
+      8'b??????1?:
+        \11101  = b[15:8];
+      8'b?????1??:
+        \11101  = b[23:16];
+      8'b????1???:
+        \11101  = b[31:24];
+      8'b???1????:
+        \11101  = b[39:32];
+      8'b??1?????:
+        \11101  = b[47:40];
+      8'b?1??????:
+        \11101  = b[55:48];
+      8'b1???????:
+        \11101  = b[63:56];
+      default:
+        \11101  = a;
+    endcase
+  endfunction
+  assign _0303_ = \11101 (8'h00, 64'h0102040810204080, { _0302_, _0301_, _0300_, _0299_, _0298_, _0297_, _0296_, _0295_ });
+  assign _0304_ = e_in[8:3] == 6'h0c;
+  assign _0305_ = a_in[7:0] == b_in[7:0];
+  assign _0306_ = _0305_ ? 1'h1 : 1'h0;
+  assign _0307_ = a_in[7:0] == b_in[15:8];
+  assign _0308_ = _0307_ ? 1'h1 : _0306_;
+  assign _0309_ = a_in[7:0] == b_in[23:16];
+  assign _0310_ = _0309_ ? 1'h1 : _0308_;
+  assign _0311_ = a_in[7:0] == b_in[31:24];
+  assign _0312_ = _0311_ ? 1'h1 : _0310_;
+  assign _0313_ = a_in[7:0] == b_in[39:32];
+  assign _0314_ = _0313_ ? 1'h1 : _0312_;
+  assign _0315_ = a_in[7:0] == b_in[47:40];
+  assign _0316_ = _0315_ ? 1'h1 : _0314_;
+  assign _0317_ = a_in[7:0] == b_in[55:48];
+  assign _0318_ = _0317_ ? 1'h1 : _0316_;
+  assign _0319_ = a_in[7:0] == b_in[63:56];
+  assign _0320_ = _0319_ ? 1'h1 : _0318_;
+  assign _0321_ = e_in[364:362] == 3'h0;
+  assign _0322_ = e_in[364:362] == 3'h1;
+  assign _0323_ = e_in[364:362] == 3'h2;
+  assign _0324_ = e_in[364:362] == 3'h3;
+  assign _0325_ = e_in[364:362] == 3'h4;
+  assign _0326_ = e_in[364:362] == 3'h5;
+  assign _0327_ = e_in[364:362] == 3'h6;
+  assign _0328_ = e_in[364:362] == 3'h7;
+  function [7:0] \11204 ;
+    input [7:0] a;
+    input [63:0] b;
+    input [7:0] s;
+    (* parallel_case *)
+    casez (s)
+      8'b???????1:
+        \11204  = b[7:0];
+      8'b??????1?:
+        \11204  = b[15:8];
+      8'b?????1??:
+        \11204  = b[23:16];
+      8'b????1???:
+        \11204  = b[31:24];
+      8'b???1????:
+        \11204  = b[39:32];
+      8'b??1?????:
+        \11204  = b[47:40];
+      8'b?1??????:
+        \11204  = b[55:48];
+      8'b1???????:
+        \11204  = b[63:56];
+      default:
+        \11204  = a;
+    endcase
+  endfunction
+  assign _0329_ = \11204 (8'h00, 64'h0102040810204080, { _0328_, _0327_, _0326_, _0325_, _0324_, _0323_, _0322_, _0321_ });
+  assign _0330_ = e_in[8:3] == 6'h0b;
+  assign _0331_ = e_in[8:3] == 6'h03;
+  assign _0332_ = e_in[8:3] == 6'h2e;
+  assign _0333_ = _0331_ | _0332_;
+  assign _0334_ = e_in[8:3] == 6'h3c;
+  assign _0335_ = _0333_ | _0334_;
+  assign _0336_ = e_in[8:3] == 6'h2f;
+  assign _0337_ = _0335_ | _0336_;
+  assign _0338_ = e_in[8:3] == 6'h30;
+  assign _0339_ = _0337_ | _0338_;
+  assign _0340_ = e_in[8:3] == 6'h0a;
+  assign _0341_ = _0339_ | _0340_;
+  assign _0342_ = e_in[8:3] == 6'h17;
+  assign _0343_ = _0341_ | _0342_;
+  assign _0344_ = e_in[8:3] == 6'h08;
+  assign _0345_ = _0343_ | _0344_;
+  assign _0346_ = e_in[8:3] == 6'h3d;
+  assign _0347_ = _0345_ | _0346_;
+  assign _0348_ = ctrl[137] ? 1'h1 : _0086_;
+  assign _0349_ = e_in[8:3] == 6'h05;
+  assign _0350_ = ~ e_in[362];
+  assign _0351_ = a_in - 64'h0000000000000001;
+  assign _0352_ = _0350_ ? 7'h21 : e_in[79:73];
+  assign _0353_ = _0350_ ? _0351_ : 64'h0000000000000000;
+  assign _0354_ = _0350_ ? 1'h1 : 1'h0;
+  assign _0355_ = 32'd31 - { 27'h0000000, e_in[359:355] };
+  assign _0356_ = _1179_ == e_in[363];
+  assign _0357_ = _0356_ ? 1'h1 : 1'h0;
+  assign _0358_ = a_in != 64'h0000000000000001;
+  assign _0359_ = _0358_ ? 1'h1 : 1'h0;
+  assign _0360_ = _0359_ ^ e_in[361];
+  assign _0361_ = e_in[362] | _0360_;
+  assign _0362_ = e_in[364] | _0357_;
+  assign _0363_ = _0361_ & _0362_;
+  assign _0364_ = ctrl[137] ? 1'h1 : _0086_;
+  assign _0365_ = e_in[8:3] == 6'h06;
+  assign _0366_ = ~ e_in[362];
+  assign _0367_ = ~ e_in[349];
+  assign _0368_ = _0366_ & _0367_;
+  assign _0369_ = a_in - 64'h0000000000000001;
+  assign _0370_ = _0368_ ? 7'h21 : e_in[79:73];
+  assign _0371_ = _0368_ ? _0369_ : 64'h0000000000000000;
+  assign _0372_ = _0368_ ? 1'h1 : 1'h0;
+  assign _0373_ = 32'd31 - { 27'h0000000, e_in[359:355] };
+  assign _0374_ = _1190_ == e_in[363];
+  assign _0375_ = _0374_ ? 1'h1 : 1'h0;
+  assign _0376_ = a_in != 64'h0000000000000001;
+  assign _0377_ = _0376_ ? 1'h1 : 1'h0;
+  assign _0378_ = _0377_ ^ e_in[361];
+  assign _0379_ = e_in[362] | _0378_;
+  assign _0380_ = e_in[364] | _0375_;
+  assign _0381_ = _0379_ & _0380_;
+  assign _0382_ = ctrl[137] ? 1'h1 : _0086_;
+  assign _0383_ = e_in[8:3] == 6'h07;
+  assign _0384_ = a_in[5] | a_in[14];
+  assign _0385_ = ~ a_in[14];
+  assign _0386_ = ~ a_in[0];
+  assign _0387_ = ~ a_in[63];
+  assign _0388_ = a_in[14] ? 2'h3 : a_in[5:4];
+  assign _0389_ = a_in[14] ? 1'h1 : a_in[15];
+  assign _0390_ = e_in[8:3] == 6'h31;
+  assign _0391_ = e_in[8:3] == 6'h0d;
+  assign _0392_ = 32'd31 - { 27'h0000000, e_in[349:345] };
+  assign _0393_ = _1201_ ? a_in : b_in;
+  assign _0394_ = e_in[8:3] == 6'h1d;
+  assign _0395_ = ~ e_in[340];
+  assign _0396_ = e_in[364:362] == 3'h0;
+  assign _0397_ = e_in[364:362] == 3'h1;
+  assign _0398_ = e_in[364:362] == 3'h2;
+  assign _0399_ = e_in[364:362] == 3'h3;
+  assign _0400_ = e_in[364:362] == 3'h4;
+  assign _0401_ = e_in[364:362] == 3'h5;
+  assign _0402_ = e_in[364:362] == 3'h6;
+  assign _0403_ = e_in[364:362] == 3'h7;
+  function [7:0] \11507 ;
+    input [7:0] a;
+    input [63:0] b;
+    input [7:0] s;
+    (* parallel_case *)
+    casez (s)
+      8'b???????1:
+        \11507  = b[7:0];
+      8'b??????1?:
+        \11507  = b[15:8];
+      8'b?????1??:
+        \11507  = b[23:16];
+      8'b????1???:
+        \11507  = b[31:24];
+      8'b???1????:
+        \11507  = b[39:32];
+      8'b??1?????:
+        \11507  = b[47:40];
+      8'b?1??????:
+        \11507  = b[55:48];
+      8'b1???????:
+        \11507  = b[63:56];
+      default:
+        \11507  = a;
+    endcase
+  endfunction
+  assign _0404_ = \11507 (8'h00, 64'h0102040810204080, { _0403_, _0402_, _0401_, _0400_, _0399_, _0398_, _0397_, _0396_ });
+  assign _0405_ = 32'd0 == { 29'h00000000, e_in[359:357] };
+  assign _0406_ = _0405_ ? cr_in[31:28] : 4'h0;
+  assign _0407_ = 32'd1 == { 29'h00000000, e_in[359:357] };
+  assign _0408_ = _0407_ ? cr_in[27:24] : _0406_;
+  assign _0409_ = 32'd2 == { 29'h00000000, e_in[359:357] };
+  assign _0410_ = _0409_ ? cr_in[23:20] : _0408_;
+  assign _0411_ = 32'd3 == { 29'h00000000, e_in[359:357] };
+  assign _0412_ = _0411_ ? cr_in[19:16] : _0410_;
+  assign _0413_ = 32'd4 == { 29'h00000000, e_in[359:357] };
+  assign _0414_ = _0413_ ? cr_in[15:12] : _0412_;
+  assign _0415_ = 32'd5 == { 29'h00000000, e_in[359:357] };
+  assign _0416_ = _0415_ ? cr_in[11:8] : _0414_;
+  assign _0417_ = 32'd6 == { 29'h00000000, e_in[359:357] };
+  assign _0418_ = _0417_ ? cr_in[7:4] : _0416_;
+  assign _0419_ = 32'd7 == { 29'h00000000, e_in[359:357] };
+  assign _0420_ = _0419_ ? cr_in[3:0] : _0418_;
+  assign _0421_ = 32'd31 - { 27'h0000000, e_in[364:360] };
+  assign _0422_ = 32'd31 - { 27'h0000000, e_in[359:355] };
+  assign _0423_ = 32'd31 - { 27'h0000000, e_in[354:350] };
+  assign _0424_ = 32'd5 + { 30'h00000000, _1212_, _1223_ };
+  assign _0425_ = 32'd31 - { 27'h0000000, _0421_[4:0] };
+  assign _0426_ = $signed(_0425_) / $signed(32'd4);
+  assign _0427_ = _0426_[2:0] == 3'h0;
+  assign _0428_ = _0426_[2:0] == 3'h1;
+  assign _0429_ = _0426_[2:0] == 3'h2;
+  assign _0430_ = _0426_[2:0] == 3'h3;
+  assign _0431_ = _0426_[2:0] == 3'h4;
+  assign _0432_ = _0426_[2:0] == 3'h5;
+  assign _0433_ = _0426_[2:0] == 3'h6;
+  assign _0434_ = _0426_[2:0] == 3'h7;
+  function [7:0] \11635 ;
+    input [7:0] a;
+    input [63:0] b;
+    input [7:0] s;
+    (* parallel_case *)
+    casez (s)
+      8'b???????1:
+        \11635  = b[7:0];
+      8'b??????1?:
+        \11635  = b[15:8];
+      8'b?????1??:
+        \11635  = b[23:16];
+      8'b????1???:
+        \11635  = b[31:24];
+      8'b???1????:
+        \11635  = b[39:32];
+      8'b??1?????:
+        \11635  = b[47:40];
+      8'b?1??????:
+        \11635  = b[55:48];
+      8'b1???????:
+        \11635  = b[63:56];
+      default:
+        \11635  = a;
+    endcase
+  endfunction
+  assign _0435_ = \11635 (8'h00, 64'h0102040810204080, { _0434_, _0433_, _0432_, _0431_, _0430_, _0429_, _0428_, _0427_ });
+  assign _0436_ = 32'd0 == { 27'h0000000, _0421_[4:0] };
+  assign _0437_ = _0436_ ? _1228_ : cr_in[0];
+  assign _0438_ = 32'd1 == { 27'h0000000, _0421_[4:0] };
+  assign _0439_ = _0438_ ? _1228_ : cr_in[1];
+  assign _0440_ = 32'd2 == { 27'h0000000, _0421_[4:0] };
+  assign _0441_ = _0440_ ? _1228_ : cr_in[2];
+  assign _0442_ = 32'd3 == { 27'h0000000, _0421_[4:0] };
+  assign _0443_ = _0442_ ? _1228_ : cr_in[3];
+  assign _0444_ = 32'd4 == { 27'h0000000, _0421_[4:0] };
+  assign _0445_ = _0444_ ? _1228_ : cr_in[4];
+  assign _0446_ = 32'd5 == { 27'h0000000, _0421_[4:0] };
+  assign _0447_ = _0446_ ? _1228_ : cr_in[5];
+  assign _0448_ = 32'd6 == { 27'h0000000, _0421_[4:0] };
+  assign _0449_ = _0448_ ? _1228_ : cr_in[6];
+  assign _0450_ = 32'd7 == { 27'h0000000, _0421_[4:0] };
+  assign _0451_ = _0450_ ? _1228_ : cr_in[7];
+  assign _0452_ = 32'd8 == { 27'h0000000, _0421_[4:0] };
+  assign _0453_ = _0452_ ? _1228_ : cr_in[8];
+  assign _0454_ = 32'd9 == { 27'h0000000, _0421_[4:0] };
+  assign _0455_ = _0454_ ? _1228_ : cr_in[9];
+  assign _0456_ = 32'd10 == { 27'h0000000, _0421_[4:0] };
+  assign _0457_ = _0456_ ? _1228_ : cr_in[10];
+  assign _0458_ = 32'd11 == { 27'h0000000, _0421_[4:0] };
+  assign _0459_ = _0458_ ? _1228_ : cr_in[11];
+  assign _0460_ = 32'd12 == { 27'h0000000, _0421_[4:0] };
+  assign _0461_ = _0460_ ? _1228_ : cr_in[12];
+  assign _0462_ = 32'd13 == { 27'h0000000, _0421_[4:0] };
+  assign _0463_ = _0462_ ? _1228_ : cr_in[13];
+  assign _0464_ = 32'd14 == { 27'h0000000, _0421_[4:0] };
+  assign _0465_ = _0464_ ? _1228_ : cr_in[14];
+  assign _0466_ = 32'd15 == { 27'h0000000, _0421_[4:0] };
+  assign _0467_ = _0466_ ? _1228_ : cr_in[15];
+  assign _0468_ = 32'd16 == { 27'h0000000, _0421_[4:0] };
+  assign _0469_ = _0468_ ? _1228_ : cr_in[16];
+  assign _0470_ = 32'd17 == { 27'h0000000, _0421_[4:0] };
+  assign _0471_ = _0470_ ? _1228_ : cr_in[17];
+  assign _0472_ = 32'd18 == { 27'h0000000, _0421_[4:0] };
+  assign _0473_ = _0472_ ? _1228_ : cr_in[18];
+  assign _0474_ = 32'd19 == { 27'h0000000, _0421_[4:0] };
+  assign _0475_ = _0474_ ? _1228_ : cr_in[19];
+  assign _0476_ = 32'd20 == { 27'h0000000, _0421_[4:0] };
+  assign _0477_ = _0476_ ? _1228_ : cr_in[20];
+  assign _0478_ = 32'd21 == { 27'h0000000, _0421_[4:0] };
+  assign _0479_ = _0478_ ? _1228_ : cr_in[21];
+  assign _0480_ = 32'd22 == { 27'h0000000, _0421_[4:0] };
+  assign _0481_ = _0480_ ? _1228_ : cr_in[22];
+  assign _0482_ = 32'd23 == { 27'h0000000, _0421_[4:0] };
+  assign _0483_ = _0482_ ? _1228_ : cr_in[23];
+  assign _0484_ = 32'd24 == { 27'h0000000, _0421_[4:0] };
+  assign _0485_ = _0484_ ? _1228_ : cr_in[24];
+  assign _0486_ = 32'd25 == { 27'h0000000, _0421_[4:0] };
+  assign _0487_ = _0486_ ? _1228_ : cr_in[25];
+  assign _0488_ = 32'd26 == { 27'h0000000, _0421_[4:0] };
+  assign _0489_ = _0488_ ? _1228_ : cr_in[26];
+  assign _0490_ = 32'd27 == { 27'h0000000, _0421_[4:0] };
+  assign _0491_ = _0490_ ? _1228_ : cr_in[27];
+  assign _0492_ = 32'd28 == { 27'h0000000, _0421_[4:0] };
+  assign _0493_ = _0492_ ? _1228_ : cr_in[28];
+  assign _0494_ = 32'd29 == { 27'h0000000, _0421_[4:0] };
+  assign _0495_ = _0494_ ? _1228_ : cr_in[29];
+  assign _0496_ = 32'd30 == { 27'h0000000, _0421_[4:0] };
+  assign _0497_ = _0496_ ? _1228_ : cr_in[30];
+  assign _0498_ = 32'd31 == { 27'h0000000, _0421_[4:0] };
+  assign _0499_ = _0498_ ? _1228_ : cr_in[31];
+  assign _0500_ = _0395_ ? { _0420_, _0420_, _0420_, _0420_, _0420_, _0420_, _0420_, _0420_, _0404_, 1'h1 } : { _0499_, _0497_, _0495_, _0493_, _0491_, _0489_, _0487_, _0485_, _0483_, _0481_, _0479_, _0477_, _0475_, _0473_, _0471_, _0469_, _0467_, _0465_, _0463_, _0461_, _0459_, _0457_, _0455_, _0453_, _0451_, _0449_, _0447_, _0445_, _0443_, _0441_, _0439_, _0437_, _0435_, 1'h1 };
+  assign _0501_ = e_in[8:3] == 6'h0e;
+  assign _0502_ = e_in[364:362] == 3'h0;
+  assign _0503_ = e_in[364:362] == 3'h1;
+  assign _0504_ = e_in[364:362] == 3'h2;
+  assign _0505_ = e_in[364:362] == 3'h3;
+  assign _0506_ = e_in[364:362] == 3'h4;
+  assign _0507_ = e_in[364:362] == 3'h5;
+  assign _0508_ = e_in[364:362] == 3'h6;
+  assign _0509_ = e_in[364:362] == 3'h7;
+  function [7:0] \11890 ;
+    input [7:0] a;
+    input [63:0] b;
+    input [7:0] s;
+    (* parallel_case *)
+    casez (s)
+      8'b???????1:
+        \11890  = b[7:0];
+      8'b??????1?:
+        \11890  = b[15:8];
+      8'b?????1??:
+        \11890  = b[23:16];
+      8'b????1???:
+        \11890  = b[31:24];
+      8'b???1????:
+        \11890  = b[39:32];
+      8'b??1?????:
+        \11890  = b[47:40];
+      8'b?1??????:
+        \11890  = b[55:48];
+      8'b1???????:
+        \11890  = b[63:56];
+      default:
+        \11890