final gds & drc results
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tree: 0853a78ac607261a02d68b6d2d5f99b339fdf418
  1. .travis.yml
  2. .travisCI/
  4. Makefile
  6. def/
  7. doc/
  8. documents/
  9. gds/
  10. info.yaml
  11. lef/
  12. macros/
  13. mag/
  14. maglef/
  16. netlists/
  17. ngspice/
  18. openlane/
  19. qflow/
  20. scripts/
  21. signoff/
  22. spi/
  23. test_integrate/
  24. utils/
  25. verilog/

Analog and RF Testchip on Skywaters 130nm Technology.

In this tapeout, we are planning to achieve the following:

  • 5 Transistor OTA with trimming resistors to adjust bias. [Completed with Layout, without the trimming resistor]
  • LDO [Schematic is complete, no layout currently]
  • VCO at 2.45GHz for BT, Wifi applications [Tentative plan and in progress]

OTA Design

  • Simulated specs
BW10Mega Hz12.6Mgea Hz10Mega Hz10Mega Hz10 Mega Hz
GBW64Mega80 Mega64 Mega65 Mega62Mega
power82.5 uw98.6 uw67 uw96 uw70 uw
phase margin92 degre94 degree93degree93 degree94 degree

LDO Design

  • Input voltage is 1.8V
  • Will add the specs later.

Schedule and timeline:

Monday December 7th, 2020

  • Complete the layout of trimming resistor for biasing of the 5 Transistor OTA

Thursday December 10th, 2020

  • Complete the LDO layout.

Thursday December 17th, 2020

  • Add a second stage for the OTA and have double stage OTA to achieve higher gain.