Merge branch 'develop' into master
diff --git a/.travisCI/runPrecheck.sh b/.travisCI/runPrecheck.sh
index 786b8b6..099f447 100644
--- a/.travisCI/runPrecheck.sh
+++ b/.travisCI/runPrecheck.sh
@@ -13,8 +13,11 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 export TARGET_PATH=$(pwd)
-cd open_mpw_precheck
-docker run -v $(pwd):/usr/local/bin -v $TARGET_PATH:$TARGET_PATH -u $(id -u $USER):$(id -g $USER) open_mpw_prechecker:latest bash -c "python3 open_mpw_prechecker.py --skip_drc -t $TARGET_PATH"
+cd ..
+export PDK_ROOT=$(pwd)/pdks
+cd $TARGET_PATH/open_mpw_precheck/
+
+docker run -v $(pwd):/usr/local/bin -v $TARGET_PATH:$TARGET_PATH -v $PDK_ROOT:$PDK_ROOT -u $(id -u $USER):$(id -g $USER) open_mpw_prechecker:latest bash -c "python3 open_mpw_prechecker.py -p $PDK_ROOT -t $TARGET_PATH"
 output=$TARGET_PATH/checks/full_log.log
 
 gzipped_file=$TARGET_PATH/checks/full_log.log.gz
@@ -23,8 +26,7 @@
     gzip -d $gzipped_file
 fi
 
-cnt=$(grep -c -i "All Checks PASSED" $output)
+cnt=$(grep -c -i "DRC violations" $output)
 if ! [[ $cnt ]]; then cnt=0; fi
-
-if [[ $cnt -eq 1 ]]; then exit 0; fi
-exit 2
+if [[ $cnt -eq 2 ]]; then exit 0; fi
+exit 2
\ No newline at end of file
diff --git a/.travisCI/travisBuild.sh b/.travisCI/travisBuild.sh
index bc0c40c..68d3fb4 100644
--- a/.travisCI/travisBuild.sh
+++ b/.travisCI/travisBuild.sh
@@ -17,5 +17,10 @@
 git clone https://github.com/efabless/open_mpw_precheck.git
 cd open_mpw_precheck/dependencies
 sh build-docker.sh
+cd $TARGET_PATH/..
+export PDK_ROOT=$(pwd)/pdks
+mkdir $PDK_ROOT
+cd $TARGET_PATH/open_mpw_precheck/dependencies
+sh build-pdk.sh
 cd $TARGET_DIR
 exit 0
diff --git a/Makefile b/Makefile
index cbc1c31..0071b95 100644
--- a/Makefile
+++ b/Makefile
@@ -8,13 +8,14 @@
 ARCHIVES := $(shell find . -type f -name "*.gz")
 ARCHIVE_SOURCES := $(basename $(ARCHIVES))
 
+
 # PDK setup configs
 THREADS ?= $(shell nproc)
 STD_CELL_LIBRARY ?= sky130_fd_sc_hd
 SPECIAL_VOLTAGE_LIBRARY ?= sky130_fd_sc_hvl
 IO_LIBRARY ?= sky130_fd_io
 SKYWATER_COMMIT ?= 3d7617a1acb92ea883539bcf22a632d6361a5de4
-OPEN_PDKS_COMMIT ?= 3959de867a4acb6867df376dac495e33bb0734f1
+OPEN_PDKS_COMMIT ?= b184e85de7629b8c87087a46b79eb45e7f7cd383
 
 .DEFAULT_GOAL := ship
 # We need portable GDS_FILE pointers...
@@ -61,6 +62,36 @@
 uncompress: $(ARCHIVE_SOURCES)
 	@echo "All files are uncompressed!"
 
+
+# LVS
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+LVS_BLOCKS = $(foreach block, $(BLOCKS), lvs-$(block))
+$(LVS_BLOCKS): lvs-% : ./mag/%.mag ./verilog/gl/%.v
+	echo "Extracting $*"
+	mkdir -p ./mag/tmp
+	echo "load $* -dereference;\
+		extract no all;\
+		extract do local;\
+		extract;\
+		ext2spice lvs;\
+		ext2spice;\
+		feedback save extract_$*.log;\
+		exit;" > ./mag/extract_$*.tcl
+	cd mag && MAGTYPE=maglef magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/current/sky130A.magicrc -noc -dnull extract_$*.tcl
+	mv ./mag/$*.spice ./spi/lvs
+	mv -f ./mag/extract_$*.{tcl,log} ./mag/*.ext ./mag/tmp
+	####
+	mkdir -p ./spi/lvs/tmp
+	sh ./spi/lvs/run_lvs.sh ./verilog/gl/$*.v ./spi/lvs/$*.spice $*
+	mv -f ./spi/lvs/*{.out,.json,.log} ./spi/lvs/tmp 2> /dev/null || true
+	
+
+.PHONY: help
+help:
+	@$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
+
+		
+###########################################################################
 .PHONY: pdk
 pdk: skywater-pdk skywater-library open_pdks build-pdk
 
diff --git a/README.md b/README.md
index 53d1508..2c77d56 100644
--- a/README.md
+++ b/README.md
@@ -6,8 +6,11 @@
 <img src="/doc/ciic_harness.png" width="75%" height="75%"> 
 </p>
 
+
 ## Getting Started:
 
+* For information on tooling and versioning, please refer to [this][1].
+
 Start by cloning the repo and uncompressing the files.
 ```bash
 git clone https://github.com/efabless/caravel.git
@@ -31,7 +34,8 @@
 - Caravel User Project Features -- https://youtu.be/zJhnmilXGPo
 - Aboard Caravel -- How to put your design on Caravel? -- https://youtu.be/9QV8SDelURk
 - Things to Clarify About Caravel -- What versions to use with Caravel? -- https://youtu.be/-LZ522mxXMw
-
+    - You could only use openlane:rc5
+    - Make sure you have the commit hashes provided here inside the [Makefile](./Makefile)
 ## Aboard Caravel:
 
 Your area is the full user_project_wrapper, so feel free to add your project there or create a differnt macro and harden it seperately then insert it into the user_project_wrapper. For example, if your design is analog or you're using a different tool other than OpenLANE.
@@ -43,7 +47,7 @@
 - [Magic VLSI Layout Tool](http://opencircuitdesign.com/magic/index.html) installed on your machine. We may provide a Dockerized version later.\*
 - You have your user_project_wrapper.gds under `./gds/` in the Caravel directory.
 
- > \* **Note:** You can avoid the need for the magic prerequisite by using the openlane docker to run the make step. This [section](#running-make-using-openlane's-magic) shows how.
+ > \* **Note:** You can avoid the need for the magic prerequisite by using the openlane docker to run the make step. This [section](#running-make-using-openlane-magic) shows how.
 
 Run the following command:
 
@@ -54,7 +58,7 @@
 
 This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`. You should expect hundred of thousands of magic DRC violations with the current "development" state of caravel.
 
-## Running Make using OpenLANE's Magic
+## Running Make using OpenLANE Magic
 
 To use the magic installed inside Openlane to complete the final GDS streaming out step, export the following:
 
@@ -80,6 +84,20 @@
 
 This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`. You should expect hundred of thousands of magic DRC violations with the current "development" state of caravel.
 
+## Required Directory Structure
+
+- ./gds/ : includes all the gds files used or produced from the project.
+- ./def/ : includes all the def files used or produced from the project.
+- ./lef/ : includes all the lef files used or produced from the project.
+- ./mag/ : includes all the mag files used or produced from the project.
+- ./maglef/ : includes all the maglef files used or produced from the project.
+- ./spi/lvs/ : includes all the maglef files used or produced from the project.
+- ./verilog/dv/ : includes all the simulation test benches and how to run them. 
+- ./verilog/gl/ : includes all the synthesized/elaborated netlists. 
+- ./verilog/rtl/ : includes all the Verilog RTLs and source files.
+- ./openlane/`<macro>`/ : includes all configuration files used to run openlane on your project.
+- info.yaml: includes all the info required in [this example](info.yaml). Please make sure that you are pointing to an elaborated caravel netlist as well as a synthesized gate-level-netlist for the user_project_wrapper
+
 ## Managment SoC
 The managment SoC runs firmware that can be used to:
 - Configure User Project I/O pads
@@ -102,3 +120,4 @@
 3. Configure the User Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles:  [LA_Test2](verilog/dv/caravel/user_proj_example/la_test2).
 
 [0]: openlane/README.md
+[1]: mpw-one-a.md
diff --git a/mag/.gitignore b/mag/.gitignore
new file mode 100644
index 0000000..a9a5aec
--- /dev/null
+++ b/mag/.gitignore
@@ -0,0 +1 @@
+tmp
diff --git a/maglef/digital_pll.mag b/maglef/digital_pll.mag
index 6db6f44..313db1f 100644
--- a/maglef/digital_pll.mag
+++ b/maglef/digital_pll.mag
@@ -205,7 +205,7 @@
 string LEFclass BLOCK
 string FIXED_BBOX 0 0 41136 41040
 string LEFview TRUE
-string GDS_FILE digital_pll.gds
+string GDS_FILE ../gds/digital_pll.gds
 string GDS_END 2654930
 string GDS_START 265824
 << end >>
diff --git a/maglef/gpio_control_block.mag b/maglef/gpio_control_block.mag
index d9036ce..352439b 100644
--- a/maglef/gpio_control_block.mag
+++ b/maglef/gpio_control_block.mag
@@ -135,7 +135,7 @@
 string LEFclass BLOCK
 string FIXED_BBOX 0 0 33934 18344
 string LEFview TRUE
-string GDS_FILE gpio_control_block.gds
+string GDS_FILE ../gds/gpio_control_block.gds
 string GDS_END 380356
 string GDS_START 138912
 << end >>
diff --git a/maglef/mgmt_core.mag b/maglef/mgmt_core.mag
index c508713..46c4a89 100644
--- a/maglef/mgmt_core.mag
+++ b/maglef/mgmt_core.mag
@@ -3291,7 +3291,7 @@
 string LEFclass BLOCK
 string FIXED_BBOX 0 0 430000 170000
 string LEFview TRUE
-string GDS_FILE mgmt_core.gds
+string GDS_FILE ../gds/mgmt_core.gds
 string GDS_END 169521478
 string GDS_START 2812312
 << end >>
diff --git a/maglef/mgmt_protect.mag b/maglef/mgmt_protect.mag
new file mode 100644
index 0000000..ee8e9db
--- /dev/null
+++ b/maglef/mgmt_protect.mag
@@ -0,0 +1,3740 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1607107346
+<< obsli1 >>
+rect 368 17 169556 12971
+<< metal1 >>
+rect 368 11920 169556 12016
+rect 368 11376 169556 11472
+<< obsm1 >>
+rect 368 12072 169556 12980
+rect 368 11528 169556 11864
+rect 368 8 169556 11320
+<< metal2 >>
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+<< metal3 >>
+rect 0 11976 800 12096
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+<< obsm3 >>
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+<< obsm4 >>
+rect 5494 171 153213 13021
+<< obsm5 >>
+rect 368 180 169556 10582
+<< labels >>
+rlabel metal2 s 570 0 626 800 6 caravel_clk
+port 1 nsew
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+rlabel metal3 s 0 1096 800 1216 6 caravel_rstn
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+rlabel metal2 s 754 12200 810 13000 6 la_data_in_core[0]
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+rlabel metal2 s 2594 12200 2650 13000 6 la_data_in_core[108]
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+rlabel metal2 s 3330 12200 3386 13000 6 la_data_in_core[110]
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+rlabel metal3 s 0 8168 800 8288 6 la_data_in_core[116]
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+rlabel metal2 s 11794 12200 11850 13000 6 la_data_in_core[2]
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+rlabel metal2 s 5722 0 5778 800 6 la_data_in_core[58]
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+rlabel metal2 s 18786 12200 18842 13000 6 la_data_in_core[59]
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+rlabel metal2 s 6090 0 6146 800 6 la_data_in_core[5]
+port 87 nsew
+rlabel metal2 s 19154 12200 19210 13000 6 la_data_in_core[60]
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+rlabel metal2 s 6458 0 6514 800 6 la_data_in_core[61]
+port 89 nsew
+rlabel metal2 s 19522 12200 19578 13000 6 la_data_in_core[62]
+port 90 nsew
+rlabel metal2 s 6826 0 6882 800 6 la_data_in_core[63]
+port 91 nsew
+rlabel metal2 s 19890 12200 19946 13000 6 la_data_in_core[64]
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+rlabel metal2 s 9770 0 9826 800 6 la_data_in_core[78]
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+rlabel metal2 s 10138 0 10194 800 6 la_data_in_core[7]
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+rlabel metal2 s 25042 12200 25098 13000 6 la_data_in_core[8]
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+rlabel metal2 s 12346 0 12402 800 6 la_data_in_core[90]
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+rlabel metal2 s 25410 12200 25466 13000 6 la_data_in_core[91]
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+rlabel metal2 s 12714 0 12770 800 6 la_data_in_core[92]
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+rlabel metal2 s 13082 0 13138 800 6 la_data_in_core[94]
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+rlabel metal2 s 26514 12200 26570 13000 6 la_data_in_core[97]
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+rlabel metal2 s 13818 0 13874 800 6 la_data_in_core[98]
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+rlabel metal2 s 26882 12200 26938 13000 6 la_data_in_core[99]
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+rlabel metal2 s 14186 0 14242 800 6 la_data_in_core[9]
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+rlabel metal2 s 14554 0 14610 800 6 la_data_in_mprj[0]
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+rlabel metal2 s 22282 0 22338 800 6 la_data_in_mprj[119]
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+rlabel metal2 s 153474 12200 153530 13000 6 mprj_dat_o_user[18]
+port 879 nsew
+rlabel metal2 s 153842 12200 153898 13000 6 mprj_dat_o_user[19]
+port 880 nsew
+rlabel metal2 s 154210 12200 154266 13000 6 mprj_dat_o_user[1]
+port 881 nsew
+rlabel metal2 s 154578 12200 154634 13000 6 mprj_dat_o_user[20]
+port 882 nsew
+rlabel metal2 s 154946 12200 155002 13000 6 mprj_dat_o_user[21]
+port 883 nsew
+rlabel metal2 s 155314 12200 155370 13000 6 mprj_dat_o_user[22]
+port 884 nsew
+rlabel metal2 s 155682 12200 155738 13000 6 mprj_dat_o_user[23]
+port 885 nsew
+rlabel metal2 s 156050 12200 156106 13000 6 mprj_dat_o_user[24]
+port 886 nsew
+rlabel metal2 s 156418 12200 156474 13000 6 mprj_dat_o_user[25]
+port 887 nsew
+rlabel metal2 s 156786 12200 156842 13000 6 mprj_dat_o_user[26]
+port 888 nsew
+rlabel metal2 s 157154 12200 157210 13000 6 mprj_dat_o_user[27]
+port 889 nsew
+rlabel metal2 s 157522 12200 157578 13000 6 mprj_dat_o_user[28]
+port 890 nsew
+rlabel metal2 s 157890 12200 157946 13000 6 mprj_dat_o_user[29]
+port 891 nsew
+rlabel metal2 s 158258 12200 158314 13000 6 mprj_dat_o_user[2]
+port 892 nsew
+rlabel metal2 s 158626 12200 158682 13000 6 mprj_dat_o_user[30]
+port 893 nsew
+rlabel metal2 s 158994 12200 159050 13000 6 mprj_dat_o_user[31]
+port 894 nsew
+rlabel metal2 s 159362 12200 159418 13000 6 mprj_dat_o_user[3]
+port 895 nsew
+rlabel metal2 s 159730 12200 159786 13000 6 mprj_dat_o_user[4]
+port 896 nsew
+rlabel metal2 s 160098 12200 160154 13000 6 mprj_dat_o_user[5]
+port 897 nsew
+rlabel metal2 s 160466 12200 160522 13000 6 mprj_dat_o_user[6]
+port 898 nsew
+rlabel metal2 s 160834 12200 160890 13000 6 mprj_dat_o_user[7]
+port 899 nsew
+rlabel metal2 s 161202 12200 161258 13000 6 mprj_dat_o_user[8]
+port 900 nsew
+rlabel metal2 s 161570 12200 161626 13000 6 mprj_dat_o_user[9]
+port 901 nsew
+rlabel metal2 s 163226 0 163282 800 6 mprj_sel_o_core[0]
+port 902 nsew
+rlabel metal2 s 163594 0 163650 800 6 mprj_sel_o_core[1]
+port 903 nsew
+rlabel metal2 s 163962 0 164018 800 6 mprj_sel_o_core[2]
+port 904 nsew
+rlabel metal2 s 164330 0 164386 800 6 mprj_sel_o_core[3]
+port 905 nsew
+rlabel metal2 s 161938 12200 161994 13000 6 mprj_sel_o_user[0]
+port 906 nsew
+rlabel metal2 s 162306 12200 162362 13000 6 mprj_sel_o_user[1]
+port 907 nsew
+rlabel metal2 s 162674 12200 162730 13000 6 mprj_sel_o_user[2]
+port 908 nsew
+rlabel metal2 s 163042 12200 163098 13000 6 mprj_sel_o_user[3]
+port 909 nsew
+rlabel metal2 s 164698 0 164754 800 6 mprj_stb_o_core
+port 910 nsew
+rlabel metal2 s 163410 12200 163466 13000 6 mprj_stb_o_user
+port 911 nsew
+rlabel metal2 s 165066 0 165122 800 6 mprj_we_o_core
+port 912 nsew
+rlabel metal2 s 163778 12200 163834 13000 6 mprj_we_o_user
+port 913 nsew
+rlabel metal2 s 165434 0 165490 800 6 user1_vcc_powergood
+port 914 nsew
+rlabel metal2 s 165802 0 165858 800 6 user1_vdd_powergood
+port 915 nsew
+rlabel metal2 s 166170 0 166226 800 6 user2_vcc_powergood
+port 916 nsew
+rlabel metal2 s 166538 0 166594 800 6 user2_vdd_powergood
+port 917 nsew
+rlabel metal2 s 164146 12200 164202 13000 6 user_clock
+port 918 nsew
+rlabel metal2 s 164514 12200 164570 13000 6 user_clock2
+port 919 nsew
+rlabel metal2 s 164882 12200 164938 13000 6 user_reset
+port 920 nsew
+rlabel metal2 s 754 0 810 800 6 user_resetn
+port 921 nsew
+rlabel metal1 s 368 11376 169556 11472 6 VPWR
+port 922 nsew power default
+rlabel metal1 s 368 11920 169556 12016 6 VGND
+port 923 nsew ground default
+<< properties >>
+string LEFclass BLOCK
+string FIXED_BBOX 0 0 169594 13025
+string LEFview TRUE
+<< end >>
+
diff --git a/maglef/simple_por.mag b/maglef/simple_por.mag
index cad6611..df5f40b 100644
--- a/maglef/simple_por.mag
+++ b/maglef/simple_por.mag
@@ -49,7 +49,7 @@
 string LEFclass BLOCK
 string FIXED_BBOX 0 0 11344 8338
 string LEFview TRUE
-string GDS_FILE simple_por.gds
+string GDS_FILE ../gds/simple_por.gds
 string GDS_END 386480
 string GDS_START 263388
 << end >>
diff --git a/maglef/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.mag b/maglef/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.mag
new file mode 100644
index 0000000..2309e77
--- /dev/null
+++ b/maglef/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.mag
@@ -0,0 +1,41 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1607107367
+<< obsli1 >>
+rect 66 67 5058 4171
+<< metal1 >>
+rect 66 4917 5058 5019
+rect 66 3289 5058 3391
+<< obsm1 >>
+rect 66 3447 5058 4177
+rect 66 33 5058 3233
+<< metal2 >>
+rect 4310 4284 4366 5084
+rect 662 84 718 884
+<< obsm2 >>
+rect 664 4228 4254 5019
+rect 4422 4228 4460 5019
+rect 664 940 4460 4228
+rect 774 33 4460 940
+<< obsm3 >>
+rect 739 51 4392 5001
+<< obsm4 >>
+rect 739 33 4392 5019
+<< obsm5 >>
+rect 66 706 5058 4359
+<< labels >>
+rlabel metal2 s 4310 4284 4366 5084 6 A
+port 1 nsew
+rlabel metal2 s 662 84 718 884 6 X
+port 2 nsew
+rlabel metal1 s 66 3289 5058 3391 6 VPWR
+port 3 nsew power default
+rlabel metal1 s 66 4917 5058 5019 6 VGND
+port 4 nsew ground default
+<< properties >>
+string LEFclass BLOCK
+string FIXED_BBOX 0 1 5124 5084
+string LEFview TRUE
+<< end >>
+
diff --git a/maglef/storage.mag b/maglef/storage.mag
index ca6b712..f7edcd7 100644
--- a/maglef/storage.mag
+++ b/maglef/storage.mag
@@ -816,7 +816,7 @@
 string LEFclass BLOCK
 string FIXED_BBOX 0 0 88934 189234
 string LEFview TRUE
-string GDS_FILE storage.gds
+string GDS_FILE ../gds/storage.gds
 string GDS_END 15067618
 string GDS_START 13323184
 << end >>
diff --git a/maglef/user_id_programming.mag b/maglef/user_id_programming.mag
new file mode 100644
index 0000000..1a5da66
--- /dev/null
+++ b/maglef/user_id_programming.mag
@@ -0,0 +1,164 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1607107372
+<< obsli1 >>
+rect 1104 1071 5980 6001
+<< obsm1 >>
+rect 566 1040 6518 6032
+<< metal2 >>
+rect 1122 6277 1178 7077
+rect 1674 6277 1730 7077
+rect 2226 6277 2282 7077
+rect 2962 6277 3018 7077
+rect 3514 6277 3570 7077
+rect 4066 6277 4122 7077
+rect 4802 6277 4858 7077
+rect 5354 6277 5410 7077
+rect 5906 6277 5962 7077
+rect 6458 6277 6514 7077
+rect 570 0 626 800
+rect 1122 0 1178 800
+rect 1674 0 1730 800
+rect 2226 0 2282 800
+rect 2962 0 3018 800
+rect 3514 0 3570 800
+rect 4066 0 4122 800
+rect 4802 0 4858 800
+rect 5354 0 5410 800
+rect 5906 0 5962 800
+<< obsm2 >>
+rect 572 6221 1066 6277
+rect 1234 6221 1618 6277
+rect 1786 6221 2170 6277
+rect 2338 6221 2906 6277
+rect 3074 6221 3458 6277
+rect 3626 6221 4010 6277
+rect 4178 6221 4746 6277
+rect 4914 6221 5298 6277
+rect 5466 6221 5850 6277
+rect 6018 6221 6402 6277
+rect 572 856 6512 6221
+rect 682 800 1066 856
+rect 1234 800 1618 856
+rect 1786 800 2170 856
+rect 2338 800 2906 856
+rect 3074 800 3458 856
+rect 3626 800 4010 856
+rect 4178 800 4746 856
+rect 4914 800 5298 856
+rect 5466 800 5850 856
+rect 6018 800 6512 856
+<< metal3 >>
+rect 0 5992 800 6112
+rect 0 5176 800 5296
+rect 6309 5176 7109 5296
+rect 0 4360 800 4480
+rect 6309 4360 7109 4480
+rect 6309 3544 7109 3664
+rect 0 3272 800 3392
+rect 0 2456 800 2576
+rect 6309 2456 7109 2576
+rect 0 1640 800 1760
+rect 6309 1640 7109 1760
+rect 6309 824 7109 944
+<< obsm3 >>
+rect 880 5912 6309 6082
+rect 800 5376 6309 5912
+rect 880 5096 6229 5376
+rect 800 4560 6309 5096
+rect 880 4280 6229 4560
+rect 800 3744 6309 4280
+rect 800 3472 6229 3744
+rect 880 3464 6229 3472
+rect 880 3192 6309 3464
+rect 800 2656 6309 3192
+rect 880 2376 6229 2656
+rect 800 1840 6309 2376
+rect 880 1560 6229 1840
+rect 800 1024 6309 1560
+rect 800 851 6229 1024
+<< obsm4 >>
+rect 1756 1040 5327 6032
+<< metal5 >>
+rect 1104 2512 5980 2832
+rect 1104 1696 5980 2016
+<< obsm5 >>
+rect 1104 3328 5980 5280
+<< labels >>
+rlabel metal2 s 4066 6277 4122 7077 6 mask_rev[0]
+port 1 nsew
+rlabel metal2 s 4066 0 4122 800 6 mask_rev[10]
+port 2 nsew
+rlabel metal2 s 1122 0 1178 800 6 mask_rev[11]
+port 3 nsew
+rlabel metal2 s 570 0 626 800 6 mask_rev[12]
+port 4 nsew
+rlabel metal2 s 5354 6277 5410 7077 6 mask_rev[13]
+port 5 nsew
+rlabel metal2 s 5906 0 5962 800 6 mask_rev[14]
+port 6 nsew
+rlabel metal3 s 6309 1640 7109 1760 6 mask_rev[15]
+port 7 nsew
+rlabel metal2 s 2226 0 2282 800 6 mask_rev[16]
+port 8 nsew
+rlabel metal2 s 1674 6277 1730 7077 6 mask_rev[17]
+port 9 nsew
+rlabel metal3 s 0 5176 800 5296 6 mask_rev[18]
+port 10 nsew
+rlabel metal2 s 2962 6277 3018 7077 6 mask_rev[19]
+port 11 nsew
+rlabel metal3 s 0 3272 800 3392 6 mask_rev[1]
+port 12 nsew
+rlabel metal3 s 6309 2456 7109 2576 6 mask_rev[20]
+port 13 nsew
+rlabel metal3 s 6309 824 7109 944 6 mask_rev[21]
+port 14 nsew
+rlabel metal3 s 0 5992 800 6112 6 mask_rev[22]
+port 15 nsew
+rlabel metal2 s 1674 0 1730 800 6 mask_rev[23]
+port 16 nsew
+rlabel metal2 s 5906 6277 5962 7077 6 mask_rev[24]
+port 17 nsew
+rlabel metal3 s 0 1640 800 1760 6 mask_rev[25]
+port 18 nsew
+rlabel metal2 s 4802 6277 4858 7077 6 mask_rev[26]
+port 19 nsew
+rlabel metal2 s 1122 6277 1178 7077 6 mask_rev[27]
+port 20 nsew
+rlabel metal2 s 6458 6277 6514 7077 6 mask_rev[28]
+port 21 nsew
+rlabel metal2 s 5354 0 5410 800 6 mask_rev[29]
+port 22 nsew
+rlabel metal3 s 0 2456 800 2576 6 mask_rev[2]
+port 23 nsew
+rlabel metal3 s 6309 5176 7109 5296 6 mask_rev[30]
+port 24 nsew
+rlabel metal2 s 2962 0 3018 800 6 mask_rev[31]
+port 25 nsew
+rlabel metal2 s 3514 0 3570 800 6 mask_rev[3]
+port 26 nsew
+rlabel metal3 s 6309 3544 7109 3664 6 mask_rev[4]
+port 27 nsew
+rlabel metal3 s 6309 4360 7109 4480 6 mask_rev[5]
+port 28 nsew
+rlabel metal3 s 0 4360 800 4480 6 mask_rev[6]
+port 29 nsew
+rlabel metal2 s 3514 6277 3570 7077 6 mask_rev[7]
+port 30 nsew
+rlabel metal2 s 4802 0 4858 800 6 mask_rev[8]
+port 31 nsew
+rlabel metal2 s 2226 6277 2282 7077 6 mask_rev[9]
+port 32 nsew
+rlabel metal5 s 1104 1696 5980 2016 6 VPWR
+port 33 nsew power default
+rlabel metal5 s 1104 2512 5980 2832 6 VGND
+port 34 nsew ground default
+<< properties >>
+string LEFclass BLOCK
+string FIXED_BBOX 0 0 7109 7077
+string LEFview TRUE
+string GDS_FILE ../gds/user_id_programming.gds
+string GDS_START 0
+<< end >>
+
diff --git a/mpw-one-a.md b/mpw-one-a.md
new file mode 100644
index 0000000..7c4833e
--- /dev/null
+++ b/mpw-one-a.md
@@ -0,0 +1,71 @@
+# Repositories and versions to use
+
+## skywater-pdk:
+
+Please stick to version `v0.0.0-303-g3d7617a`
+(commit hash: `3d7617a1acb92ea883539bcf22a632d6361a5de4`)
+```
+git clone https://github.com/google/skywater-pdk.git
+cd skywater-pdk
+git checkout v0.0.0-303-g3d7617a
+git submodule update --init libraries/sky130_fd_sc_hd/latest
+git submodule update --init libraries/sky130_fd_sc_hvl/latest
+...
+git submodule update --init libraries/sky130_fd_io/latest
+```
+
+## open_pdks:
+
+Please stick to the `mpw-one-a` tag.
+```
+git clone https://github.com/RTimothyEdwards/open_pdks.git -b mpw-one-a
+```
+
+## OpenLane:
+
+Please stick to the `mpw-one-a` tag.
+```
+git clone https://github.com/efabless/openlane.git -b mpw-one-a
+```
+Note that the `mpw-one-a` tag is equivalent to the `rc5` tag. Also, note that
+running `make` inside the openlane directory will automatically grab the right
+versions of `open_pdks` and `skywater-pdk` as listed above and install them to
+PDK_ROOT.
+
+For example,
+
+```
+export PDK_ROOT=$HOME/pdks
+cd openlane
+make
+```
+
+## Caravel: 
+
+Please stick to the `mpw-one-a` tag.
+```
+git clone https://github.com/efabless/caravel.git -b mpw-one-a
+```
+
+## Notes
+
+- If you have already successfully hardened your blocks and have a clean
+  `user_project_wrapper`, you don't have to recreate it and can just reuse it.
+  No changes have been made to the user project area or to the tools that
+  require you to reharden your design(s).
+
+- If you prefer to re-generate your blocks (using OpenLane), you can refer to
+  this [page][1].
+
+- **IMPORTANT**. Do not forget to run `make uncompress -j4` in the caravel root
+  directory before you start working. Likewise, before you commit and push your
+  changes back, run `make compress -j4`.
+
+- If you already have a clean working tree in a previously cloned repository from
+  those listed above, what you need to do is:
+  ```
+  git pull
+  git checkout tag
+  ```
+
+[1]: ./openlane/README.md
diff --git a/openlane/Makefile b/openlane/Makefile
index 8d2e712..44e9415 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -47,7 +47,7 @@
 	@echo "Please export OPENLANE_ROOT"
 	@exit 1
 endif
-	git clone https://github.com/efabless/openlane.git --branch=develop $(OPENLANE_ROOT) && \
+	git clone https://github.com/efabless/openlane.git --branch=master $(OPENLANE_ROOT) && \
 		cd $(OPENLANE_ROOT) && \
 		make openlane
 
diff --git a/openlane/README.md b/openlane/README.md
index 9218d7d..82381e9 100644
--- a/openlane/README.md
+++ b/openlane/README.md
@@ -10,16 +10,16 @@
 
 **NOTE:** rc5 and caravel are still WIP so expect to run into some issues when using it.
 
-If you don't have openlane already, then you can get it from [here](https://github.com/efabless/openlane) and checkout out to `develop` branch. Alternatively, you can clone and build the openlane develop branch through:
+If you don't have openlane already, then you can get it from [here](https://github.com/efabless/openlane) and checkout out to `rc5` tag. Alternatively, you can clone and build openlane through:
 ```bash
     make openlane
 ```
 
-**NOTE:** We are developing caravel using openlane:rc5 which is the current develop branch. openlane:rc5 will be merged to master once the caravel chip is finalized.
+**NOTE:** We are developing caravel using openlane:rc5 which is the current master branch.
 
-**NOTE:** rc5 (current openlane develop) and rc4 (current openlane master) are using two different concepts of cell padding. rc4 is modifying the LEF, while rc5 is relying on openroad to handle the cell padding. Also, rc4 is using the standalone version of openDP while rc5 is using the one integrated in the openroad app. This affects the concept of PL_TARGET_DENSITY and while in rc4 it was preferred to have PL_TARGET_DENSITY=(FP_CORE_UTIL-(5\~10)/100). Now, in rc5 it is preferred to be  PL_TARGET_DENSITY=(FP_CORE_UTIL+(1\~5)/100).
+**NOTE:** rc5 (current openlane master) and rc4 (previous openlane master) are using two different concepts of cell padding. rc4 is modifying the LEF, while rc5 is relying on openroad to handle the cell padding. Also, rc4 is using the standalone version of openDP while rc5 is using the one integrated in the openroad app. This affects the concept of PL_TARGET_DENSITY and while in rc4 it was preferred to have PL_TARGET_DENSITY=(FP_CORE_UTIL-(5\~10)/100). Now, in rc5 it is preferred to be  PL_TARGET_DENSITY=(FP_CORE_UTIL+(1\~5)/100).
 FP_CORE_UTIL should be relaxed as well as it became more representative of the actual core utilization, which wasn't so much the case earlier. So, the perception of these two variables as well as CELL_PAD changed between rc4 and rc5 which necessitates a change in the configurations of almost every single design.
-CELL_PAD should be 4~6 for the skywater libraries in rc5 unlike rc4 which was 8.This will be included in the release notes when rc5 is released as well as the openlane wiki.
+CELL_PAD should be 4~6 for the skywater libraries in rc5 unlike rc4 which was 8.
 
 Then, you have two options:
 1. Create a macro for your design and harden it, then insert it into user_project_wrapper.
@@ -57,7 +57,7 @@
 
 Then, follow the instructions given in Option 2.
 
-**NOTE:** You might have other macros inside your design. In which case, you may need to have some special power configurations. This is covered [here](https://github.com/efabless/openlane/blob/develop/doc/hardening_macros.md#power-grid-pdn).
+**NOTE:** You might have other macros inside your design. In which case, you may need to have some special power configurations. This is covered [here](https://github.com/efabless/openlane/blob/master/doc/hardening_macros.md#power-grid-pdn).
 
 ## Option 2:
 
@@ -83,18 +83,25 @@
 ```
 **NOTE:** Don't change the size or the pin order!
 
-3. Remove this line `add_macro_placement mprj 1150 1700 N` from the interactive script [here](./user_project_wrapper/config.tcl) and replace it with the placement for your macro instances. Or, remove it entirely if you have no macros, along with this line `manual_macro_placement f`.
+3. If your design has standard cells then you need to replace `verilog_elaborate` with `run_synthesis` [here](./user_project_wrapper/interactive.tcl).
 
-4. Run your design through the flow: `make user_project_wrapper`
+4. If your design has standard cells then you need to replace `init_floorplan; place_io_ol;` with `run_floorplan` [here](./user_project_wrapper/interactive.tcl).
+ 
+5. If your design has standard cells then add `run_placement` after `manual_macro_placement f` [here](./user_project_wrapper/interactive.tcl).
 
-5. Re-iterate until you have what you want.
+6. Remove this line `add_macro_placement mprj 1150 1700 N` from the interactive script [here](./user_project_wrapper/interactive.tcl) and replace it with the placement for your macro instances. Or, remove it entirely if you have no macros, along with this line `manual_macro_placement f`.
 
-6. Go back to the main [README.md](../README.md) and continue the process of boarding the chip.
+7. Run your design through the flow: `make user_project_wrapper`
 
-**NOTE:** In both cases you might have other macros inside your design. In which case, you may need to have some special power configurations. This is covered [here](https://github.com/efabless/openlane/blob/develop/doc/hardening_macros.md#power-grid-pdn).
+8. You may want to take a look at the [Extra Pointers](#extra-pointers) to apply any necessary changes to the interactive script.
 
-## Extra Pointers:
+8. Re-iterate until you have what you want.
 
+9. Go back to the main [README.md](../README.md) and continue the process of boarding the chip.
+
+**NOTE:** In both cases you might have other macros inside your design. In which case, you may need to have some special power configurations. This is covered [here](https://github.com/efabless/openlane/blob/master/doc/hardening_macros.md#power-grid-pdn).
+
+## Extra Pointers
 
 - The OpenLANE documentation should cover everything you might need to create your design. You can find that [here](https://github.com/efabless/openlane/blob/master/README.md).
 - The OpenLANE [FAQs](https://github.com/efabless/openlane/wiki) can guide through your troubles.
@@ -102,4 +109,4 @@
 - [Here](https://github.com/efabless/openlane/blob/master/doc/advanced_readme.md) you can learn how to write an interactive script.
 - [Here](https://github.com/efabless/openlane/blob/master/doc/OpenLANE_commands.md) you can find a full documentation for all OpenLANE commands.
 - [This documentation](https://github.com/efabless/openlane/blob/master/regression_results/README.md) describes how to use the exploration script to achieve an LVS/DRC clean design.
-- [This documentation](https://github.com/efabless/openlane/blob/develop/doc/hardening_macros.md) walks you through hardening a macro and all the decisions you should make.
+- [This documentation](https://github.com/efabless/openlane/blob/master/doc/hardening_macros.md) walks you through hardening a macro and all the decisions you should make.
diff --git a/openlane/chip_io/interactive.tcl b/openlane/chip_io/interactive.tcl
index 76964a0..cea6f32 100755
--- a/openlane/chip_io/interactive.tcl
+++ b/openlane/chip_io/interactive.tcl
@@ -98,7 +98,7 @@
                  -gds_path $::env(magic_result_file_tag).gds \
                  -mag_path $::env(magic_result_file_tag).mag \
                  -maglef_path $::env(magic_result_file_tag).lef.mag \
-				 -verilog_path $::env(CURRENT_NETLIST) \
+				 -verilog_path $::env(TMP)/lvs.v \
                  -save_path $save_path \
                  -tag $::env(RUN_TAG)
 
diff --git a/spi/lvs/.gitignore b/spi/lvs/.gitignore
new file mode 100644
index 0000000..a9a5aec
--- /dev/null
+++ b/spi/lvs/.gitignore
@@ -0,0 +1 @@
+tmp
diff --git a/spi/lvs/run_lvs.sh b/spi/lvs/run_lvs.sh
new file mode 100644
index 0000000..77ff185
--- /dev/null
+++ b/spi/lvs/run_lvs.sh
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+NETGEN_SETUP=$PDK_ROOT/sky130A/libs.tech/netgen/sky130A_setup.tcl
+
+netgen -batch lvs "$1 $3" "$2 $3" ${NETGEN_SETUP} $2_comp.out -json | tee $2_comp_lvs.log
diff --git a/verilog/dv/caravel/mgmt_soc/Makefile b/verilog/dv/caravel/mgmt_soc/Makefile
index 2f6bd4a..acf62f9 100644
--- a/verilog/dv/caravel/mgmt_soc/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/Makefile
@@ -7,7 +7,8 @@
 
 all:  ${PATTERNS}
 	for i in ${PATTERNS}; do \
-		( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+		( cd $$i && SIM=RTL make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+		( cd $$i && SIM=GL make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
 	done
 
 clean:  ${PATTERNS}
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/Makefile b/verilog/dv/caravel/mgmt_soc/gpio/Makefile
index 305375f..9eba549 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/gpio/Makefile
@@ -1,5 +1,6 @@
 FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
@@ -7,6 +8,8 @@
 GCC_PREFIX?=riscv32-unknown-elf
 PDK_PATH?=/ef/tech/SW/sky130A
 
+SIM?=RTL
+
 .SUFFIXES:
 
 PATTERN = gpio
@@ -16,9 +19,15 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
 	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
+	$< -o $@ 
+else  
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
 
 %.vcd: %.vvp
 	vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
index 849032c..f46fee9 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
@@ -46,8 +46,12 @@
 			$display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test GPIO (RTL) Failed");
-		 $display("%c[0m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test GPIO (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
 		$finish;
 	end
 
@@ -59,6 +63,7 @@
 	assign mprj_io[23:16] = checkbits_lo;
 	assign checkbits = mprj_io[31:16];
 	assign checkbits_hi = checkbits[15:8];
+	assign mprj_io[3] = 1'b1;       // Force CSB high.
 
 	wire flash_csb;
 	wire flash_clk;
@@ -96,7 +101,11 @@
 		wait(checkbits_hi == 8'h02);
 		wait(checkbits[7:0]  == 8'h03);
 		wait(checkbits_hi == 8'h04);
-		$display("Monitor: Test GPIO (RTL) Passed");
+		`ifdef GL
+			$display("Monitor: Test GPIO (GL) Passed");
+		`else
+			$display("Monitor: Test GPIO (RTL) Passed");
+		`endif
 		$finish;
 	end
 
diff --git a/verilog/dv/caravel/mgmt_soc/gpio_gl/Makefile b/verilog/dv/caravel/mgmt_soc/gpio_gl/Makefile
deleted file mode 100644
index f896dc0..0000000
--- a/verilog/dv/caravel/mgmt_soc/gpio_gl/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-FIRMWARE_PATH = ../..
-VERILOG_PATH = ../../../..
-RTL_PATH = $(VERILOG_PATH)/rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../ 
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = gpio
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
-	$< -o $@
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
-	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/gpio_gl/README b/verilog/dv/caravel/mgmt_soc/gpio_gl/README
deleted file mode 100644
index f1935dd..0000000
--- a/verilog/dv/caravel/mgmt_soc/gpio_gl/README
+++ /dev/null
@@ -1,27 +0,0 @@
-------------------------------------------------
-Caravel
-gpio testbench
-------------------------------------------------
-
-This testbench exercises the fundamental use of the Caravel
-management SoC to drive the I/O in the user area as general
-purpose I/O on startup.
-
-On startup, all GPIO are configured as input to the management
-region (so as to be high impedence to the external world) and
-decoupled from the user project area.
-
-To configure any GPIO as output, the appropriate memory-mapped
-location for the I/O must be properly configured.  Since the
-I/O configuration is stored in two places, in the SoC, but
-also locally at each I/O pad, the "transfer" bit must be
-applied, which initiates a transfer of the configuration data
-around the padframe.
-
-The testbench takes 16 pins from the user area and checks
-functionality by applying input values on 8 of these pins from
-the testbench verilog, detecting them in the C program, then
-copying the values to the other 8 pins, and detecting those
-values in the testbench verilog.
-
-If any of that does not work, then the testbench will fail.
diff --git a/verilog/dv/caravel/mgmt_soc/gpio_gl/gpio.c b/verilog/dv/caravel/mgmt_soc/gpio_gl/gpio.c
deleted file mode 100644
index 1e1e48a..0000000
--- a/verilog/dv/caravel/mgmt_soc/gpio_gl/gpio.c
+++ /dev/null
@@ -1,98 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-/*
- *	GPIO Test
- *		Tests PU and PD on the lower 8 pins while being driven from outside
- *		Tests Writing to the upper 8 pins
- *		Tests reading from the lower 8 pins
- */
-
-void main()
-{
-	int i;
-
-	/* Set data out to zero */
-	reg_mprj_datal = 0;
-
-	/* Lower 8 pins are input and upper 8 pins are output */
-	reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-	reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
-	reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
-	reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
-	reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
-	reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
-	reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
-	reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
-	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
-
-	/* Apply configuration */
-	reg_mprj_xfer = 1;
-	while (reg_mprj_xfer == 1);
-
-	// change the pull up and pull down (checked by the TB)
-	reg_mprj_datal = 0xa0000000;
-
-	reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
-	reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
-	reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
-	reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
-
-	reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
-	reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
-	reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
-	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
-
-	/* Apply configuration */
-	reg_mprj_xfer = 1;
-	while (reg_mprj_xfer == 1);
-
-	reg_mprj_datal = 0x0b000000;
-
-	reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
-	reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
-	reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
-	reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
-
-	reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
-	reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
-	reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
-	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
-
-	/* Apply configuration */
-	reg_mprj_xfer = 1;
-	while (reg_mprj_xfer == 1);
-
-	reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
-	reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
-	reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
-	reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
-
-	reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
-	reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
-	reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
-	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
-
-	/* Apply configuration */
-	reg_mprj_xfer = 1;
-	while (reg_mprj_xfer == 1);
-
-	// read the lower 8 pins, add 1 then output the result
-	// checked by the TB
-	reg_mprj_datal = 0xab000000;
-
-	while (1){
-		int x = (reg_mprj_datal & 0xff0000) >> 16;
-		reg_mprj_datal = (x+1) << 24;
-	}
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/gpio_gl/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio_gl/gpio_tb.v
deleted file mode 100644
index 49a3467..0000000
--- a/verilog/dv/caravel/mgmt_soc/gpio_gl/gpio_tb.v
+++ /dev/null
@@ -1,185 +0,0 @@
-`default_nettype none
-/*
- *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
- *
- *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
- *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module gpio_tb;
-
-	reg clock;
-	reg power1;
-	reg power2;
-
-	always #10 clock <= (clock === 1'b0);
-
-	initial begin
-		clock <= 0;
-	end
-
-	initial begin
-		$dumpfile("gpio.vcd");
-		$dumpvars(0, gpio_tb);
-
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (25) begin
-			repeat (1000) @(posedge clock);
-			$display("+1000 cycles");
-		end
-		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test GPIO (GL) Failed");
-		$display("%c[0m",27);
-		$finish;
-	end
-
-	wire [37:0] mprj_io;	// Most of these are no-connects
-	wire [15:0] checkbits;
-	reg  [7:0] checkbits_lo;
-	wire [7:0] checkbits_hi;
-
-	assign mprj_io[23:16] = checkbits_lo;
-	assign checkbits = mprj_io[31:16];
-	assign checkbits_hi = checkbits[15:8];
-
-	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-	wire gpio;
-
-	reg RSTB;
-
-	// Transactor
-	initial begin
-		checkbits_lo <= {8{1'bz}};
-		wait(checkbits_hi == 8'hA0);
-		checkbits_lo <= 8'hF0;
-		wait(checkbits_hi == 8'h0B);
-		checkbits_lo <= 8'h0F;
-		wait(checkbits_hi == 8'hAB);
-		checkbits_lo <= 8'h0;
-		repeat (1000) @(posedge clock);
-		checkbits_lo <= 8'h1;
-		repeat (1000) @(posedge clock);
-		checkbits_lo <= 8'h3;
-	end
-
-	// Monitor
-	initial begin
-		wait(checkbits_hi == 8'hA0);
-		wait(checkbits[7:0]  == 8'hF0);
-		wait(checkbits_hi == 8'h0B);
-		wait(checkbits[7:0]  == 8'h0F);
-		wait(checkbits_hi == 8'hAB);
-		wait(checkbits[7:0]  == 8'h00);
-		wait(checkbits_hi == 8'h01);
-		wait(checkbits[7:0]  == 8'h01);
-		wait(checkbits_hi == 8'h02);
-		wait(checkbits[7:0]  == 8'h03);
-		wait(checkbits_hi == 8'h04);
-		$display("Monitor: Test GPIO (GL) Passed");
-		$finish;
-	end
-
-	initial begin
-		RSTB <= 1'b0;
-		
-		#1000;
-		RSTB <= 1'b1;	    // Release reset
-		#2000;
-	end
-
-	initial begin			// Power-up
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		#200;
-		power1 <= 1'b1;
-		#200;
-		power2 <= 1'b1;
-	end
-		
-
-	always @(checkbits) begin
-		#1 $display("GPIO state = %b (%d - %d)", checkbits,
-				checkbits_hi, checkbits_lo);
-	end
-
-	wire VDD3V3;
-	wire VDD1V8;
-	wire VSS;
-
-	assign VDD3V3 = power1;
-	assign VDD1V8 = power2;
-	assign VSS = 1'b0;
-
-	// These are the mappings of mprj_io GPIO pads that are set to
-	// specific functions on startup:
-	//
-	// JTAG      = mgmt_gpio_io[0]              (inout)
-	// SDO       = mgmt_gpio_io[1]              (output)
-	// SDI       = mgmt_gpio_io[2]              (input)
-	// CSB       = mgmt_gpio_io[3]              (input)
-	// SCK       = mgmt_gpio_io[4]              (input)
-	// ser_rx    = mgmt_gpio_io[5]              (input)
-	// ser_tx    = mgmt_gpio_io[6]              (output)
-	// irq       = mgmt_gpio_io[7]              (input)
-
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (VDD3V3),
-		.vdda2    (VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (VDD1V8),
-		.vccd2	  (VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock	  (clock),
-		.gpio     (gpio),
-		.mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("gpio.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/Makefile b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
index 9ba4635..4d47f98 100644
--- a/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
@@ -1,6 +1,7 @@
 # ---- Test patterns for project striVe ----
 FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
@@ -8,6 +9,8 @@
 GCC_PREFIX?=riscv32-unknown-elf
 PDK_PATH?=/ef/tech/SW/sky130A
 
+SIM?=RTL
+
 .SUFFIXES:
 
 PATTERN = hkspi
@@ -17,9 +20,15 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
 	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
+	$< -o $@ 
+else  
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
 
 %.vcd: %.vvp
 	vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
index 56531d0..e709e91 100644
--- a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
@@ -165,65 +165,183 @@
 	    read_byte(tbdata);
 
 	    $display("Read register 0 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read register 1 = 0x%02x (should be 0x04)", tbdata);
-		if(tbdata !== 8'h04) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h04) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read register 2 = 0x%02x (should be 0x56)", tbdata);
-		if(tbdata !== 8'h56) begin $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish; end
+		if(tbdata !== 8'h56) begin
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed, %02x", tbdata); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read register 3 = 0x%02x (should be 0x10)", tbdata);
-		if(tbdata !== 8'h10) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h10) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed, %02x", tbdata); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read register 4 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read register 5 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read register 6 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read register 7 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read register 8 = 0x%02x (should be 0x02)", tbdata);
-		if(tbdata !== 8'h02) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h02) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read register 9 = 0x%02x (should be 0x01)", tbdata);
-		if(tbdata !== 8'h01) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h01) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read register 10 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read register 11 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read register 12 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read register 13 = 0x%02x (should be 0xff)", tbdata);
-		if(tbdata !== 8'hff) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'hff) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read register 14 = 0x%02x (should be 0xef)", tbdata);
-		if(tbdata !== 8'hef) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'hef) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read register 15 = 0x%02x (should be 0xff)", tbdata);
-		if(tbdata !== 8'hff) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'hff) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read register 16 = 0x%02x (should be 0x03)", tbdata);
-		if(tbdata !== 8'h03) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h03) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read register 17 = 0x%02x (should be 0x12)", tbdata);
-		if(tbdata !== 8'h12) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h12) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read register 18 = 0x%02x (should be 0x04)", tbdata);
-		if(tbdata !== 8'h04) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+		if(tbdata !== 8'h04) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
 		
         end_csb();
 
-		$display("Monitor: Test HK SPI (RTL) Passed");
+		`ifdef GL
+			$display("Monitor: Test HK SPI (GL) Passed");
+		`else
+			$display("Monitor: Test HK SPI (RTL) Passed");
+		`endif
 
 	    #10000;
  	    $finish;
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi_gl/Makefile b/verilog/dv/caravel/mgmt_soc/hkspi_gl/Makefile
deleted file mode 100644
index be47dd2..0000000
--- a/verilog/dv/caravel/mgmt_soc/hkspi_gl/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-FIRMWARE_PATH = ../..
-VERILOG_PATH = ../../../..
-RTL_PATH = $(VERILOG_PATH)/rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../ 
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = hkspi
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
-	$< -o $@
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
-	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi_gl/hkspi.c b/verilog/dv/caravel/mgmt_soc/hkspi_gl/hkspi.c
deleted file mode 100644
index 826bf59..0000000
--- a/verilog/dv/caravel/mgmt_soc/hkspi_gl/hkspi.c
+++ /dev/null
@@ -1,75 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-void putchar(char c)
-{
-	if (c == '\n')
-		putchar('\r');
-	reg_uart_data = c;
-}
-
-void print(const char *p)
-{
-	while (*p)
-		putchar(*(p++));
-}
-
-// --------------------------------------------------------
-
-void main()
-{
-    // This program is just to keep the processor busy while the
-    // housekeeping SPI is being accessed, to show that the
-    // processor is interrupted only when the reset is applied
-    // through the SPI.
-
-    // Configure I/O:  High 16 bits of user area used for a 16-bit
-    // word to write and be detected by the testbench verilog.
-    // Only serial Tx line is used in this testbench.  It connects
-    // to mprj_io[6].  Since all lines of the chip are input or
-    // high impedence on startup, the I/O has to be configured
-    // for output
-
-    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    // Apply configuration
-    reg_mprj_xfer = 1;
-    while (reg_mprj_xfer == 1);
-
-    // Start test
-    reg_mprj_datal = 0xa0000000;
-
-    // Set clock to 64 kbaud and enable the UART
-    reg_uart_clkdiv = 625;
-    reg_uart_enable = 1;
-
-    // Test message
-    print("\n");
-    print("  ____  _          ____         ____\n");
-    print(" |  _ \\(_) ___ ___/ ___|  ___  / ___|\n");
-    print(" | |_) | |/ __/ _ \\___ \\ / _ \\| |\n");
-    print(" |  __/| | (_| (_) |__) | (_) | |___\n");
-    print(" |_|   |_|\\___\\___/____/ \\___/ \\____|\n");
-
-    reg_mprj_datal = 0xab000000;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi_gl/hkspi_tb.v b/verilog/dv/caravel/mgmt_soc/hkspi_gl/hkspi_tb.v
deleted file mode 100644
index 88b8edf..0000000
--- a/verilog/dv/caravel/mgmt_soc/hkspi_gl/hkspi_tb.v
+++ /dev/null
@@ -1,298 +0,0 @@
-`default_nettype none
-/*	
-	StriVe housekeeping SPI testbench.
-*/
-`define GL
-
-`timescale 1 ns / 1 ps
-
-`include "caravel.v"
-`include "spiflash.v"
-`include "tbuart.v"
-
-module hkspi_tb;
-	reg clock;
-	reg SDI, CSB, SCK, RSTB;
-	reg power1, power2;
-
-	wire gpio;
-	wire [15:0] checkbits;
-	wire [37:0] mprj_io;
-	wire uart_tx;
-	wire uart_rx;
-
-	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-	wire flash_io2;
-	wire flash_io3;
-
-	wire SDO;
-
-	always #10 clock <= (clock === 1'b0);
-
-	initial begin
-		clock = 0;
-	end
-
-	initial begin		// Power-up sequence
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		#200;
-		power1 <= 1'b1;
-		#200;
-		power2 <= 1'b1;
-	end
-
-    // The main testbench is here.  Put the housekeeping SPI into
-    // pass-thru mode and read several bytes from the flash SPI.
-
-    // First define tasks for SPI functions
-
-	task start_csb;
-	    begin
-		SCK <= 1'b0;
-		SDI <= 1'b0;
-		CSB <= 1'b0;
-		#50;
-	    end
-	endtask
-
-	task end_csb;
-	    begin
-		SCK <= 1'b0;
-		SDI <= 1'b0;
-		CSB <= 1'b1;
-		#50;
-	    end
-	endtask
-
-	task write_byte;
-	    input [7:0] odata;
-	    begin
-		SCK <= 1'b0;
-		for (i=7; i >= 0; i--) begin
-		    #50;
-		    SDI <= odata[i];
-                    #50;
-		    SCK <= 1'b1;
-                    #100;
-		    SCK <= 1'b0;
-		end
-	    end
-	endtask
-
-	task read_byte;
-	    output [7:0] idata;
-	    begin
-		SCK <= 1'b0;
-		SDI <= 1'b0;
-		for (i=7; i >= 0; i--) begin
-		    #50;
-                    idata[i] = SDO;
-                    #50;
-		    SCK <= 1'b1;
-                    #100;
-		    SCK <= 1'b0;
-		end
-	    end
-	endtask
-
-	task read_write_byte
-	    (input [7:0] odata,
-	    output [7:0] idata);
-	    begin
-		SCK <= 1'b0;
-		for (i=7; i >= 0; i--) begin
-		    #50;
-		    SDI <= odata[i];
-                    idata[i] = SDO;
-                    #50;
-		    SCK <= 1'b1;
-                    #100;
-		    SCK <= 1'b0;
-		end
-	    end
-	endtask
-	
-	integer i;
-
-    // Now drive the digital signals on the housekeeping SPI
-	reg [7:0] tbdata;
-
-	initial begin
-	    $dumpfile("hkspi.vcd");
-	    $dumpvars(0, hkspi_tb);
-
-	    CSB <= 1'b1;
-	    SCK <= 1'b0;
-	    SDI <= 1'b0;
-	    RSTB <= 1'b0;
-
-	    // Delay, then bring chip out of reset
-	    #1000;
-	    RSTB <= 1'b1;
-	    #2000;
-
-            // First do a normal read from the housekeeping SPI to
-	    // make sure the housekeeping SPI works.
-
-	    start_csb();
-	    write_byte(8'h40);	// Read stream command
-	    write_byte(8'h03);	// Address (register 3 = product ID)
-	    read_byte(tbdata);
-	    end_csb();
-	    #10;
-	    $display("Read data = 0x%02x (should be 0x10)", tbdata);
-
-	    // Toggle external reset
-	    start_csb();
-	    write_byte(8'h80);	// Write stream command
-	    write_byte(8'h07);	// Address (register 7 = external reset)
-	    write_byte(8'h01);	// Data = 0x01 (apply external reset)
-	    end_csb();
-
-	    start_csb();
-	    write_byte(8'h80);	// Write stream command
-	    write_byte(8'h07);	// Address (register 7 = external reset)
-	    write_byte(8'h00);	// Data = 0x00 (release external reset)
-	    end_csb();
-
-	    // Read all registers (0 to 18)
-	    start_csb();
-	    write_byte(8'h40);	// Read stream command
-	    write_byte(8'h00);	// Address (register 3 = product ID)
-	    read_byte(tbdata);
-
-	    $display("Read register 0 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read register 1 = 0x%02x (should be 0x04)", tbdata);
-		if(tbdata !== 8'h04) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read register 2 = 0x%02x (should be 0x56)", tbdata);
-		if(tbdata !== 8'h56) begin $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish; end
-	    read_byte(tbdata);
-	    $display("Read register 3 = 0x%02x (should be 0x10)", tbdata);
-		if(tbdata !== 8'h10) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read register 4 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read register 5 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read register 6 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read register 7 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read register 8 = 0x%02x (should be 0x02)", tbdata);
-		if(tbdata !== 8'h02) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read register 9 = 0x%02x (should be 0x01)", tbdata);
-		if(tbdata !== 8'h01) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read register 10 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read register 11 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read register 12 = 0x%02x (should be 0x00)", tbdata);
-		if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read register 13 = 0x%02x (should be 0xff)", tbdata);
-		if(tbdata !== 8'hff) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read register 14 = 0x%02x (should be 0xef)", tbdata);
-		if(tbdata !== 8'hef) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read register 15 = 0x%02x (should be 0xff)", tbdata);
-		if(tbdata !== 8'hff) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read register 16 = 0x%02x (should be 0x03)", tbdata);
-		if(tbdata !== 8'h03) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read register 17 = 0x%02x (should be 0x12)", tbdata);
-		if(tbdata !== 8'h12) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read register 18 = 0x%02x (should be 0x04)", tbdata);
-		if(tbdata !== 8'h04) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-		
-        end_csb();
-
-		$display("Monitor: Test HK SPI (GL) Passed");
-
-	    #10000;
- 	    $finish;
-	end
-
-	wire VDD3V3;
-	wire VDD1V8;
-	wire VSS;
-
-	assign VDD3V3 = power1;
-	assign VDD1V8 = power2;
-	assign VSS = 1'b0;
-
-	wire hk_sck;
-	wire hk_csb;
-	wire hk_sdi;
-
-	assign hk_sck = SCK;
-	assign hk_csb = CSB;
-	assign hk_sdi = SDI;
-
-	assign checkbits = mprj_io[31:16];
-	assign uart_tx = mprj_io[6];
-	assign mprj_io[5] = uart_rx;
-	assign mprj_io[4] = hk_sck;
-	assign mprj_io[3] = hk_csb;
-	assign mprj_io[2] = hk_sdi;
-	assign SDO = mprj_io[1];
-	
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (VDD3V3),
-		.vdda2    (VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (VDD1V8),
-		.vccd2	  (VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock	  (clock),
-		.gpio     (gpio),
-		.mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("hkspi.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-
-	tbuart tbuart (
-		.ser_rx(uart_tx)
-	);
-		
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/mem/Makefile b/verilog/dv/caravel/mgmt_soc/mem/Makefile
index 0bcd880..d50e261 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/mem/Makefile
@@ -1,12 +1,16 @@
 
 FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
 GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
 PDK_PATH?=/ef/tech/SW/sky130A
 
+SIM?=RTL
+
 .SUFFIXES:
 
 PATTERN = mem
@@ -16,9 +20,15 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
 	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
+	$< -o $@ 
+else  
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
 
 %.vcd: %.vvp
 	vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem.c b/verilog/dv/caravel/mgmt_soc/mem/mem.c
index 7fbf8ad..f4e2ea3 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/mem.c
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem.c
@@ -72,5 +72,4 @@
 	    reg_mprj_datal = 0xAB100000;
 
     reg_mprj_datal = 0xAB110000;
-}
-
+}
\ No newline at end of file
diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
index 8df4d4b..a82184c 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
@@ -59,7 +59,11 @@
 			//$display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test MEM (RTL) Failed");
+		`ifdef GL
+			$display ("Monitor: Timeout, Test MEM (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test MEM (RTL) Failed");
+		`endif
 		$display("%c[0m",27);
 		$finish;
 	end
@@ -86,36 +90,60 @@
 		end
 		else if(checkbits == 16'hAB40) begin
 			$display("%c[1;31m",27);
-			$display("Monitor: Test MEM (RTL) [word rw] failed");
+			`ifdef GL
+				$display("Monitor: Test MEM (GL) [word rw] failed");
+			`else
+				$display("Monitor: Test MEM (RTL) [word rw] failed");
+			`endif
 			$display("%c[0m",27);
 			$finish;
 		end
 		else if(checkbits == 16'hAB41) begin
-			$display("Monitor: Test MEM (RTL) [word rw]  passed");
+			`ifdef GL
+				$display("Monitor: Test MEM (GL) [word rw]  passed");
+			`else
+				$display("Monitor: Test MEM (RTL) [word rw]  passed");
+			`endif
 		end
 		else if(checkbits == 16'hA020) begin
 			$display("Mem Test (short rw) started");
 		end
 		else if(checkbits == 16'hAB20) begin
 			$display("%c[1;31m",27);
-			$display("Monitor: Test MEM (RTL) [short rw] failed");
+			`ifdef GL
+				$display("Monitor: Test MEM (GL) [short rw] failed");
+			`else
+				$display("Monitor: Test MEM (RTL) [short rw] failed");
+			`endif
 			$display("%c[0m",27);
 			$finish;
 		end
 		else if(checkbits == 16'hAB21) begin
-			$display("Monitor: Test MEM (RTL) [short rw]  passed");
+			`ifdef GL
+				$display("Monitor: Test MEM (GL) [short rw]  passed");
+			`else
+				$display("Monitor: Test MEM (RTL) [short rw]  passed");
+			`endif
 		end
 		else if(checkbits == 16'hA010) begin
 			$display("Mem Test (byte rw) started");
 		end
 		else if(checkbits == 16'hAB10) begin
 			$display("%c[1;31m",27);
-			$display("Monitor: Test MEM (RTL) [byte rw] failed");
+			`ifdef GL
+				$display("Monitor: Test MEM (GL) [byte rw] failed");
+			`else
+				$display("Monitor: Test MEM (RTL) [byte rw] failed");
+			`endif
 			$display("%c[0m",27);
 			$finish;
 		end
 		else if(checkbits == 16'hAB11) begin
-			$display("Monitor: Test MEM (RTL) [byte rw] passed");
+			`ifdef GL
+				$display("Monitor: Test MEM (GL) [byte rw] passed");
+			`else
+				$display("Monitor: Test MEM (RTL) [byte rw] passed");
+			`endif
 			$finish;
 		end
 
@@ -129,6 +157,8 @@
 	assign VDD3V3 = power1;
 	assign VDD1V8 = power2;
 
+	assign mprj_io[3] = 1'b1;       // Force CSB high.
+
 	caravel uut (
 		.vddio	  (VDD3V3),
 		.vssio	  (VSS),
diff --git a/verilog/dv/caravel/mgmt_soc/mem_gl/Makefile b/verilog/dv/caravel/mgmt_soc/mem_gl/Makefile
deleted file mode 100644
index 16e340e..0000000
--- a/verilog/dv/caravel/mgmt_soc/mem_gl/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-FIRMWARE_PATH = ../..
-VERILOG_PATH = ../../../..
-RTL_PATH = $(VERILOG_PATH)/rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../ 
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = mem
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -DUSE_POWER_PINS -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
-	$< -o $@
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
-	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/mem_gl/mem.c b/verilog/dv/caravel/mgmt_soc/mem_gl/mem.c
deleted file mode 100644
index 7fbf8ad..0000000
--- a/verilog/dv/caravel/mgmt_soc/mem_gl/mem.c
+++ /dev/null
@@ -1,76 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-/*
-	Memory Test
-	It uses GPIO to flag the success or failure of the test
-*/
-unsigned int ints[10];
-unsigned short shorts[10];
-unsigned char bytes[10];
-
-void main()
-{
-    int i;
-
-    /* Upper 16 user area pins are configured to be GPIO output */
-
-    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    // Apply configuration
-    reg_mprj_xfer = 1;
-    while (reg_mprj_xfer == 1);
-
-    // start test
-    reg_mprj_datal = 0xA0400000;
-
-    // Test Word R/W
-    for (i=0; i<10; i++)
-	ints[i] = i*5000 + 10000;
-	
-    for (i=0; i<10; i++)
-	if ((i*5000+10000) != ints[i])
-	    reg_mprj_datal = 0xAB400000;
-
-    reg_mprj_datal = 0xAB410000;
-	
-    // Test Half Word R/W
-    reg_mprj_datal = 0xA0200000;
-    for (i=0; i<10; i++)
-	shorts[i] = i*500 + 100;
-	
-    for(i=0; i<10; i++)
-	if((i*500+100) != shorts[i])
-	    reg_mprj_datal = 0xAB200000;
-
-    reg_mprj_datal = 0xAB210000;
-
-    // Test byte R/W
-    reg_mprj_datal = 0xA0100000;
-    for(i=0; i<10; i++)
-	bytes[i] = i*5 + 10;
-	
-    for(i=0; i<10; i++)
-	if((i*5+10) != bytes[i])
-	    reg_mprj_datal = 0xAB100000;
-
-    reg_mprj_datal = 0xAB110000;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/mem_gl/mem_tb.v b/verilog/dv/caravel/mgmt_soc/mem_gl/mem_tb.v
deleted file mode 100644
index c633468..0000000
--- a/verilog/dv/caravel/mgmt_soc/mem_gl/mem_tb.v
+++ /dev/null
@@ -1,171 +0,0 @@
-`default_nettype none
-/*
- *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
- *
- *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
- *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module mem_tb;
-	reg clock;
-	reg RSTB;
-	reg power1, power2;
-
-	wire gpio;
-        wire [15:0] checkbits;
-	wire [37:0] mprj_io;
-	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-
-	assign checkbits = mprj_io[31:16];
-
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
-
-	always #10 clock <= (clock === 1'b0);
-
-	initial begin
-		clock = 0;
-	end
-
-	initial begin
-		$dumpfile("mem.vcd");
-		$dumpvars(0, mem_tb);
-
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (100) begin
-			repeat (1000) @(posedge clock);
-			//$display("+1000 cycles");
-		end
-		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test MEM (GL) Failed");
-		$display("%c[0m",27);
-		$finish;
-	end
-
-	initial begin
-		RSTB <= 1'b0;
-		#1000;
-		RSTB <= 1'b1;	    // Release reset
-		#2000;
-	end
-
-	initial begin		// Power-up sequence
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		#200;
-		power1 <= 1'b1;
-		#200;
-		power2 <= 1'b1;
-	end
-
-	always @(checkbits) begin
-		if(checkbits == 16'hA040) begin
-			$display("Mem Test (word rw) started");
-		end
-		else if(checkbits == 16'hAB40) begin
-			$display("%c[1;31m",27);
-			$display("Monitor: Test MEM (GL) [word rw] failed");
-			$display("%c[0m",27);
-			$finish;
-		end
-		else if(checkbits == 16'hAB41) begin
-			$display("Monitor: Test MEM (GL) [word rw]  passed");
-		end
-		else if(checkbits == 16'hA020) begin
-			$display("Mem Test (short rw) started");
-		end
-		else if(checkbits == 16'hAB20) begin
-			$display("%c[1;31m",27);
-			$display("Monitor: Test MEM (GL) [short rw] failed");
-			$display("%c[0m",27);
-			$finish;
-		end
-		else if(checkbits == 16'hAB21) begin
-			$display("Monitor: Test MEM (GL) [short rw]  passed");
-		end
-		else if(checkbits == 16'hA010) begin
-			$display("Mem Test (byte rw) started");
-		end
-		else if(checkbits == 16'hAB10) begin
-			$display("%c[1;31m",27);
-			$display("Monitor: Test MEM (GL) [byte rw] failed");
-			$display("%c[0m",27);
-			$finish;
-		end
-		else if(checkbits == 16'hAB11) begin
-			$display("Monitor: Test MEM (GL) [byte rw] passed");
-			$finish;
-		end
-
-	end
-
-	wire VDD3V3;
-	wire VDD1V8;
-	wire VSS;
-
-	assign VSS = 1'b0;
-	assign VDD3V3 = power1;
-	assign VDD1V8 = power2;
-
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (VDD3V3),
-		.vdda2    (VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (VDD1V8),
-		.vccd2	  (VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock	  (clock),
-		.gpio     (gpio),
-		.mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("mem.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
index d477f20..1f5ee62 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
@@ -1,6 +1,7 @@
 
 FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
@@ -8,6 +9,8 @@
 GCC_PREFIX?=riscv32-unknown-elf
 PDK_PATH?=/ef/tech/SW/sky130A
 
+SIM?=RTL
+
 .SUFFIXES:
 
 PATTERN = mprj_ctrl
@@ -17,9 +20,15 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
 	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
+	$< -o $@ 
+else  
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
 
 %.vcd: %.vvp
 	vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
index 75b41d4..4625f32 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
@@ -46,7 +46,7 @@
     reg_mprj_io_6  = GPIO_MODE_USER_STD_OUTPUT;
     reg_mprj_io_5  = GPIO_MODE_USER_STD_OUTPUT;
     reg_mprj_io_4  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
+    // reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
     reg_mprj_io_2  = GPIO_MODE_USER_STD_OUTPUT;
     reg_mprj_io_1  = GPIO_MODE_USER_STD_OUTPUT;
     reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
index b1d4f2d..ffc74a9 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -40,8 +40,12 @@
 			$display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test User Project (RTL) Failed");
-		 $display("%c[0m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test User Project (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test User Project (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
 		$finish;
 	end
 
@@ -75,9 +79,14 @@
 			$display("%c[0m",27);
 			$finish;
         	end else if(checkbits == 4'hd) begin
+
 			$display("Monitor: power control R/W passed (check 13)");
-            		$display("Monitor: User Project control (RTL) test passed.");
-            		$finish;
+			`ifdef GL
+            	$display("Monitor: User Project control (GL) test passed.");
+			`else
+			    $display("Monitor: User Project control (RTL) test passed.");
+			`endif
+            $finish;
         	end			
 	end
 
@@ -109,6 +118,8 @@
 	assign VDD1V8 = power2;
 	assign VSS = 1'b0;
 
+	assign user_io[3] = 1'b1;
+	
 	caravel uut (
 		.vddio	  (VDD3V3),
 		.vssio	  (VSS),
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl_gl/Makefile b/verilog/dv/caravel/mgmt_soc/mprj_ctrl_gl/Makefile
deleted file mode 100644
index b1d5ec9..0000000
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl_gl/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-FIRMWARE_PATH = ../..
-VERILOG_PATH = ../../../..
-RTL_PATH = $(VERILOG_PATH)/rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../ 
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = mprj_ctrl
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -DUSE_POWER_PINS -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
-	$< -o $@
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
-	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl_gl/mprj_ctrl.c b/verilog/dv/caravel/mgmt_soc/mprj_ctrl_gl/mprj_ctrl.c
deleted file mode 100644
index 75b41d4..0000000
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl_gl/mprj_ctrl.c
+++ /dev/null
@@ -1,91 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-/*
- *	User Project IO Control Test
- */
-
-void main()
-{
-    /* All GPIO pins are configured to be output	*/
-    /* The lower 28 bits are connected to the user	*/
-    /* project to output the counter result, and the	*/
-    /* upper 4 bits are connected to the management	*/
-    /* SoC to apply values that can be flagged by the	*/
-    /* testbench for specific benchmark tests.		*/
-
-    /* GPIOs 31 to 16 are connected to the management SoC */
-    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    /* GPIOs 27 to 0 are connected to the user area */
-    reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_9  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_8  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_7  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_6  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_5  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_4  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_2  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_1  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
-
-    // Apply configuration
-    reg_mprj_xfer = 1;
-    while (reg_mprj_xfer == 1);
-
-    reg_mprj_datal = 0;
-
-    // start test
-    reg_mprj_datal = 0x50000000;
-
-    // Write to IO Control
-    reg_mprj_io_0 = 0x004F;
-    if (reg_mprj_io_0 != 0x004F)
-	reg_mprj_datal = 0x60000000;
-     else
-	reg_mprj_datal = 0x70000000;
-
-    // Write to IO Control 
-    reg_mprj_io_1 = 0x005F;
-    if (reg_mprj_io_1 != 0x005F)
-	reg_mprj_datal = 0x80000000;
-    else
-	reg_mprj_datal = 0x90000000;
-
-    // Write to IO Control
-    reg_mprj_io_2 = 0x006F;
-    if (reg_mprj_io_2 != 0x006F)
-	reg_mprj_datal = 0xA0000000;
-    else
-	reg_mprj_datal = 0xb0000000;
-
-    // Write to IO Control (NOTE:  Only 13 bits are valid)
-    reg_mprj_io_3 = 0xF0F5;
-    if (reg_mprj_io_3 != 0x10F5)
-	reg_mprj_datal = 0xc0000000;
-    else
-	reg_mprj_datal = 0xd0000000;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl_gl/mprj_ctrl_tb.v b/verilog/dv/caravel/mgmt_soc/mprj_ctrl_gl/mprj_ctrl_tb.v
deleted file mode 100644
index a907b55..0000000
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl_gl/mprj_ctrl_tb.v
+++ /dev/null
@@ -1,151 +0,0 @@
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module mprj_ctrl_tb;
-	reg clock;
-	reg RSTB;
-	reg power1, power2;
-
-	wire gpio;
-	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-	wire [37:0] user_io;
-	wire SDO;
-
-	wire [3:0] checkbits;
-
-	assign checkbits = user_io[31:28];
-
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
-
-	always #10 clock <= (clock === 1'b0);
-
-	initial begin
-		clock = 0;
-	end
-
-	initial begin
-		$dumpfile("mprj_ctrl.vcd");
-		$dumpvars(0, mprj_ctrl_tb);
-		repeat (25) begin
-			repeat (1000) @(posedge clock);
-			$display("+1000 cycles");
-		end
-		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test User Project (GL) Failed");
-		 $display("%c[0m",27);
-		$finish;
-	end
-
-	always @(checkbits) begin
-		if(checkbits == 4'h5) begin
-			$display("User Project control Test started");
-		end else if(checkbits == 4'h6) begin
-			$display("%c[1;31m",27);
-			$display("Monitor: IO control R/W failed (check 6)");
-			$display("%c[0m",27);
-			$finish;
-		end else if(checkbits == 4'h7) begin
-			$display("Monitor: IO control R/W passed (check 7)");
-		end else if(checkbits == 4'h8) begin
-            		$display("%c[1;31m",27);
-			$display("Monitor: power control R/W failed (check 8)");
-			$display("%c[0m",27);
-			$finish;
-        	end else if(checkbits == 4'h9) begin
-			$display("Monitor: power control R/W passed (check 9)");
-		end else if(checkbits == 4'ha) begin
-            		$display("%c[1;31m",27);
-			$display("Monitor: power control R/W failed (check 10)");
-			$display("%c[0m",27);
-			$finish;
-        	end else if(checkbits == 4'hb) begin
-			$display("Monitor: power control R/W passed (check 11)");
-		end else if(checkbits == 4'hc) begin
-            		$display("%c[1;31m",27);
-			$display("Monitor: power control R/W failed (check 12)");
-			$display("%c[0m",27);
-			$finish;
-        	end else if(checkbits == 4'hd) begin
-			$display("Monitor: power control R/W passed (check 13)");
-            		$display("Monitor: User Project control (GL) test passed.");
-            		$finish;
-        	end			
-	end
-
-	initial begin
-		RSTB <= 1'b0;
-		#1000;
-		RSTB <= 1'b1;	    // Release reset
-		#2000;
-	end
-
-	initial begin
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		#200;
-		power1 <= 1'b1;
-		#200;
-		power2 <= 1'b1;
-	end
-
-	always @(gpio) begin
-		#1 $display("GPIO state = %b ", gpio);
-	end
-
-	wire VDD3V3;
-	wire VDD1V8;
-	wire VSS;
-	
-	assign VDD3V3 = power1;
-	assign VDD1V8 = power2;
-	assign VSS = 1'b0;
-
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (VDD3V3),
-		.vdda2    (VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (VDD1V8),
-		.vccd2	  (VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock	   (clock),
-		.gpio      (gpio),
-		.mprj_io   (user_io),
-		.flash_csb (flash_csb),
-		.flash_clk (flash_clk),
-		.flash_io0 (flash_io0),
-		.flash_io1 (flash_io1),
-		.resetb	   (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("mprj_ctrl.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile b/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile
index 92919b5..4969c6a 100644
--- a/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile
@@ -1,6 +1,7 @@
 # ---- Test patterns for project striVe ----
 FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
@@ -8,6 +9,8 @@
 GCC_PREFIX?=riscv32-unknown-elf
 PDK_PATH?=/ef/tech/SW/sky130A
 
+SIM?=RTL
+
 .SUFFIXES:
 
 PATTERN = pass_thru
@@ -17,9 +20,15 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
 	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
+	$< -o $@ 
+else  
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
 
 %.vcd: %.vvp
 	vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
index aab7a74..8413e85 100644
--- a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
@@ -146,7 +146,13 @@
 	    end_csb();
 	    #10;
 	    $display("Read data = 0x%02x (should be 0x10)", tbdata);
-	    if(tbdata !== 8'h10) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+	    if(tbdata !== 8'h10) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
 
 	    start_csb();
 	    write_byte(8'hc4);	// Pass-thru mode
@@ -157,28 +163,76 @@
 
 	    read_byte(tbdata);
 	    $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
-	    if(tbdata !== 8'h93) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+	    if(tbdata !== 8'h93) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
-	    if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+	    if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
-	    if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+	    if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
-	    if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+	    if(tbdata !== 8'h00) begin
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
-	    if(tbdata !== 8'h93) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+	    if(tbdata !== 8'h93) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read flash data = 0x%02x (should be 0x01)", tbdata);
-	    if(tbdata !== 8'h01) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+	    if(tbdata !== 8'h01) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
-	    if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+	    if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
 	    read_byte(tbdata);
 	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
-	    if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+	    if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
 
 	    end_csb();
 
@@ -194,10 +248,20 @@
 	    end_csb();
 	    #10;
 	    $display("Read data = 0x%02x (should be 0x10)", tbdata);
-	    if(tbdata !== 8'h10) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+	    if(tbdata !== 8'h10) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
 
-	    $display("Monitor: Test HK SPI Pass-thru (RTL) Passed");
-
+		`ifdef GL
+	    	$display("Monitor: Test HK SPI Pass-thru (GL) Passed");
+		`else
+			$display("Monitor: Test HK SPI Pass-thru (RTL) Passed");
+		`endif
+		
 	    #10000;
  	    $finish;
 	end
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru_gl/Makefile b/verilog/dv/caravel/mgmt_soc/pass_thru_gl/Makefile
deleted file mode 100644
index f043a9a..0000000
--- a/verilog/dv/caravel/mgmt_soc/pass_thru_gl/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-FIRMWARE_PATH = ../..
-VERILOG_PATH = ../../../..
-RTL_PATH = $(VERILOG_PATH)/rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../ 
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = pass_thru
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -DUSE_POWER_PINS -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
-	$< -o $@
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
-	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru_gl/pass_thru.c b/verilog/dv/caravel/mgmt_soc/pass_thru_gl/pass_thru.c
deleted file mode 100644
index d31b31f..0000000
--- a/verilog/dv/caravel/mgmt_soc/pass_thru_gl/pass_thru.c
+++ /dev/null
@@ -1,74 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-void putchar(char c)
-{
-	if (c == '\n')
-		putchar('\r');
-	reg_uart_data = c;
-}
-
-void print(const char *p)
-{
-	while (*p)
-		putchar(*(p++));
-}
-
-// --------------------------------------------------------
-
-void main()
-{
-    // This program is just to keep the processor busy while the
-    // housekeeping SPI is being accessed. to show that the
-    // processor is halted while the SPI is accessing the
-    // flash SPI in pass-through mode.
-
-    // Configure I/O:  High 16 bits of user area used for a 16-bit
-    // word to write and be detected by the testbench verilog.
-    // Only serial Tx line is used in this testbench.  It connects
-    // to mprj_io[6].  Since all lines of the chip are input or
-    // high impedence on startup, the I/O has to be configured
-    // for output
-
-    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    // Apply configuration
-    reg_mprj_xfer = 1;
-    while (reg_mprj_xfer == 1);
-
-    // Start test
-    reg_mprj_datal = 0xa0000000;
-
-    // Set clock to 64 kbaud and enable the UART
-    reg_uart_clkdiv = 625;
-    reg_uart_enable = 1;
-
-    // Test in progress
-    reg_mprj_datal = 0xa5000000;
-
-    // Test message
-    print("Test message\n");
-
-    // End test
-    reg_mprj_datal = 0xab000000;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru_gl/pass_thru_tb.v b/verilog/dv/caravel/mgmt_soc/pass_thru_gl/pass_thru_tb.v
deleted file mode 100644
index e2587ee..0000000
--- a/verilog/dv/caravel/mgmt_soc/pass_thru_gl/pass_thru_tb.v
+++ /dev/null
@@ -1,272 +0,0 @@
-`default_nettype none
-/*	
- *	StriVe housekeeping pass-thru mode SPI testbench.
- */
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-`include "tbuart.v"
-
-module pass_thru_tb;
-	reg clock;
-	reg SDI, CSB, SCK, RSTB;
-	reg power1, power2;
-
-	wire gpio;
-	wire [15:0] checkbits;
-	wire [37:0] mprj_io;
-	wire uart_tx;
-	wire uart_rx;
-
-	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-	wire flash_io2;
-	wire flash_io3;
-
-	wire SDO;
-
-	always #10 clock <= (clock === 1'b0);
-
-	initial begin
-		clock = 0;
-	end
-
-	initial begin		// Power-up sequence
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		#200;
-		power1 <= 1'b1;
-		#200;
-		power2 <= 1'b1;
-	end
-
-    // The main testbench is here.  Put the housekeeping SPI into
-    // pass-thru mode and read several bytes from the flash SPI.
-
-    // First define tasks for SPI functions
-
-	task start_csb;
-	    begin
-		SCK <= 1'b0;
-		SDI <= 1'b0;
-		CSB <= 1'b0;
-		#50;
-	    end
-	endtask
-
-	task end_csb;
-	    begin
-		SCK <= 1'b0;
-		SDI <= 1'b0;
-		CSB <= 1'b1;
-		#50;
-	    end
-	endtask
-
-	task write_byte;
-	    input [7:0] odata;
-	    begin
-		SCK <= 1'b0;
-		for (i=7; i >= 0; i--) begin
-		    #50;
-		    SDI <= odata[i];
-                    #50;
-		    SCK <= 1'b1;
-                    #100;
-		    SCK <= 1'b0;
-		end
-	    end
-	endtask
-
-	task read_byte;
-	    output [7:0] idata;
-	    begin
-		SCK <= 1'b0;
-		SDI <= 1'b0;
-		for (i=7; i >= 0; i--) begin
-		    #50;
-                    idata[i] = SDO;
-                    #50;
-		    SCK <= 1'b1;
-                    #100;
-		    SCK <= 1'b0;
-		end
-	    end
-	endtask
-
-	task read_write_byte
-	    (input [7:0] odata,
-	    output [7:0] idata);
-	    begin
-		SCK <= 1'b0;
-		for (i=7; i >= 0; i--) begin
-		    #50;
-		    SDI <= odata[i];
-                    idata[i] = SDO;
-                    #50;
-		    SCK <= 1'b1;
-                    #100;
-		    SCK <= 1'b0;
-		end
-	    end
-	endtask
-	
-	integer i;
-
-    // Now drive the digital signals on the housekeeping SPI
-	reg [7:0] tbdata;
-
-	initial begin
-	    $dumpfile("pass_thru.vcd");
-	    $dumpvars(0, pass_thru_tb);
-
-	    CSB <= 1'b1;
-	    SCK <= 1'b0;
-	    SDI <= 1'b0;
-	    RSTB <= 1'b0;
-
-	    #2000;
-
-	    RSTB <= 1'b1;
-
-	    // Wait on start of program execution
-	    wait(checkbits == 16'hA000);
-
-            // First do a normal read from the housekeeping SPI to
-	    // make sure the housekeeping SPI works.
-
-	    start_csb();
-	    write_byte(8'h40);	// Read stream command
-	    write_byte(8'h03);	// Address (register 3 = product ID)
-	    read_byte(tbdata);
-	    end_csb();
-	    #10;
-	    $display("Read data = 0x%02x (should be 0x10)", tbdata);
-	    if(tbdata !== 8'h10) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
-
-	    start_csb();
-	    write_byte(8'hc4);	// Pass-thru mode
-	    write_byte(8'h03);	// Command 03 (read values w/3-byte address
-	    write_byte(8'h00);	// Address is next three bytes (0x000000)
-	    write_byte(8'h00);
-	    write_byte(8'h00);
-
-	    read_byte(tbdata);
-	    $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
-	    if(tbdata !== 8'h93) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
-	    if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
-	    if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
-	    if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
-	    if(tbdata !== 8'h93) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read flash data = 0x%02x (should be 0x01)", tbdata);
-	    if(tbdata !== 8'h01) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
-	    if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
-	    read_byte(tbdata);
-	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
-	    if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
-
-	    end_csb();
-
-	    // Wait for processor to restart
-	    wait(checkbits == 16'hA000);
-
-	    // Read product ID register again
-
-	    start_csb();
-	    write_byte(8'h40);	// Read stream command
-	    write_byte(8'h03);	// Address (register 3 = product ID)
-	    read_byte(tbdata);
-	    end_csb();
-	    #10;
-	    $display("Read data = 0x%02x (should be 0x10)", tbdata);
-	    if(tbdata !== 8'h10) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
-
-	    $display("Monitor: Test HK SPI Pass-thru (GL) Passed");
-
-	    #10000;
- 	    $finish;
-	end
-
-	wire VDD3V3;
-	wire VDD1V8;
-	wire VSS;
-
-	assign VDD3V3 = power1;
-	assign VDD1V8 = power2;
-	assign VSS = 1'b0;
-
-	wire hk_sck;
-	wire hk_csb;
-	wire hk_sdi;
-
-	assign hk_sck = SCK;
-	assign hk_csb = CSB;
-	assign hk_sdi = SDI;
-
-	assign checkbits = mprj_io[31:16];
-	assign uart_tx = mprj_io[6];
-	assign mprj_io[5] = uart_rx;
-	assign mprj_io[4] = hk_sck;
-	assign mprj_io[3] = hk_csb;
-	assign mprj_io[2] = hk_sdi;
-	assign SDO = mprj_io[1];
-	
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (VDD3V3),
-		.vdda2    (VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (VDD1V8),
-		.vccd2	  (VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock	  (clock),
-		.gpio     (gpio),
-		.mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("pass_thru.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-
-	tbuart tbuart (
-		.ser_rx(uart_tx)
-	);
-		
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/perf/Makefile b/verilog/dv/caravel/mgmt_soc/perf/Makefile
index 1fdfeae..c08b51f 100644
--- a/verilog/dv/caravel/mgmt_soc/perf/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/perf/Makefile
@@ -1,4 +1,6 @@
 FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
 RTL_PATH = ../../../../rtl
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
@@ -7,6 +9,8 @@
 GCC_PREFIX?=riscv32-unknown-elf
 PDK_PATH?=/ef/tech/SW/sky130A
 
+SIM?=RTL
+
 .SUFFIXES:
 
 PATTERN = perf
@@ -16,9 +20,15 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
 	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
+	$< -o $@ 
+else  
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
 	
 %.vcd: %.vvp
 	vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
index dac5af4..c086226 100644
--- a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
@@ -63,7 +63,11 @@
 			kcycles <= kcycles + 1;
 		end
 		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test Performance (RTL) Failed");
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Performance (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Performance (RTL) Failed");
+		`endif
 		$display("%c[0m",27);
 		$finish;
 	end
@@ -92,7 +96,11 @@
 		end
 		else if(checkbits == 16'hAB00) begin
 			//$display("Monitor: number of cycles/100 iterations: %d KCycles", kcycles);
-			$display("Monitor: Test Performance (RTL) passed [%0d KCycles]", kcycles);
+			`ifdef GL
+				$display("Monitor: Test Performance (GL) passed [%0d KCycles]", kcycles);
+			`else
+				$display("Monitor: Test Performance (RTL) passed [%0d KCycles]", kcycles);
+			`endif
 			$finish;
 		end
 	end
@@ -105,6 +113,8 @@
 	assign VDD1V8 = power2;
 	assign VSS = 1'b0;
 
+	assign mprj_io[3] = 1'b1;       // Force CSB high.
+
 	caravel uut (
 		.vddio	  (VDD3V3),
 		.vssio	  (VSS),
diff --git a/verilog/dv/caravel/mgmt_soc/perf_gl/Makefile b/verilog/dv/caravel/mgmt_soc/perf_gl/Makefile
deleted file mode 100644
index f5e0730..0000000
--- a/verilog/dv/caravel/mgmt_soc/perf_gl/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-FIRMWARE_PATH = ../..
-VERILOG_PATH = ../../../..
-RTL_PATH = $(VERILOG_PATH)/rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../ 
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = perf
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -DUSE_POWER_PINS -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
-	$< -o $@
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
-	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/perf_gl/perf.c b/verilog/dv/caravel/mgmt_soc/perf_gl/perf.c
deleted file mode 100644
index 0d83518..0000000
--- a/verilog/dv/caravel/mgmt_soc/perf_gl/perf.c
+++ /dev/null
@@ -1,54 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-/*
-	Performance Test
-	It uses GPIO to flag the success or failure of the test
-*/
-unsigned int ints[50];
-unsigned short shorts[50];
-unsigned char bytes[50];
-
-int main()
-{
-    int i;
-    int sum = 0;
-
-    /* Upper 16 user area pins are configured to be GPIO output */
-
-    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    // Apply configuration
-    reg_mprj_xfer = 1;
-    while (reg_mprj_xfer == 1);
-
-    reg_mprj_datal = 0;
-
-    // start test
-    reg_mprj_datal = 0xA0000000;
-	
-    for (i=0; i<100; i++)
-        sum += (sum + i);
-    
-    reg_mprj_datal = 0xAB000000;
-    
-    return sum;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/perf_gl/perf_tb.v b/verilog/dv/caravel/mgmt_soc/perf_gl/perf_tb.v
deleted file mode 100644
index be9410a..0000000
--- a/verilog/dv/caravel/mgmt_soc/perf_gl/perf_tb.v
+++ /dev/null
@@ -1,147 +0,0 @@
-`default_nettype none
-/*
- *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
- *
- *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
- *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module perf_tb;
-	reg clock;
-	reg RSTB;
-	reg power1, power2;
-
-	wire gpio;
-	wire [15:0] checkbits;
-	wire [37:0] mprj_io;
-	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-
-	assign checkbits = mprj_io[31:16];
-
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
-
-	always #10 clock <= (clock === 1'b0);
-
-	initial begin
-		clock = 0;
-	end
-
-	reg [31:0] kcycles;
-
-	initial begin
-		$dumpfile("perf.vcd");
-		$dumpvars(0, perf_tb);
-
-		kcycles = 0;
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (150) begin
-			repeat (1000) @(posedge clock);
-			//$display("+1000 cycles");
-			kcycles <= kcycles + 1;
-		end
-		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test Performance (GL) Failed");
-		$display("%c[0m",27);
-		$finish;
-	end
-
-	initial begin
-		RSTB <= 1'b0;
-		#1000;
-		RSTB <= 1'b1;	    // Release reset
-		#2000;
-	end
-
-	initial begin			// Power-up sequence
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		#200;
-		power1 <= 1'b1;
-		#200;
-		power2 <= 1'b1;
-	end
-
-	always @(checkbits) begin
-		//#1 $display("GPIO state = %X ", gpio);
-		if(checkbits == 16'hA000) begin
-			kcycles = 0;
-			$display("Performance Test started");
-		end
-		else if(checkbits == 16'hAB00) begin
-			//$display("Monitor: number of cycles/100 iterations: %d KCycles", kcycles);
-			$display("Monitor: Test Performance (GL) passed [%0d KCycles]", kcycles);
-			$finish;
-		end
-	end
-	
-	wire VDD3V3;
-	wire VDD1V8;
-	wire VSS;
-
-	assign VDD3V3 = power1;
-	assign VDD1V8 = power2;
-	assign VSS = 1'b0;
-
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (VDD3V3),
-		.vdda2    (VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (VDD1V8),
-		.vccd2	  (VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock	  (clock),
-		.gpio     (gpio),
-		.mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("perf.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/pll/Makefile b/verilog/dv/caravel/mgmt_soc/pll/Makefile
index 4750a33..c60b5af 100644
--- a/verilog/dv/caravel/mgmt_soc/pll/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/pll/Makefile
@@ -1,5 +1,6 @@
 FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
@@ -7,6 +8,8 @@
 GCC_PREFIX?=riscv32-unknown-elf
 PDK_PATH?=/ef/tech/SW/sky130A
 
+SIM?=RTL
+
 .SUFFIXES:
 
 PATTERN = pll
@@ -16,9 +19,15 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -I $(PDK_PATH) -I $(BEHAVIOURAL_MODELS) \
-	-I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
 
 %.vcd: %.vvp
 	vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
index b0df093..b9a6dd8 100644
--- a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
@@ -42,7 +42,11 @@
 			$display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test PLL (RTL) Failed");
+		`ifdef GL
+			$display ("Monitor: Timeout, Test PLL (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test PLL (RTL) Failed");
+		`endif
 		 $display("%c[0m",27);
 		$finish;
 	end
@@ -50,7 +54,11 @@
 	// Monitor
 	initial begin
 	    wait(checkbits == 16'hA040);
-            $display("Monitor: Test PLL (RTL) Started");
+		`ifdef GL
+			$display("Monitor: Test PLL (GL) Started");
+		`else
+			$display("Monitor: Test PLL (RTL) Started");
+		`endif
 
 	    wait(checkbits == 16'hA041);
             // $display("   SPI value = 0x%x (should be 0x04)", spivalue);
@@ -66,7 +74,11 @@
             // end
 
 	    wait(checkbits == 16'hA090);
-            $display("Monitor: Test PLL (RTL) Passed");
+		`ifdef GL
+            $display("Monitor: Test PLL (GL) Passed");
+		`else
+		    $display("Monitor: Test PLL (RTL) Passed");
+		`endif
             $finish;
 	end
 
@@ -98,6 +110,8 @@
 	assign VDD1V8 = power2;
 	assign VSS = 1'b0;
 
+	assign mprj_io[3] = 1'b1;  // Force CSB high.
+
 	caravel uut (
 		.vddio	  (VDD3V3),
 		.vssio	  (VSS),
diff --git a/verilog/dv/caravel/mgmt_soc/pll_gl/Makefile b/verilog/dv/caravel/mgmt_soc/pll_gl/Makefile
deleted file mode 100644
index da4e1c4..0000000
--- a/verilog/dv/caravel/mgmt_soc/pll_gl/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-FIRMWARE_PATH = ../..
-VERILOG_PATH = ../../../..
-RTL_PATH = $(VERILOG_PATH)/rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../ 
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = pll
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -DUSE_POWER_PINS -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
-	$< -o $@
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
-	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/pll_gl/pll.c b/verilog/dv/caravel/mgmt_soc/pll_gl/pll.c
deleted file mode 100644
index b74860b..0000000
--- a/verilog/dv/caravel/mgmt_soc/pll_gl/pll.c
+++ /dev/null
@@ -1,105 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-/*
- *	PLL Test (self-switching)
- *	- Enables SPI master
- *	- Uses SPI master to internally access the housekeeping SPI
- *      - Switches PLL bypass
- *	- Changes PLL divider
- *
- * 	Tesbench mostly copied from sysctrl
- */
-void main()
-{
-    int i;
-
-    reg_mprj_datal = 0;
-
-    // Configure upper 16 bits of user GPIO for generating testbench
-    // checkpoints.
-
-    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    /* Apply configuration */
-    reg_mprj_xfer = 1;
-    while (reg_mprj_xfer == 1);
-
-    // Start test
-    reg_mprj_datal = 0xA0400000;
-
-    // Enable SPI master
-    // SPI master configuration bits:
-    // bits 7-0:	Clock prescaler value (default 2)
-    // bit  8:		MSB/LSB first (0 = MSB first, 1 = LSB first)
-    // bit  9:		CSB sense (0 = inverted, 1 = noninverted)
-    // bit 10:		SCK sense (0 = noninverted, 1 = inverted)
-    // bit 11:		mode (0 = read/write opposite edges, 1 = same edges)
-    // bit 12:		stream (1 = CSB ends transmission)
-    // bit 13:		enable (1 = enabled)
-    // bit 14:		IRQ enable (1 = enabled)
-    // bit 15:		Connect to housekeeping SPI (1 = connected)
-
-    reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
-					// connect to housekeeping SPI
-
-    // Apply stream read (0x40 + 0x03) and read back one byte 
-
-    reg_spimaster_config = 0xb002;	// Apply stream mode
-    reg_spimaster_data = 0x80;		// Write 0x80 (write mode)
-    reg_spimaster_data = 0x08;		// Write 0x18 (start address)
-    reg_spimaster_data = 0x01;		// Write 0x01 to PLL enable, no DCO mode
-    reg_spimaster_config = 0xa102;	// Release CSB (ends stream mode)
-
-    reg_spimaster_config = 0xb002;	// Apply stream mode
-    reg_spimaster_data = 0x80;		// Write 0x80 (write mode)
-    reg_spimaster_data = 0x11;		// Write 0x11 (start address)
-    reg_spimaster_data = 0x03;		// Write 0x03 to PLL output divider
-    reg_spimaster_config = 0xa102;	// Release CSB (ends stream mode)
-
-    reg_spimaster_config = 0xb002;	// Apply stream mode
-    reg_spimaster_data = 0x80;		// Write 0x80 (write mode)
-    reg_spimaster_data = 0x09;		// Write 0x09 (start address)
-    reg_spimaster_data = 0x00;		// Write 0x00 to clock from PLL (no bypass)
-    reg_spimaster_config = 0xa102;	// Release CSB (ends stream mode)
-
-    // Write checkpoint
-    reg_mprj_datal = 0xA0410000;
-
-    reg_spimaster_config = 0xb002;	// Apply stream mode
-    reg_spimaster_data = 0x80;		// Write 0x80 (write mode)
-    reg_spimaster_data = 0x12;		// Write 0x12 (start address)
-    reg_spimaster_data = 0x03;		// Write 0x03 to feedback divider (was 0x04)
-    reg_spimaster_config = 0xa102;	// Release CSB (ends stream mode)
-
-    // Write checkpoint
-    reg_mprj_datal = 0xA0420000;
-
-    reg_spimaster_config = 0xb002;	// Apply stream mode
-    reg_spimaster_data = 0x80;		// Write 0x80 (write mode)
-    reg_spimaster_data = 0x11;		// Write 0x11 (start address)
-    reg_spimaster_data = 0x04;		// Write 0x04 to PLL output divider
-    reg_spimaster_config = 0xa102;	// Release CSB (ends stream mode)
-
-    reg_spimaster_config = 0x2102;	// Release housekeeping SPI
-
-    // End test
-    reg_mprj_datal = 0xA0900000;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/pll_gl/pll_tb.v b/verilog/dv/caravel/mgmt_soc/pll_gl/pll_tb.v
deleted file mode 100644
index 149517a..0000000
--- a/verilog/dv/caravel/mgmt_soc/pll_gl/pll_tb.v
+++ /dev/null
@@ -1,140 +0,0 @@
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module pll_tb;
-	reg clock;
-	reg power1;
-	reg power2;
-	reg RSTB;
-
-	wire gpio;
-	wire [15:0] checkbits;
-	wire [7:0] spivalue;
-	wire [37:0] mprj_io;
-	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-	wire SDO;
-
-	assign checkbits = mprj_io[31:16];
-	assign spivalue  = mprj_io[15:8];
-
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
-
-	always #10 clock <= (clock === 1'b0);
-
-	initial begin
-		clock = 0;
-	end
-
-	initial begin
-		$dumpfile("pll.vcd");
-		$dumpvars(0, pll_tb);
-		repeat (25) begin
-			repeat (1000) @(posedge clock);
-			$display("+1000 cycles");
-		end
-		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test PLL (GL) Failed");
-		 $display("%c[0m",27);
-		$finish;
-	end
-
-	// Monitor
-	initial begin
-	    wait(checkbits == 16'hA040);
-            $display("Monitor: Test PLL (GL) Started");
-
-	    wait(checkbits == 16'hA041);
-            // $display("   SPI value = 0x%x (should be 0x04)", spivalue);
-            // if(spivalue !== 32'h04) begin
-            //     $display("Monitor: Test PLL (GL) Failed");
-            //     $finish;
-            // end
-	    wait(checkbits == 16'hA042);
-            // $display("   SPI value = 0x%x (should be 0x56)", spivalue);
-            // if(spivalue !== 32'h56) begin
-            //     $display("Monitor: Test PLL (GL) Failed");
-            //     $finish;
-            // end
-
-	    wait(checkbits == 16'hA090);
-            $display("Monitor: Test PLL (GL) Passed");
-            $finish;
-	end
-
-	initial begin
-		RSTB <= 1'b0;
-		#1000;
-		RSTB <= 1'b1;	    // Release reset
-		#2000;
-	end
-
-	initial begin
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		#200;
-		power1 <= 1'b1;
-		#200;
-		power2 <= 1'b1;
-	end
-
-	always @(checkbits) begin
-		#1 $display("GPIO state = %b ", checkbits);
-	end
-
-	wire VDD3V3;
-	wire VDD1V8;
-	wire VSS;
-	
-	assign VDD3V3 = power1;
-	assign VDD1V8 = power2;
-	assign VSS = 1'b0;
-
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (VDD3V3),
-		.vdda2    (VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (VDD1V8),
-		.vccd2	  (VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock    (clock),
-		.gpio     (gpio),
-		.mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("pll.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/storage/Makefile b/verilog/dv/caravel/mgmt_soc/storage/Makefile
index 2792ce9..dace1f7 100644
--- a/verilog/dv/caravel/mgmt_soc/storage/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/storage/Makefile
@@ -1,5 +1,6 @@
 FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
@@ -7,6 +8,8 @@
 GCC_PREFIX?=riscv32-unknown-elf
 PDK_PATH?=/ef/tech/SW/sky130A
 
+SIM?=RTL
+
 .SUFFIXES:
 
 PATTERN = storage
@@ -16,9 +19,15 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -I $(PDK_PATH) -I $(BEHAVIOURAL_MODELS) \
-	-I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
 
 %.vcd: %.vvp
 	vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
index 8fc22cd..cfbe150 100644
--- a/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
@@ -59,7 +59,11 @@
 			//$display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test Storage (RTL) Failed");
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Storage (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Storage (RTL) Failed");
+		`endif
 		$display("%c[0m",27);
 		$finish;
 	end
@@ -82,28 +86,52 @@
 
 	always @(checkbits) begin
 		if(checkbits == 16'hA040) begin
-			$display("Mem Test storage MGMT block0 (RTL) [word rw] started");
+			`ifdef GL
+				$display("Mem Test storage MGMT block0 (GL) [word rw] started");
+			`else
+				$display("Mem Test storage MGMT block0 (RTL) [word rw] started");
+			`endif
 		end
 		else if(checkbits == 16'hAB40) begin
 			$display("%c[1;31m",27);
-			$display("Monitor: Test storage MGMT block0 (RTL) [word rw] failed");
+			`ifdef GL
+				$display("Monitor: Test storage MGMT block0 (GL) [word rw] failed");
+			`else
+				$display("Monitor: Test storage MGMT block0 (RTL) [word rw] failed");
+			`endif
 			$display("%c[0m",27);
 			$finish;
 		end
 		else if(checkbits == 16'hAB41) begin
-			$display("Monitor: Test storage MGMT block0 (RTL) [word rw]  passed");
+			`ifdef GL
+				$display("Monitor: Test storage MGMT block0 (GL) [word rw]  passed");
+			`else
+				$display("Monitor: Test storage MGMT block0 (RTL) [word rw]  passed");
+			`endif
 		end
 		else if(checkbits == 16'hA020) begin
-			$display("Mem Test storage MGMT block1 (RTL) [word rw] started");
+			`ifdef GL
+				$display("Mem Test storage MGMT block1 (GL) [word rw] started");
+			`else
+				$display("Mem Test storage MGMT block1 (RTL) [word rw] started");
+			`endif
 		end
 		else if(checkbits == 16'hAB20) begin
 			$display("%c[1;31m",27);
-			$display("Monitor: Test storage MGMT block1 (RTL) [word rw] failed");
+			`ifdef GL
+				$display("Monitor: Test storage MGMT block1 (GL) [word rw] failed");
+			`else
+				$display("Monitor: Test storage MGMT block1 (RTL) [word rw] failed");
+			`endif
 			$display("%c[0m",27);
 			$finish;
 		end
 		else if(checkbits == 16'hAB21) begin
-			$display("Monitor: Test storage MGMT block1 (RTL) [word rw]  passed");
+			`ifdef GL
+				$display("Monitor: Test storage MGMT block1 (GL) [word rw]  passed");
+			`else
+				$display("Monitor: Test storage MGMT block1 (RTL) [word rw]  passed");
+			`endif
             $finish;
 		end
 	end
@@ -116,6 +144,8 @@
 	assign VDD3V3 = power1;
 	assign VDD1V8 = power2;
 
+	assign mprj_io[3] = 1'b1;  // Force CSB high.
+
 	caravel uut (
 		.vddio	  (VDD3V3),
 		.vssio	  (VSS),
diff --git a/verilog/dv/caravel/mgmt_soc/storage_gl/Makefile b/verilog/dv/caravel/mgmt_soc/storage_gl/Makefile
deleted file mode 100644
index f1b3248..0000000
--- a/verilog/dv/caravel/mgmt_soc/storage_gl/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-FIRMWARE_PATH = ../..
-VERILOG_PATH = ../../../..
-RTL_PATH = $(VERILOG_PATH)/rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../ 
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = storage
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -DUSE_POWER_PINS -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
-	$< -o $@
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
-	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/storage_gl/storage.c b/verilog/dv/caravel/mgmt_soc/storage_gl/storage.c
deleted file mode 100644
index b5f7408..0000000
--- a/verilog/dv/caravel/mgmt_soc/storage_gl/storage.c
+++ /dev/null
@@ -1,70 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-/*
-	Storage area Test
-	It uses GPIO to flag the success or failure of the test
-*/
-
-void main()
-{
-    int i;
-    volatile uint32_t* ram_addr; 
-    /* Upper 16 user area pins are configured to be GPIO output */
-
-    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    // Apply configuration
-    reg_mprj_xfer = 1;
-    while (reg_mprj_xfer == 1);
-
-    // start test
-    reg_mprj_datal = 0xA0400000;
-
-    // Test Management R/W block0
-    for (i=0; i<10; i++){
-        ram_addr = &reg_rw_block0 + i;
-        *ram_addr = i*5000 + 10000;
-    }
-	
-    for (i=0; i<10; i++){
-        ram_addr = &reg_rw_block0 + i;
-        if ((i*5000+10000) != *ram_addr) 
-	    reg_mprj_datal = 0xAB400000;
-    }
-	
-    reg_mprj_datal = 0xAB410000;
-	
-    // Test Management R/W block1
-    reg_mprj_datal = 0xA0200000;
-    for (i=0; i<10; i++){
-        ram_addr = &reg_rw_block1 + i;
-        *ram_addr = i*5000 + 10000;
-    }
-	
-    for (i=0; i<10; i++){
-        ram_addr = &reg_rw_block1 + i;
-        if ((i*5000+10000) != *ram_addr) 
-	    reg_mprj_datal = 0xAB200000;
-    }
-    
-    reg_mprj_datal = 0xAB210000;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/storage_gl/storage_tb.v b/verilog/dv/caravel/mgmt_soc/storage_gl/storage_tb.v
deleted file mode 100644
index ae1209a..0000000
--- a/verilog/dv/caravel/mgmt_soc/storage_gl/storage_tb.v
+++ /dev/null
@@ -1,158 +0,0 @@
-`default_nettype none
-/*
- *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
- *
- *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
- *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module storage_tb;
-	reg clock;
-	reg RSTB;
-	reg power1, power2;
-
-	wire gpio;
-    wire [15:0] checkbits;
-	wire [37:0] mprj_io;
-	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-
-	assign checkbits = mprj_io[31:16];
-
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
-
-	always #10 clock <= (clock === 1'b0);
-
-	initial begin
-		clock = 0;
-	end
-
-	initial begin
-		$dumpfile("storage.vcd");
-		$dumpvars(0, storage_tb);
-
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (100) begin
-			repeat (1000) @(posedge clock);
-			//$display("+1000 cycles");
-		end
-		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test Storage (GL) Failed");
-		$display("%c[0m",27);
-		$finish;
-	end
-
-	initial begin
-		RSTB <= 1'b0;
-		#1000;
-		RSTB <= 1'b1;	    // Release reset
-		#2000;
-	end
-
-	initial begin		// Power-up sequence
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		#200;
-		power1 <= 1'b1;
-		#200;
-		power2 <= 1'b1;
-	end
-
-	always @(checkbits) begin
-		if(checkbits == 16'hA040) begin
-			$display("Mem Test storage MGMT block0 (GL) [word rw] started");
-		end
-		else if(checkbits == 16'hAB40) begin
-			$display("%c[1;31m",27);
-			$display("Monitor: Test storage MGMT block0 (GL) [word rw] failed");
-			$display("%c[0m",27);
-			$finish;
-		end
-		else if(checkbits == 16'hAB41) begin
-			$display("Monitor: Test storage MGMT block0 (GL) [word rw]  passed");
-		end
-		else if(checkbits == 16'hA020) begin
-			$display("Mem Test storage MGMT block1 (GL) [word rw] started");
-		end
-		else if(checkbits == 16'hAB20) begin
-			$display("%c[1;31m",27);
-			$display("Monitor: Test storage MGMT block1 (GL) [word rw] failed");
-			$display("%c[0m",27);
-			$finish;
-		end
-		else if(checkbits == 16'hAB21) begin
-			$display("Monitor: Test storage MGMT block1 (GL) [word rw]  passed");
-            $finish;
-		end
-	end
-
-	wire VDD3V3;
-	wire VDD1V8;
-	wire VSS;
-
-	assign VSS = 1'b0;
-	assign VDD3V3 = power1;
-	assign VDD1V8 = power2;
-
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (VDD3V3),
-		.vdda2    (VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (VDD1V8),
-		.vccd2	  (VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock	  (clock),
-		.gpio     (gpio),
-		.mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("storage.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile b/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
index 0cd4654..351c740 100644
--- a/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
@@ -1,5 +1,6 @@
 FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
@@ -7,6 +8,8 @@
 GCC_PREFIX?=riscv32-unknown-elf
 PDK_PATH?=/ef/tech/SW/sky130A
 
+SIM?=RTL
+
 .SUFFIXES:
 
 PATTERN = sysctrl
@@ -16,9 +19,15 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
 	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
+	$< -o $@ 
+else  
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
 
 %.vcd: %.vvp
 	vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
index b80cc33..509bc20 100644
--- a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -41,7 +41,11 @@
 			$display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Sysctrl (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Sysctrl (RTL) Failed");
+		`endif
 		 $display("%c[0m",27);
 		$finish;
 	end
@@ -49,77 +53,84 @@
 	// Monitor
 	initial begin
 	    wait(checkbits == 16'hA040);
-            $display("Monitor: Test Sysctrl (RTL) Started");
-
+			`ifdef GL
+            	$display("Monitor: Test Sysctrl (GL) Started");
+			`else
+			    $display("Monitor: Test Sysctrl (RTL) Started");
+			`endif
 	    wait(checkbits == 16'hA041);
             $display("   SPI value = 0x%x (should be 0x04)", spivalue);
             if(spivalue !== 32'h04) begin
-                $display("Monitor: Test Sysctrl (RTL) Failed");
+                $display("Monitor: Test Sysctrl Failed");
                 $finish;
             end
 	    wait(checkbits == 16'hA042);
             $display("   SPI value = 0x%x (should be 0x56)", spivalue);
             if(spivalue !== 32'h56) begin
-                $display("Monitor: Test Sysctrl (RTL) Failed");
+                $display("Monitor: Test Sysctrl Failed");
                 $finish;
             end
 	    wait(checkbits == 16'hA043);
             $display("   SPI value = 0x%x (should be 0x10)", spivalue);
             if(spivalue !== 32'h10) begin
-                $display("Monitor: Test Sysctrl (RTL) Failed");
+                $display("Monitor: Test Sysctrl Failed");
                 $finish;
             end
 	    wait(checkbits == 16'hA044);
             $display("   SPI value = 0x%x (should be 0x02)", spivalue);
             if(spivalue !== 32'h02) begin
-                $display("Monitor: Test Sysctrl (RTL) Failed");
+                $display("Monitor: Test Sysctrl Failed");
                 $finish;
             end
 	    wait(checkbits == 16'hA045);
             $display("   SPI value = 0x%x (should be 0x01)", spivalue);
             if(spivalue !== 32'h01) begin
-                $display("Monitor: Test Sysctrl (RTL) Failed");
+                $display("Monitor: Test Sysctrl Failed");
                 $finish;
             end
 	    wait(checkbits == 16'hA046);
             $display("   SPI value = 0x%x (should be 0xff)", spivalue);
             if(spivalue !== 32'hff) begin
-                $display("Monitor: Test Sysctrl (RTL) Failed");
+                $display("Monitor: Test Sysctrl Failed");
                 $finish;
             end
 	    wait(checkbits == 16'hA047);
             $display("   SPI value = 0x%x (should be 0xef)", spivalue);
             if(spivalue !== 32'hef) begin
-                $display("Monitor: Test Sysctrl (RTL) Failed");
+                $display("Monitor: Test Sysctrl Failed");
                 $finish;
             end
 	    wait(checkbits == 16'hA048);
             $display("   SPI value = 0x%x (should be 0xff)", spivalue);
             if(spivalue !== 32'hff) begin
-                $display("Monitor: Test Sysctrl (RTL) Failed");
+                $display("Monitor: Test Sysctrl Failed");
                 $finish;
             end
 	    wait(checkbits == 16'hA049);
             $display("   SPI value = 0x%x (should be 0x03)", spivalue);
             if(spivalue !== 32'h03) begin
-                $display("Monitor: Test Sysctrl (RTL) Failed");
+                $display("Monitor: Test Sysctrl Failed");
                 $finish;
             end
 	    wait(checkbits == 16'hA04a);
             $display("   SPI value = 0x%x (should be 0x12)", spivalue);
             if(spivalue !== 32'h12) begin
-                $display("Monitor: Test Sysctrl (RTL) Failed");
+                $display("Monitor: Test Sysctrl Failed");
                 $finish;
             end
 	    wait(checkbits == 16'hA04b);
             $display("   SPI value = 0x%x (should be 0x04)", spivalue);
             if(spivalue !== 32'h04) begin
-                $display("Monitor: Test Sysctrl (RTL) Failed");
+                $display("Monitor: Test Sysctrl Failed");
                 $finish;
             end
 
 	    wait(checkbits == 16'hA090);
-            $display("Monitor: Test Sysctrl (RTL) Passed");
+		 	`ifdef GL
+            	$display("Monitor: Test Sysctrl (GL) Passed");
+			`else
+		        $display("Monitor: Test Sysctrl (RTL) Passed");
+			`endif
             $finish;
 	end
 
@@ -151,6 +162,8 @@
 	assign VDD1V8 = power2;
 	assign VSS = 1'b0;
 
+	assign mprj_io[3] = 1'b1;
+	
 	caravel uut (
 		.vddio	  (VDD3V3),
 		.vssio	  (VSS),
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl_gl/Makefile b/verilog/dv/caravel/mgmt_soc/sysctrl_gl/Makefile
deleted file mode 100644
index 0cd4654..0000000
--- a/verilog/dv/caravel/mgmt_soc/sysctrl_gl/Makefile
+++ /dev/null
@@ -1,43 +0,0 @@
-FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../ 
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = sysctrl
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
-	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl_gl/sysctrl.c b/verilog/dv/caravel/mgmt_soc/sysctrl_gl/sysctrl.c
deleted file mode 100644
index 3d2cefd..0000000
--- a/verilog/dv/caravel/mgmt_soc/sysctrl_gl/sysctrl.c
+++ /dev/null
@@ -1,148 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-/*
- *	System Control Test
- *	- Enables SPI master
- *	- Uses SPI master to internally access the housekeeping SPI
- *      - Reads default value of SPI-Controlled registers
- *      - Flags failure/success using mprj_io
- */
-void main()
-{
-    int i;
-    uint32_t value;
-
-    reg_mprj_datal = 0;
-
-    // Configure upper 16 bits of user GPIO for generating testbench
-    // checkpoints.
-
-    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    // Configure next 8 bits for writing the SPI value read on GPIO
-    reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_9  = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_8  = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    /* Apply configuration */
-    reg_mprj_xfer = 1;
-    while (reg_mprj_xfer == 1);
-
-    // Start test
-    reg_mprj_datal = 0xA0400000;
-
-    // Enable SPI master
-    // SPI master configuration bits:
-    // bits 7-0:	Clock prescaler value (default 2)
-    // bit  8:		MSB/LSB first (0 = MSB first, 1 = LSB first)
-    // bit  9:		CSB sense (0 = inverted, 1 = noninverted)
-    // bit 10:		SCK sense (0 = noninverted, 1 = inverted)
-    // bit 11:		mode (0 = read/write opposite edges, 1 = same edges)
-    // bit 12:		stream (1 = CSB ends transmission)
-    // bit 13:		enable (1 = enabled)
-    // bit 14:		IRQ enable (1 = enabled)
-    // bit 15:		Connect to housekeeping SPI (1 = connected)
-
-    reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
-					// connect to housekeeping SPI
-
-    // Apply stream read (0x40 + 0x03) and read back one byte 
-
-    reg_spimaster_config = 0xb002;	// Apply stream mode
-    reg_spimaster_data = 0x40;		// Write 0x40 (read mode)
-    reg_spimaster_data = 0x01;		// Write 0x01 (start address)
-
-    reg_spimaster_data = 0x00;		// Write 0x00 for read
-    value = reg_spimaster_data;		// Read back byte
-    // Write checkpoint
-    reg_mprj_datal = 0xA0410000 | (value << 8);	// Mfgr ID (high)
-
-    reg_spimaster_data = 0x00;		// Write 0x00 for read
-    value = reg_spimaster_data;		// Read back byte
-    // Write checkpoint
-    reg_mprj_datal = 0xA0420000 | (value << 8);	// Mfgr ID (low)
-
-    reg_spimaster_data = 0x00;		// Write 0x00 for read
-    value = reg_spimaster_data;		// Read back byte
-    // Write checkpoint
-    reg_mprj_datal = 0xA0430000 | (value << 8);	// Prod ID
-
-    reg_spimaster_config = 0xa102;	// Release CSB (ends stream mode)
-    reg_spimaster_config = 0xb002;	// Apply stream mode
-    reg_spimaster_data = 0x40;		// Write 0x40 (read mode)
-    reg_spimaster_data = 0x08;		// Write 0x08 (start address)
-
-    reg_spimaster_data = 0x00;		// Write 0x00 for read
-    value = reg_spimaster_data;		// Read back byte
-    // Write checkpoint
-    reg_mprj_datal = 0xA0440000 | (value << 8);	// PLL enable
-
-    reg_spimaster_data = 0x00;		// Write 0x00 for read
-    value = reg_spimaster_data;		// Read back byte
-    // Write checkpoint
-    reg_mprj_datal = 0xA0450000 | (value << 8);	// PLL bypass
-
-    reg_spimaster_config = 0xa102;	// Release CSB (ends stream mode)
-    reg_spimaster_config = 0xb002;	// Apply stream mode
-    reg_spimaster_data = 0x40;		// Write 0x40 (read mode)
-    reg_spimaster_data = 0x0d;		// Write 0x0d (start address)
-
-    reg_spimaster_data = 0x00;		// Write 0x00 for read
-    value = reg_spimaster_data;		// Read back byte
-    // Write checkpoint
-    reg_mprj_datal = 0xA0460000 | (value << 8);	// PLL trim (2 high bits)
-
-    reg_spimaster_data = 0x00;		// Write 0x00 for read
-    value = reg_spimaster_data;		// Read back byte
-    // Write checkpoint
-    reg_mprj_datal = 0xA0470000 | (value << 8);	// PLL trim (2nd byte)
-
-    reg_spimaster_data = 0x00;		// Write 0x00 for read
-    value = reg_spimaster_data;		// Read back byte
-    // Write checkpoint
-    reg_mprj_datal = 0xA0480000 | (value << 8);	// PLL trim (3rd byte)
-
-    reg_spimaster_data = 0x00;		// Write 0x00 for read
-    value = reg_spimaster_data;		// Read back byte
-    // Write checkpoint
-    reg_mprj_datal = 0xA0490000 | (value << 8);	// PLL trim (low byte)
-
-    reg_spimaster_data = 0x00;		// Write 0x00 for read
-    value = reg_spimaster_data;		// Read back byte
-    // Write checkpoint
-    reg_mprj_datal = 0xA04a0000 | (value << 8);	// PLL select (3 lowest bits)
-
-    reg_spimaster_data = 0x00;		// Write 0x00 for read
-    value = reg_spimaster_data;		// Read back byte
-    // Write checkpoint
-    reg_mprj_datal = 0xA04b0000 | (value << 8);	// PLL divider (5 lowest bits)
-
-    reg_spimaster_config = 0xa102;	// Release CSB (ends stream mode)
-    reg_spimaster_config = 0x2102;	// Release housekeeping SPI
-
-    // End test
-    reg_mprj_datal = 0xA0900000;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl_gl/sysctrl_tb.v b/verilog/dv/caravel/mgmt_soc/sysctrl_gl/sysctrl_tb.v
deleted file mode 100644
index 8b33e6b..0000000
--- a/verilog/dv/caravel/mgmt_soc/sysctrl_gl/sysctrl_tb.v
+++ /dev/null
@@ -1,193 +0,0 @@
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module sysctrl_tb;
-	reg clock;
-	reg RSTB;
-	reg power1, power2;
-
-	wire gpio;
-	wire [15:0] checkbits;
-	wire [7:0] spivalue;
-	wire [37:0] mprj_io;
-	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-	wire SDO;
-
-	assign checkbits = mprj_io[31:16];
-	assign spivalue  = mprj_io[15:8];
-
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
-
-	always #10 clock <= (clock === 1'b0);
-
-	initial begin
-		clock = 0;
-	end
-
-	initial begin
-		$dumpfile("sysctrl.vcd");
-		$dumpvars(0, sysctrl_tb);
-		repeat (25) begin
-			repeat (1000) @(posedge clock);
-			$display("+1000 cycles");
-		end
-		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test GPIO (GL) Failed");
-		 $display("%c[0m",27);
-		$finish;
-	end
-
-	// Monitor
-	initial begin
-	    wait(checkbits == 16'hA040);
-            $display("Monitor: Test Sysctrl (GL) Started");
-
-	    wait(checkbits == 16'hA041);
-            $display("   SPI value = 0x%x (should be 0x04)", spivalue);
-            if(spivalue !== 32'h04) begin
-                $display("Monitor: Test Sysctrl (GL) Failed");
-                $finish;
-            end
-	    wait(checkbits == 16'hA042);
-            $display("   SPI value = 0x%x (should be 0x56)", spivalue);
-            if(spivalue !== 32'h56) begin
-                $display("Monitor: Test Sysctrl (GL) Failed");
-                $finish;
-            end
-	    wait(checkbits == 16'hA043);
-            $display("   SPI value = 0x%x (should be 0x10)", spivalue);
-            if(spivalue !== 32'h10) begin
-                $display("Monitor: Test Sysctrl (GL) Failed");
-                $finish;
-            end
-	    wait(checkbits == 16'hA044);
-            $display("   SPI value = 0x%x (should be 0x02)", spivalue);
-            if(spivalue !== 32'h02) begin
-                $display("Monitor: Test Sysctrl (GL) Failed");
-                $finish;
-            end
-	    wait(checkbits == 16'hA045);
-            $display("   SPI value = 0x%x (should be 0x01)", spivalue);
-            if(spivalue !== 32'h01) begin
-                $display("Monitor: Test Sysctrl (GL) Failed");
-                $finish;
-            end
-	    wait(checkbits == 16'hA046);
-            $display("   SPI value = 0x%x (should be 0xff)", spivalue);
-            if(spivalue !== 32'hff) begin
-                $display("Monitor: Test Sysctrl (GL) Failed");
-                $finish;
-            end
-	    wait(checkbits == 16'hA047);
-            $display("   SPI value = 0x%x (should be 0xef)", spivalue);
-            if(spivalue !== 32'hef) begin
-                $display("Monitor: Test Sysctrl (GL) Failed");
-                $finish;
-            end
-	    wait(checkbits == 16'hA048);
-            $display("   SPI value = 0x%x (should be 0xff)", spivalue);
-            if(spivalue !== 32'hff) begin
-                $display("Monitor: Test Sysctrl (GL) Failed");
-                $finish;
-            end
-	    wait(checkbits == 16'hA049);
-            $display("   SPI value = 0x%x (should be 0x03)", spivalue);
-            if(spivalue !== 32'h03) begin
-                $display("Monitor: Test Sysctrl (GL) Failed");
-                $finish;
-            end
-	    wait(checkbits == 16'hA04a);
-            $display("   SPI value = 0x%x (should be 0x12)", spivalue);
-            if(spivalue !== 32'h12) begin
-                $display("Monitor: Test Sysctrl (GL) Failed");
-                $finish;
-            end
-	    wait(checkbits == 16'hA04b);
-            $display("   SPI value = 0x%x (should be 0x04)", spivalue);
-            if(spivalue !== 32'h04) begin
-                $display("Monitor: Test Sysctrl (GL) Failed");
-                $finish;
-            end
-
-	    wait(checkbits == 16'hA090);
-            $display("Monitor: Test Sysctrl (GL) Passed");
-            $finish;
-	end
-
-	initial begin
-		RSTB <= 1'b0;
-		#1000;
-		RSTB <= 1'b1;	    // Release reset
-		#2000;
-	end
-
-	initial begin		// Power-up sequence
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		#200;
-		power1 <= 1'b1;
-		#200;
-		power2 <= 1'b1;
-	end
-
-	always @(checkbits) begin
-		#1 $display("GPIO state = %b ", checkbits);
-	end
-
-	wire VDD3V3;
-	wire VDD1V8;
-	wire VSS;
-	
-	assign VDD3V3 = power1;
-	assign VDD1V8 = power2;
-	assign VSS = 1'b0;
-
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (VDD3V3),
-		.vdda2    (VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (VDD1V8),
-		.vccd2	  (VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock    (clock),
-		.gpio     (gpio),
-		.mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("sysctrl.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/timer/Makefile b/verilog/dv/caravel/mgmt_soc/timer/Makefile
index 92e809f..641a453 100644
--- a/verilog/dv/caravel/mgmt_soc/timer/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/timer/Makefile
@@ -16,9 +16,15 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
 	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
+	$< -o $@ 
+else  
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
 
 %.vcd: %.vvp
 	vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
index 8e43731..acb6798 100644
--- a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
@@ -46,7 +46,11 @@
 			$display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+		`ifdef GL
+			$display ("Monitor: Timeout, Test GPIO (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+		`endif
 		 $display("%c[0m",27);
 		$finish;
 	end
@@ -67,41 +71,48 @@
 	// Monitor
 	initial begin
 		wait(checkbits == 6'h0a);
-		$display("Monitor: Test Timer (RTL) Started");
-
+		`ifdef GL
+			$display("Monitor: Test Timer (GL) Started");
+		`else 
+			$display("Monitor: Test Timer (RTL) Started");
+		`endif
 		/* Add checks here */
 		wait(checkbits == 6'h01);
 		$display("   countbits = 0x%x (should be 0xdcba7cf3)", countbits);
 		if(countbits !== 32'hdcba7cf3) begin
-		    $display("Monitor: Test Timer (RTL) Failed");
+		    $display("Monitor: Test Timer Failed");
 		    $finish;
 		end
 		wait(checkbits == 6'h02);
 		$display("   countbits = 0x%x (should be 0x11)", countbits);
 		if(countbits !== 32'h11) begin
-		    $display("Monitor: Test Timer (RTL) Failed");
+		    $display("Monitor: Test Timer Failed");
 		    $finish;
 		end
 		wait(checkbits == 6'h03);
 		$display("   countbits = %x (should be 0x0f)", countbits);
 		if(countbits !== 32'h0f) begin
-		    $display("Monitor: Test Timer (RTL) Failed");
+		    $display("Monitor: Test Timer Failed");
 		    $finish;
 		end
 		wait(checkbits == 6'h04);
 		$display("   countbits = %x (should be 0x0f)", countbits);
 		if(countbits !== 32'h0f) begin
-		    $display("Monitor: Test Timer (RTL) Failed");
+		    $display("Monitor: Test Timer Failed");
 		    $finish;
 		end
 		wait(checkbits == 6'h05);
 		$display("   countbits = %x (should be 0x12b4)", countbits);
 		if(countbits !== 32'h12b4) begin
-		    $display("Monitor: Test Timer (RTL) Failed");
+		    $display("Monitor: Test Timer Failed");
 		    $finish;
 		end
-
-		$display("Monitor: Test Timer (RTL) Passed");
+		
+		`ifdef GL
+			$display("Monitor: Test Timer (GL) Passed");
+		`else
+			$display("Monitor: Test Timer (RTL) Passed");
+		`endif
 		$finish;
 	end
 
diff --git a/verilog/dv/caravel/mgmt_soc/timer2/Makefile b/verilog/dv/caravel/mgmt_soc/timer2/Makefile
index 73cecf5..e054fa8 100644
--- a/verilog/dv/caravel/mgmt_soc/timer2/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/timer2/Makefile
@@ -1,5 +1,6 @@
 FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
@@ -7,6 +8,8 @@
 GCC_PREFIX?=riscv32-unknown-elf
 PDK_PATH?=/ef/tech/SW/sky130A
 
+SIM?=RTL
+
 .SUFFIXES:
 
 PATTERN = timer2
@@ -16,9 +19,15 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
 	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
+	$< -o $@ 
+else  
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
 
 %.vcd: %.vvp
 	vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
index 6e4e191..750635d 100644
--- a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
@@ -46,7 +46,11 @@
 			$display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Timer2 (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Timer2 (RTL) Failed");
+		`endif
 		$display("%c[0m",27);
 		$finish;
 	end
@@ -67,8 +71,11 @@
 	// Monitor
 	initial begin
 		wait(checkbits == 6'h0a);
-		$display("Monitor: Test Timer2 (RTL) Started");
-
+		`ifdef GL
+			$display("Monitor: Test Timer2 (GL) Started");
+		`else
+			$display("Monitor: Test Timer2 (RTL) Started");
+		`endif
 		/* Add checks here */
 		wait(checkbits == 6'h01);
 		$display("   countbits = 0x%x (should be 0xdcba7cf3)", countbits);
@@ -129,7 +136,11 @@
 		    $finish;
 		end
 
-		$display("Monitor: Test Timer2 (RTL) Passed");
+		`ifdef GL
+			$display("Monitor: Test Timer2 (GL) Passed");
+		`else
+			$display("Monitor: Test Timer2 (RTL) Passed");
+		`endif
 		$finish;
 	end
 
diff --git a/verilog/dv/caravel/mgmt_soc/timer2_gl/Makefile b/verilog/dv/caravel/mgmt_soc/timer2_gl/Makefile
deleted file mode 100644
index 73cecf5..0000000
--- a/verilog/dv/caravel/mgmt_soc/timer2_gl/Makefile
+++ /dev/null
@@ -1,43 +0,0 @@
-FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../ 
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = timer2
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
-	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/timer2_gl/timer2.c b/verilog/dv/caravel/mgmt_soc/timer2_gl/timer2.c
deleted file mode 100644
index a8c65e0..0000000
--- a/verilog/dv/caravel/mgmt_soc/timer2_gl/timer2.c
+++ /dev/null
@@ -1,197 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-/*
- *	Timer2 Test --- This runs the same testbench as the
- *	other timer, on the 2nd counter/timer module instance.
- */
-
-void main()
-{
-	int i;
-	uint32_t value;
-
-	/* Initialize output data vector to zero */
-	reg_mprj_datah = 0x00000000;
-	reg_mprj_datal = 0x00000000;
-
-	/* Apply all 38 bits to management standard output.	*/
-
-	/* The lower 32 will be used to output the count value	*/
-	/* from the timer.  The top 5 bits will be used	to mark	*/
-	/* specific checkpoints for the testbench simulation.	*/
-
-	reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_9  = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_8  = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_7  = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_6  = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_5  = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_4  = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_3  = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_2  = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_1  = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_0  = GPIO_MODE_MGMT_STD_OUTPUT;
-
-	/* Apply configuration */
-	reg_mprj_xfer = 1;
-	while (reg_mprj_xfer == 1);
-
-	/* Present start marker (see testbench verilog) */
-	reg_mprj_datah = 0x0a;
-
-	/* Configure timer for a single-shot countdown */
-	reg_timer1_value = 0xdcba9876;
-
-	/* Timer configuration bits:				*/
-	/* 0 = timer enable (1 = enabled, 0 = disabled)		*/
-	/* 1 = one-shot mode (1 = oneshot, 0 = continuous)	*/
-	/* 2 = up/down (1 = count up, 0 = count down)		*/
-	/* 3 = IRQ enable (1 = enabled, 0 = disabled)		*/
-
-	reg_timer1_config = 3;	/* Enabled, one-shot, down count */
-
-	for (i = 0; i < 8; i++) {
-	    value = reg_timer1_data;
-	    reg_mprj_datal = value;	// Put count value on GPIO
-	}
-
-	reg_timer1_config = 0;	/* Disabled */
-
-	reg_mprj_datah = 0x01;	/* Check value in testbench */
-
-	reg_timer1_value = 0x00000011;
-	reg_timer1_config = 7;	/* Enabled, one-shot, count up */
-	
-	for (i = 0; i < 3; i++) {
-	    value = reg_timer1_data;
-	    reg_mprj_datal = value;	// Put count value on GPIO
-	}
-
-	reg_mprj_datah = 0x02;	/* Check value in testbench */
-	
-	reg_timer1_data = 0x00000101;	// Set value (will be reset)
-	reg_timer1_config = 2;	/* Disabled, one-shot, count up */
-	reg_timer1_config = 5;	/* Enabled, continuous, count down */
-	
-	for (i = 0; i < 5; i++) {
-	    value = reg_timer1_data;
-	    reg_mprj_datal = value;	// Put count value on GPIO
-	}
-
-	reg_mprj_datah = 0x03;	/* Check value in testbench */
-
-	reg_timer1_data = 0x00000145;	// Force new value
-
-	reg_mprj_datah = 0x04;	/* Check value in testbench */
-	
-	for (i = 0; i < 5; i++) {
-	    value = reg_timer1_data;
-	    reg_mprj_datal = value;	// Put count value on GPIO
-	}
-
-	reg_mprj_datah = 0x05;	/* Check value in testbench */
-
-	/* Now, set up chained 64 bit timer.  Check count-up	*/
-	/* value and count-down value crossing the 32-bit	*/
-	/* boundary.						*/
-
-	/* First disable both counters, and set the "chained"	*/
-	/* property so that enable/disable will be synchronized	*/
-
-	reg_timer1_config = 8;	/* Disabled, chained */
-	reg_timer0_config = 8;	/* Disabled, chained */
-
-	/* Configure timer for a chained single-shot countdown. */
-	/* Count start = 0x0000000100001000, end = 0x0		*/
-
-	reg_timer1_value = 0x00000055;
-	reg_timer0_value = 0x00001000;
-
-	/* Timer configuration bits:				*/
-	/* 0 = timer enable (1 = enabled, 0 = disabled)		*/
-	/* 1 = one-shot mode (1 = oneshot, 0 = continuous)	*/
-	/* 2 = up/down (1 = count up, 0 = count down)		*/
-	/* 3 = chain (1 = enabled, 0 = disabled)		*/
-	/* 4 = IRQ enable (1 = enabled, 0 = disabled)		*/
-
-	reg_timer1_config = 11;	/* Enabled, one-shot, down count, chained */
-	reg_timer0_config = 11;	/* Enabled, one-shot, down count, chained */
-
-	for (i = 0; i < 1; i++) {
-	    value = reg_timer1_data;
-	    reg_mprj_datal = value;	// Put count value on GPIO
-	}
-
-	reg_mprj_datah = 0x06;	/* Check value in testbench */
-
-	// Skip to the end. . .
-	reg_timer1_data = 0x00000000;
-	reg_timer0_data = 0x00000200;
-
-	for (i = 0; i < 4; i++) {
-	    value = reg_timer0_data;
-	    reg_mprj_datal = value;	// Put count value on GPIO
-	}
-
-	reg_mprj_datah = 0x07;	/* Check value in testbench */
-
-	reg_timer1_config = 14;	/* Disabled, one-shot, up count, chained */
-	reg_timer0_config = 14;	/* Disabled, one-shot, up count, chained */
-
-	reg_timer1_value = 0x00000002;
-	reg_timer0_value = 0x00000000;
-
-	reg_timer1_config = 15;	/* Enabled, one-shot, up count, chained */
-	reg_timer0_config = 15;	/* Enabled, one-shot, up count, chained */
-
-	for (i = 0; i < 1; i++) {
-	    value = reg_timer0_data;
-	    reg_mprj_datal = value;	// Put count value on GPIO
-	}
-
-	reg_mprj_datah = 0x08;	/* Check value in testbench */
-
-	// Skip to the end. . . 
-	/* Count 0x00000001ffffff00 to 0x0000000200000000 and stop */
-
-	reg_timer1_data = 0x00000001;	// Set value (will be reset)
-	reg_timer0_data = 0xffffff00;	// Set value (will be reset)
-
-	for (i = 0; i < 4; i++) {
-	    value = reg_timer1_data;
-	    reg_mprj_datal = value;	// Put timer1 count value on GPIO
-	}
-
-	/* Present end marker (see testbench verilog) */
-	reg_mprj_datah = 0x10;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/timer2_gl/timer2_tb.v b/verilog/dv/caravel/mgmt_soc/timer2_gl/timer2_tb.v
deleted file mode 100644
index 00f3280..0000000
--- a/verilog/dv/caravel/mgmt_soc/timer2_gl/timer2_tb.v
+++ /dev/null
@@ -1,214 +0,0 @@
-`default_nettype none
-/*
- *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
- *
- *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
- *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module timer2_tb;
-
-	reg clock;
-	reg RSTB;
-	reg power1, power2;
-
-	always #10 clock <= (clock === 1'b0);
-
-	initial begin
-		clock <= 0;
-	end
-
-	initial begin
-		$dumpfile("timer2.vcd");
-		$dumpvars(0, timer2_tb);
-
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (60) begin
-			repeat (1000) @(posedge clock);
-			$display("+1000 cycles");
-		end
-		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test GPIO (GL) Failed");
-		$display("%c[0m",27);
-		$finish;
-	end
-
-	wire [37:0] mprj_io;	// Most of these are no-connects
-	wire [5:0] checkbits;
-	wire [31:0] countbits;
-
-	assign checkbits = mprj_io[37:32];
-	assign countbits = mprj_io[31:0];
-
-	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-	wire gpio;
-
-	// Monitor
-	initial begin
-		wait(checkbits == 6'h0a);
-		$display("Monitor: Test Timer2 (GL) Started");
-
-		/* Add checks here */
-		wait(checkbits == 6'h01);
-		$display("   countbits = 0x%x (should be 0xdcba7cf3)", countbits);
-		if(countbits !== 32'hdcba7cf3) begin
-		    $display("Monitor: Test Timer2 (GL) Failed");
-		    $finish;
-		end
-		wait(checkbits == 6'h02);
-		$display("   countbits = 0x%x (should be 0x11)", countbits);
-		if(countbits !== 32'h11) begin
-		    $display("Monitor: Test Timer2 (GL) Failed");
-		    $finish;
-		end
-		wait(checkbits == 6'h03);
-		$display("   countbits = %x (should be 0x0f)", countbits);
-		if(countbits !== 32'h0f) begin
-		    $display("Monitor: Test Timer (GL) Failed");
-		    $finish;
-		end
-		wait(checkbits == 6'h04);
-		$display("   countbits = %x (should be 0x0f)", countbits);
-		if(countbits !== 32'h0f) begin
-		    $display("Monitor: Test Timer2 (GL) Failed");
-		    $finish;
-		end
-		wait(checkbits == 6'h05);
-		$display("   countbits = %x (should be 0x12b4)", countbits);
-		if(countbits !== 32'h12b4) begin
-		    $display("Monitor: Test Timer2 (GL) Failed");
-		    $finish;
-		end
-
-		wait(checkbits == 6'h06);
-		$display("   countbits = %x (should be 0x0055)", countbits);
-		if(countbits !== 32'h0055) begin
-		    $display("Monitor: Test Timer2 (GL) Failed");
-		    $finish;
-		end
-
-		wait(checkbits == 6'h07);
-		$display("   countbits = %x (should be 0x0000)", countbits);
-		if(countbits !== 32'h0000) begin
-		    $display("Monitor: Test Timer2 (GL) Failed");
-		    $finish;
-		end
-
-		wait(checkbits == 6'h08);
-		$display("   countbits = %x (should be 0x0259)", countbits);
-		if(countbits !== 32'h0259) begin
-		    $display("Monitor: Test Timer2 (GL) Failed");
-		    $finish;
-		end
-
-		wait(checkbits == 6'h10);
-		$display("   countbits = %x (should be 0x0002)", countbits);
-		if(countbits !== 32'h0002) begin
-		    $display("Monitor: Test Timer2 (GL) Failed");
-		    $finish;
-		end
-
-		$display("Monitor: Test Timer2 (GL) Passed");
-		$finish;
-	end
-
-	initial begin
-		RSTB <= 1'b0;
-		#1000;
-		RSTB <= 1'b1;	    // Release reset
-	end
-
-	initial begin		// Power-up sequence
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		#200;
-		power1 <= 1'b1;
-		#200;
-		power2 <= 1'b1;
-	end
-
-	always @(checkbits) begin
-		#1 $display("Timer state = %b (%d)", countbits, countbits);
-	end
-
-	wire VDD3V3;
-	wire VDD1V8;
-	wire VSS;
-
-	assign VDD3V3 = power1;
-	assign VDD1V8 = power2;
-	assign VSS = 1'b0;
-
-	// These are the mappings of mprj_io GPIO pads that are set to
-	// specific functions on startup:
-	//
-	// JTAG      = mgmt_gpio_io[0]              (inout)
-	// SDO       = mgmt_gpio_io[1]              (output)
-	// SDI       = mgmt_gpio_io[2]              (input)
-	// CSB       = mgmt_gpio_io[3]              (input)
-	// SCK       = mgmt_gpio_io[4]              (input)
-	// ser_rx    = mgmt_gpio_io[5]              (input)
-	// ser_tx    = mgmt_gpio_io[6]              (output)
-	// irq       = mgmt_gpio_io[7]              (input)
-
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (VDD3V3),
-		.vdda2    (VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (VDD1V8),
-		.vccd2	  (VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock	  (clock),
-		.gpio     (gpio),
-		.mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("timer2.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/timer_gl/Makefile b/verilog/dv/caravel/mgmt_soc/timer_gl/Makefile
deleted file mode 100644
index 92e809f..0000000
--- a/verilog/dv/caravel/mgmt_soc/timer_gl/Makefile
+++ /dev/null
@@ -1,43 +0,0 @@
-FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../ 
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = timer
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
-	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/timer_gl/timer.c b/verilog/dv/caravel/mgmt_soc/timer_gl/timer.c
deleted file mode 100644
index c3a8dc4..0000000
--- a/verilog/dv/caravel/mgmt_soc/timer_gl/timer.c
+++ /dev/null
@@ -1,124 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-/*
- *	Timer Test
- */
-
-void main()
-{
-	int i;
-	uint32_t value;
-
-	/* Initialize output data vector to zero */
-	reg_mprj_datah = 0x00000000;
-	reg_mprj_datal = 0x00000000;
-
-	/* Apply all 38 bits to management standard output.	*/
-
-	/* The lower 32 will be used to output the count value	*/
-	/* from the timer.  The top 5 bits will be used	to mark	*/
-	/* specific checkpoints for the testbench simulation.	*/
-
-	reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_9  = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_8  = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_7  = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_6  = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_5  = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_4  = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_3  = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_2  = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_1  = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_0  = GPIO_MODE_MGMT_STD_OUTPUT;
-
-	/* Apply configuration */
-	reg_mprj_xfer = 1;
-	while (reg_mprj_xfer == 1);
-
-	/* Present start marker (see testbench verilog) */
-	reg_mprj_datah = 0x0a;
-
-	/* Configure timer for a single-shot countdown */
-	reg_timer0_value = 0xdcba9876;
-
-	/* Timer configuration bits:				*/
-	/* 0 = timer enable (1 = enabled, 0 = disabled)		*/
-	/* 1 = one-shot mode (1 = oneshot, 0 = continuous)	*/
-	/* 2 = up/down (1 = count up, 0 = count down)		*/
-	/* 3 = chain (1 = enabled, 0 = disabled)		*/
-	/* 4 = IRQ enable (1 = enabled, 0 = disabled)		*/
-
-	reg_timer0_config = 3;	/* Enabled, one-shot, down count */
-
-	for (i = 0; i < 8; i++) {
-	    value = reg_timer0_data;
-	    reg_mprj_datal = value;	// Put count value on GPIO
-	}
-
-	reg_timer0_config = 0;	/* Disabled */
-
-	reg_mprj_datah = 0x01;	/* Check value in testbench */
-
-	reg_timer0_value = 0x00000011;
-	reg_timer0_config = 7;	/* Enabled, one-shot, count up */
-	
-	for (i = 0; i < 3; i++) {
-	    value = reg_timer0_data;
-	    reg_mprj_datal = value;	// Put count value on GPIO
-	}
-
-	reg_mprj_datah = 0x02;	/* Check value in testbench */
-	
-	reg_timer0_data = 0x00000101;	// Set value (will be reset)
-	reg_timer0_config = 2;	/* Disabled, one-shot, count up */
-	reg_timer0_config = 5;	/* Enabled, continuous, count down */
-	
-	for (i = 0; i < 5; i++) {
-	    value = reg_timer0_data;
-	    reg_mprj_datal = value;	// Put count value on GPIO
-	}
-
-	reg_mprj_datah = 0x03;	/* Check value in testbench */
-
-	reg_timer0_data = 0x00000145;	// Force new value
-
-	reg_mprj_datah = 0x04;	/* Check value in testbench */
-	
-	for (i = 0; i < 5; i++) {
-	    value = reg_timer0_data;
-	    reg_mprj_datal = value;	// Put count value on GPIO
-	}
-	
-	/* Present end marker (see testbench verilog) */
-	reg_mprj_datah = 0x05;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/timer_gl/timer_tb.v b/verilog/dv/caravel/mgmt_soc/timer_gl/timer_tb.v
deleted file mode 100644
index 30904d6..0000000
--- a/verilog/dv/caravel/mgmt_soc/timer_gl/timer_tb.v
+++ /dev/null
@@ -1,186 +0,0 @@
-`default_nettype none
-/*
- *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
- *
- *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
- *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module timer_tb;
-
-	reg RSTB;
-	reg clock;
-	reg power1, power2;
-
-	always #10 clock <= (clock === 1'b0);
-
-	initial begin
-		clock <= 0;
-	end
-
-	initial begin
-		$dumpfile("timer.vcd");
-		$dumpvars(0, timer_tb);
-
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (50) begin
-			repeat (1000) @(posedge clock);
-			$display("+1000 cycles");
-		end
-		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test GPIO (GL) Failed");
-		 $display("%c[0m",27);
-		$finish;
-	end
-
-	wire [37:0] mprj_io;	// Most of these are no-connects
-	wire [5:0] checkbits;
-	wire [31:0] countbits;
-
-	assign checkbits = mprj_io[37:32];
-	assign countbits = mprj_io[31:0];
-
-	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-	wire gpio;
-
-	// Monitor
-	initial begin
-		wait(checkbits == 6'h0a);
-		$display("Monitor: Test Timer (GL) Started");
-
-		/* Add checks here */
-		wait(checkbits == 6'h01);
-		$display("   countbits = 0x%x (should be 0xdcba7cf3)", countbits);
-		if(countbits !== 32'hdcba7cf3) begin
-		    $display("Monitor: Test Timer (GL) Failed");
-		    $finish;
-		end
-		wait(checkbits == 6'h02);
-		$display("   countbits = 0x%x (should be 0x11)", countbits);
-		if(countbits !== 32'h11) begin
-		    $display("Monitor: Test Timer (GL) Failed");
-		    $finish;
-		end
-		wait(checkbits == 6'h03);
-		$display("   countbits = %x (should be 0x0f)", countbits);
-		if(countbits !== 32'h0f) begin
-		    $display("Monitor: Test Timer (GL) Failed");
-		    $finish;
-		end
-		wait(checkbits == 6'h04);
-		$display("   countbits = %x (should be 0x0f)", countbits);
-		if(countbits !== 32'h0f) begin
-		    $display("Monitor: Test Timer (GL) Failed");
-		    $finish;
-		end
-		wait(checkbits == 6'h05);
-		$display("   countbits = %x (should be 0x12b4)", countbits);
-		if(countbits !== 32'h12b4) begin
-		    $display("Monitor: Test Timer (GL) Failed");
-		    $finish;
-		end
-
-		$display("Monitor: Test Timer (GL) Passed");
-		$finish;
-	end
-
-	initial begin
-		RSTB <= 1'b0;
-		#1000;
-		RSTB <= 1'b1;	    // Release reset
-	end
-
-	initial begin		// Power-up sequence
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		#200;
-		power1 <= 1'b1;
-		#200;
-		power2 <= 1'b1;
-	end
-
-	always @(checkbits) begin
-		#1 $display("Timer state = %b (%d)", countbits, countbits);
-	end
-
-	wire VDD3V3;
-	wire VDD1V8;
-	wire VSS;
-
-	assign VDD3V3 = power1;
-	assign VDD1V8 = power2;
-	assign VSS = 1'b0;
-
-	// These are the mappings of mprj_io GPIO pads that are set to
-	// specific functions on startup:
-	//
-	// JTAG      = mgmt_gpio_io[0]              (inout)
-	// SDO       = mgmt_gpio_io[1]              (output)
-	// SDI       = mgmt_gpio_io[2]              (input)
-	// CSB       = mgmt_gpio_io[3]              (input)
-	// SCK       = mgmt_gpio_io[4]              (input)
-	// ser_rx    = mgmt_gpio_io[5]              (input)
-	// ser_tx    = mgmt_gpio_io[6]              (output)
-	// irq       = mgmt_gpio_io[7]              (input)
-
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (VDD3V3),
-		.vdda2    (VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (VDD1V8),
-		.vccd2	  (VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock	  (clock),
-		.gpio     (gpio),
-		.mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("timer.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/uart/Makefile b/verilog/dv/caravel/mgmt_soc/uart/Makefile
index 004a876..e421c20 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/uart/Makefile
@@ -1,6 +1,7 @@
 # ---- Test patterns for project striVe ----
 FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
@@ -8,6 +9,8 @@
 GCC_PREFIX?=riscv32-unknown-elf
 PDK_PATH?=/ef/tech/SW/sky130A
 
+SIM?=RTL
+
 .SUFFIXES:
 
 PATTERN = uart
@@ -17,9 +20,15 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
 	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
+	$< -o $@ 
+else  
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
 
 %.vcd: %.vvp
 	vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
index fbfef25..298e882 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
@@ -82,7 +82,11 @@
 			$display("UART Test started");
 		end
 		else if(checkbits == 16'hAB00) begin
-			$display("UART Test passed");
+			`ifdef GL
+				$display("UART Test (GL) passed");
+			`else
+				$display("UART Test (RTL) passed");
+			`endif
 			$finish;
 		end
 	end
@@ -94,6 +98,8 @@
 	assign VDD3V3 = power1;
 	assign VDD1V8 = power2;
 	assign VSS = 1'b0;
+	
+	assign mprj_io[3] = 1'b1;  // Force CSB high.
 
 	caravel uut (
 		.vddio	  (VDD3V3),
diff --git a/verilog/dv/caravel/mgmt_soc/uart_gl/Makefile b/verilog/dv/caravel/mgmt_soc/uart_gl/Makefile
deleted file mode 100644
index 004a876..0000000
--- a/verilog/dv/caravel/mgmt_soc/uart_gl/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-# ---- Test patterns for project striVe ----
-FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../ 
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = uart
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
-	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/uart_gl/uart.c b/verilog/dv/caravel/mgmt_soc/uart_gl/uart.c
deleted file mode 100644
index 3f8d4c9..0000000
--- a/verilog/dv/caravel/mgmt_soc/uart_gl/uart.c
+++ /dev/null
@@ -1,59 +0,0 @@
-#include "../../defs.h"
-#include "../../stub.c"
-
-// --------------------------------------------------------
-
-void main()
-{
-    int j;
-
-    // Configure I/O:  High 16 bits of user area used for a 16-bit
-    // word to write and be detected by the testbench verilog.
-    // Only serial Tx line is used in this testbench.  It connects
-    // to mprj_io[6].  Since all lines of the chip are input or
-    // high impedence on startup, the I/O has to be configured
-    // for output
-
-    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    // Set clock to 64 kbaud and enable the UART.  It is important to do this
-    // before applying the configuration, or else the Tx line initializes as
-    // zero, which indicates the start of a byte to the receiver.
-
-    reg_uart_clkdiv = 625;
-    reg_uart_enable = 1;
-
-    // Now, apply the configuration
-    reg_mprj_xfer = 1;
-    while (reg_mprj_xfer == 1);
-
-    // Start test
-    reg_mprj_datal = 0xa0000000;
-
-    // This should appear at the output, received by the testbench UART.
-    // (Makes simulation time long.)
-    print("Monitor: Test UART (RTL) passed\n");
-
-    // Allow transmission to complete before signalling that the program
-    // has ended.
-    for (j = 0; j < 20; j++);
-    reg_mprj_datal = 0xab000000;
-}
diff --git a/verilog/dv/caravel/mgmt_soc/uart_gl/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart_gl/uart_tb.v
deleted file mode 100644
index b034591..0000000
--- a/verilog/dv/caravel/mgmt_soc/uart_gl/uart_tb.v
+++ /dev/null
@@ -1,142 +0,0 @@
-`default_nettype none
-/*
- *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
- *
- *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
- *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-`include "tbuart.v"
-
-module uart_tb;
-	reg clock;
-	reg RSTB;
-	reg power1, power2;
-
-	wire gpio;
-	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-	wire [37:0] mprj_io;
-	wire [15:0] checkbits;
-	wire uart_tx;
-	wire SDO;
-
-	assign checkbits = mprj_io[31:16];
-	assign uart_tx = mprj_io[6];
-
-	always #12.5 clock <= (clock === 1'b0);
-
-	initial begin
-		clock = 0;
-	end
-
-	initial begin
-		$dumpfile("uart.vcd");
-		$dumpvars(0, uart_tb);
-
-		$display("Wait for UART o/p");
-		repeat (150) begin
-			repeat (10000) @(posedge clock);
-			// Diagnostic. . . interrupts output pattern.
-		end
-		$finish;
-	end
-
-	initial begin
-		RSTB <= 1'b0;
-		#1000;
-		RSTB <= 1'b1;	    // Release reset
-		#2000;
-	end
-
-	initial begin		// Power-up sequence
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		#200;
-		power1 <= 1'b1;
-		#200;
-		power2 <= 1'b1;
-	end
-
-	always @(checkbits) begin
-		if(checkbits == 16'hA000) begin
-			$display("UART Test (GL) started");
-		end
-		else if(checkbits == 16'hAB00) begin
-			$display("UART Test (GL) passed");
-			$finish;
-		end
-	end
-
-	wire VDD3V3;
-	wire VDD1V8;
-	wire VSS;
-
-	assign VDD3V3 = power1;
-	assign VDD1V8 = power2;
-	assign VSS = 1'b0;
-
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (VDD3V3),
-		.vdda2    (VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (VDD1V8),
-		.vccd2	  (VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock	  (clock),
-		.gpio     (gpio),
-		.mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("uart.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-
-	// Testbench UART
-	tbuart tbuart (
-		.ser_rx(uart_tx)
-	);
-		
-endmodule
-`default_nettype wire
diff --git a/verilog/gl/mgmt_core.v b/verilog/gl/mgmt_core.v
index 8d03cdf..3cc7f78 100644
--- a/verilog/gl/mgmt_core.v
+++ b/verilog/gl/mgmt_core.v
@@ -30600,24 +30600,6 @@
   wire _30594_;
   wire _30595_;
   wire _30596_;
-  wire _30597_;
-  wire _30598_;
-  wire _30599_;
-  wire _30600_;
-  wire _30601_;
-  wire _30602_;
-  wire _30603_;
-  wire _30604_;
-  wire _30605_;
-  wire _30606_;
-  wire _30607_;
-  wire _30608_;
-  wire _30609_;
-  wire _30610_;
-  wire _30611_;
-  wire _30612_;
-  wire _30613_;
-  wire _30614_;
   wire clknet_0_clock;
   wire clknet_1_0_0_clock;
   wire clknet_1_1_0_clock;
@@ -31660,9 +31642,34 @@
   wire psn_net_1743;
   wire psn_net_1744;
   wire psn_net_1745;
+  wire psn_net_1746;
+  wire psn_net_1747;
+  wire psn_net_1748;
+  wire psn_net_1749;
   wire psn_net_175;
+  wire psn_net_1750;
+  wire psn_net_1751;
+  wire psn_net_1752;
+  wire psn_net_1753;
+  wire psn_net_1754;
+  wire psn_net_1755;
+  wire psn_net_1756;
+  wire psn_net_1757;
+  wire psn_net_1758;
+  wire psn_net_1759;
   wire psn_net_176;
+  wire psn_net_1760;
+  wire psn_net_1761;
+  wire psn_net_1762;
+  wire psn_net_1763;
+  wire psn_net_1764;
+  wire psn_net_1765;
+  wire psn_net_1766;
+  wire psn_net_1767;
+  wire psn_net_1768;
+  wire psn_net_1769;
   wire psn_net_177;
+  wire psn_net_1770;
   wire psn_net_178;
   wire psn_net_179;
   wire psn_net_18;
@@ -36043,77867 +36050,78140 @@
   wire \soc.wb_bridge.wb_ack_read[0] ;
   wire \soc.wb_bridge.wb_ack_read[1] ;
   output user_clk;
-  sky130_fd_sc_hd__diode_2 ANTENNA__30615__A1 (
-    .DIODE(_05004_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30615__A2 (
-    .DIODE(_05159_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30615__A3 (
-    .DIODE(_05163_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30615__B1 (
-    .DIODE(_05015_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30615__B2 (
-    .DIODE(_05162_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30616__A1 (
-    .DIODE(_05021_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30616__A2 (
-    .DIODE(_05164_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30616__B1 (
-    .DIODE(_04742_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30617__A1 (
-    .DIODE(_04651_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30617__A2 (
-    .DIODE(_04805_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30617__B1_N (
-    .DIODE(_04806_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30618__A1 (
-    .DIODE(_04753_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30618__A2 (
-    .DIODE(_04653_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30618__B1 (
-    .DIODE(_05160_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30618__B2 (
-    .DIODE(_04825_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30619__A (
-    .DIODE(_05086_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30619__B (
-    .DIODE(_05167_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30620__A1 (
-    .DIODE(_05063_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30620__A2 (
-    .DIODE(_05166_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30620__B1 (
-    .DIODE(_05141_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30620__C1 (
-    .DIODE(_05168_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30621__A (
-    .DIODE(_05158_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30621__B (
-    .DIODE(_05165_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30621__C (
-    .DIODE(_05169_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30622__A1 (
-    .DIODE(_05140_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30622__A2 (
-    .DIODE(_05170_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30622__B1 (
-    .DIODE(_29196_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30622__B2 (
-    .DIODE(_05137_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30623__A1 (
-    .DIODE(_05123_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30623__A2 (
-    .DIODE(_05171_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30623__B1 (
-    .DIODE(_04651_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30623__B2 (
-    .DIODE(_05139_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30624__A (
-    .DIODE(_05042_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30625__A1 (
-    .DIODE(_04758_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30625__A2 (
-    .DIODE(_04804_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30625__B1_N (
-    .DIODE(_04805_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30626__A (
-    .DIODE(_05172_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30626__B (
-    .DIODE(_05173_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30627__A (
-    .DIODE(_04609_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30628__A1 (
-    .DIODE(_04920_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30628__A2 (
-    .DIODE(_05175_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30628__B1 (
-    .DIODE(_04608_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30628__B2 (
-    .DIODE(_04921_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30629__A (
-    .DIODE(_04973_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30629__B (
-    .DIODE(_05176_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30630__A1 (
-    .DIODE(_05175_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30630__A2 (
-    .DIODE(_04976_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30630__B1 (
-    .DIODE(_04891_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30631__A (
-    .DIODE(_30225_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30631__B (
-    .DIODE(_04758_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30632__A (
-    .DIODE(_05079_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30632__B (
-    .DIODE(_04840_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30633__A1 (
-    .DIODE(_05110_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30633__A2 (
-    .DIODE(_05179_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30633__A3 (
-    .DIODE(_05180_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30633__B1 (
-    .DIODE(_04840_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30633__B2 (
-    .DIODE(_05133_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30634__A (
-    .DIODE(_05181_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30635__A1 (
-    .DIODE(_04608_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30635__A2 (
-    .DIODE(_04801_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30635__B1 (
-    .DIODE(_04874_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30635__C1 (
-    .DIODE(_05182_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30636__A1 (
-    .DIODE(_04905_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30636__A2 (
-    .DIODE(_05174_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30636__A3 (
-    .DIODE(_05177_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30636__B1 (
-    .DIODE(_05178_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30636__B2 (
-    .DIODE(_05183_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30637__A1 (
-    .DIODE(_04937_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30637__A2 (
-    .DIODE(_05184_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30637__B1 (
-    .DIODE(_29514_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30637__B2 (
-    .DIODE(_04880_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30638__A1 (
-    .DIODE(_05123_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30638__A2 (
-    .DIODE(_05185_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30638__B1 (
-    .DIODE(_04758_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30638__B2 (
-    .DIODE(_05139_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30639__A (
-    .DIODE(_29134_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30639__B (
-    .DIODE(_29164_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30639__C (
-    .DIODE(_29988_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30639__D (
-    .DIODE(_29322_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30640__A (
-    .DIODE(_05186_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30641__A (
-    .DIODE(_05187_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30642__A (
-    .DIODE(_05186_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30643__A (
-    .DIODE(la_oen[47]),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30643__B (
-    .DIODE(_05189_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30644__A1 (
-    .DIODE(_04556_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30644__A2 (
-    .DIODE(_05188_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30644__B1 (
-    .DIODE(_30001_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30644__C1 (
-    .DIODE(_05190_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30645__A (
-    .DIODE(_29307_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30646__A (
-    .DIODE(la_oen[46]),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30646__B (
-    .DIODE(_05189_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30647__A1 (
-    .DIODE(_04558_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30647__A2 (
-    .DIODE(_05188_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30647__B1 (
-    .DIODE(_05191_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30647__C1 (
-    .DIODE(_05192_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30648__A (
-    .DIODE(la_oen[45]),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30648__B (
-    .DIODE(_05189_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30649__A1 (
-    .DIODE(_04561_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30649__A2 (
-    .DIODE(_05188_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30649__B1 (
-    .DIODE(_05191_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30649__C1 (
-    .DIODE(_05193_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30650__A (
-    .DIODE(la_oen[44]),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30650__B (
-    .DIODE(_05189_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30651__A1 (
-    .DIODE(_04563_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30651__A2 (
-    .DIODE(_05188_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30651__B1 (
-    .DIODE(_05191_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30651__C1 (
-    .DIODE(_05194_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30652__A (
-    .DIODE(_05187_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30653__A (
-    .DIODE(_05186_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30654__A (
-    .DIODE(la_oen[43]),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30654__B (
-    .DIODE(_05196_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30655__A1 (
-    .DIODE(_04566_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30655__A2 (
-    .DIODE(_05195_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30655__B1 (
-    .DIODE(_05191_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30655__C1 (
-    .DIODE(_05197_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30656__A (
-    .DIODE(_29191_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30657__A (
-    .DIODE(_05198_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30658__A (
-    .DIODE(la_oen[42]),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30658__B (
-    .DIODE(_05196_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30659__A1 (
-    .DIODE(_04569_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30659__A2 (
-    .DIODE(_05195_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30659__B1 (
-    .DIODE(_05199_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30659__C1 (
-    .DIODE(_05200_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30660__A (
-    .DIODE(la_oen[41]),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30660__B (
-    .DIODE(_05196_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30661__A1 (
-    .DIODE(_04571_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30661__A2 (
-    .DIODE(_05195_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30661__B1 (
-    .DIODE(_05199_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30661__C1 (
-    .DIODE(_05201_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30662__A (
-    .DIODE(la_oen[40]),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30662__B (
-    .DIODE(_05196_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30663__A1 (
-    .DIODE(_04572_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30663__A2 (
-    .DIODE(_05195_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30663__B1 (
-    .DIODE(_05199_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30663__C1 (
-    .DIODE(_05202_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30664__A (
-    .DIODE(\clocking.divider.even_0.out_counter ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30665__A (
-    .DIODE(\clocking.divider.even_0.counter[2] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30666__A (
-    .DIODE(\clocking.divider.even_0.counter[1] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30667__A (
-    .DIODE(\clocking.divider.even_0.N[0] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30668__A (
-    .DIODE(_05206_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30669__A (
-    .DIODE(_05207_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30670__A (
-    .DIODE(_05204_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30670__B (
-    .DIODE(_05205_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30670__C (
-    .DIODE(_05208_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30670__D (
-    .DIODE(\clocking.divider.even_0.counter[0] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30671__A1_N (
-    .DIODE(_05203_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30671__A2_N (
-    .DIODE(_05209_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30671__B1 (
-    .DIODE(_05203_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30671__B2 (
-    .DIODE(_05209_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30672__A (
-    .DIODE(\clocking.divider.even_0.clk ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30673__A (
-    .DIODE(\clocking.divider.even_0.N[2] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30674__A (
-    .DIODE(\clocking.divider.even_0.N[1] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30675__A (
-    .DIODE(_05210_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30675__B (
-    .DIODE(_05211_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30676__A (
-    .DIODE(_05206_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30676__B (
-    .DIODE(_05212_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30677__A (
-    .DIODE(\clocking.divider.odd_0.initial_begin[2] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30677__B (
-    .DIODE(\clocking.divider.odd_0.initial_begin[1] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30678__A (
-    .DIODE(\clocking.divider.odd_0.rst_pulse ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30679__A1 (
-    .DIODE(_05213_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30679__A2 (
-    .DIODE(_05214_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30679__B1 (
-    .DIODE(_05215_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30680__A (
-    .DIODE(_05216_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30681__A (
-    .DIODE(_05217_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30682__A (
-    .DIODE(\clocking.divider.odd_0.counter2[0] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30683__A (
-    .DIODE(\clocking.divider.odd_0.counter2[2] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30683__B (
-    .DIODE(\clocking.divider.odd_0.counter2[1] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30683__C (
-    .DIODE(_05219_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30684__A (
-    .DIODE(_05215_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30684__B (
-    .DIODE(_05220_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30685__A (
-    .DIODE(_05221_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30686__A (
-    .DIODE(\clocking.divider.odd_0.out_counter2 ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30687__A (
-    .DIODE(\clocking.divider.odd_0.rst_pulse ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30688__A (
-    .DIODE(_05217_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30688__B (
-    .DIODE(_05221_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30688__C (
-    .DIODE(_05224_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30689__A1 (
-    .DIODE(_05218_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30689__A2 (
-    .DIODE(_05222_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30689__A3 (
-    .DIODE(_05223_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30689__B1 (
-    .DIODE(\clocking.divider.odd_0.out_counter2 ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30689__B2 (
-    .DIODE(_05225_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30690__A (
-    .DIODE(_05213_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30691__A (
-    .DIODE(\clocking.divider.odd_0.counter[0] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30692__A (
-    .DIODE(\clocking.divider.odd_0.counter[2] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30692__B (
-    .DIODE(\clocking.divider.odd_0.counter[1] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30692__C (
-    .DIODE(_05227_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30693__A (
-    .DIODE(_05226_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30693__B (
-    .DIODE(_05228_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30694__A (
-    .DIODE(_05224_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30695__A (
-    .DIODE(_05230_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30696__A (
-    .DIODE(\clocking.divider.odd_0.out_counter ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30696__B (
-    .DIODE(_05229_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30697__A1 (
-    .DIODE(\clocking.divider.odd_0.out_counter ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30697__A2 (
-    .DIODE(_05229_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30697__B1 (
-    .DIODE(_05231_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30697__C1 (
-    .DIODE(_05232_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30698__A (
-    .DIODE(\clocking.divider2.even_0.out_counter ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30699__A (
-    .DIODE(\clocking.divider2.even_0.counter[2] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30700__A (
-    .DIODE(\clocking.divider2.even_0.counter[1] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30701__A (
-    .DIODE(_29521_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30702__A (
-    .DIODE(_05236_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30703__A (
-    .DIODE(_05234_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30703__B (
-    .DIODE(_05235_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30703__C (
-    .DIODE(_05237_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30703__D (
-    .DIODE(\clocking.divider2.even_0.counter[0] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30704__A1_N (
-    .DIODE(_05233_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30704__A2_N (
-    .DIODE(_05238_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30704__B1 (
-    .DIODE(_05233_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30704__B2 (
-    .DIODE(_05238_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30705__A (
-    .DIODE(\clocking.divider2.even_0.clk ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30706__A (
-    .DIODE(\clocking.divider2.odd_0.initial_begin[2] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30706__B (
-    .DIODE(\clocking.divider2.odd_0.initial_begin[1] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30707__A (
-    .DIODE(\clocking.divider2.odd_0.rst_pulse ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30708__A1 (
-    .DIODE(_29525_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30708__A2 (
-    .DIODE(_05239_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30708__B1 (
-    .DIODE(_05240_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30709__A (
-    .DIODE(_05241_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30710__A (
-    .DIODE(_05242_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30711__A (
-    .DIODE(_05240_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30712__A (
-    .DIODE(\clocking.divider2.odd_0.counter2[0] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30713__A (
-    .DIODE(\clocking.divider2.odd_0.counter2[2] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30713__B (
-    .DIODE(\clocking.divider2.odd_0.counter2[1] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30713__C (
-    .DIODE(_05245_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30714__A (
-    .DIODE(_05244_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30714__B (
-    .DIODE(_05246_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30715__A (
-    .DIODE(_05247_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30716__A (
-    .DIODE(\clocking.divider2.odd_0.out_counter2 ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30717__A (
-    .DIODE(\clocking.divider2.odd_0.rst_pulse ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30718__A (
-    .DIODE(_05242_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30718__B (
-    .DIODE(_05247_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30718__C (
-    .DIODE(_05250_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30719__A1 (
-    .DIODE(_05243_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30719__A2 (
-    .DIODE(_05248_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30719__A3 (
-    .DIODE(_05249_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30719__B1 (
-    .DIODE(\clocking.divider2.odd_0.out_counter2 ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30719__B2 (
-    .DIODE(_05251_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30720__A (
-    .DIODE(_29097_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30721__A (
-    .DIODE(_05252_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30722__A (
-    .DIODE(_05253_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30723__A (
-    .DIODE(_05254_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30724__A (
-    .DIODE(_05255_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30725__A (
-    .DIODE(\soc.cpu.picorv32_core.cpu_state[1] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30726__A (
-    .DIODE(_05257_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30727__A (
-    .DIODE(_05258_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30728__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[31] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30728__B (
-    .DIODE(_05259_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30729__A (
-    .DIODE(\soc.cpu.picorv32_core.cpu_state[1] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30730__A (
-    .DIODE(_05261_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30731__A (
-    .DIODE(_05262_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30732__A (
-    .DIODE(_05263_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30733__A (
-    .DIODE(_05264_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30734__A (
-    .DIODE(_05265_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30735__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[31] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30736__A (
-    .DIODE(\soc.cpu.picorv32_core.latched_branch ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30737__A (
-    .DIODE(_05268_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30738__A (
-    .DIODE(\soc.cpu.picorv32_core.irq_state[0] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30739__A (
-    .DIODE(_05269_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30739__B (
-    .DIODE(_05270_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30740__A (
-    .DIODE(_05271_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30741__A (
-    .DIODE(_05272_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30742__A (
-    .DIODE(_05273_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30743__A (
-    .DIODE(_05274_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30744__A (
-    .DIODE(_05275_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30745__A (
-    .DIODE(_05276_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30746__A (
-    .DIODE(_05277_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30747__A (
-    .DIODE(_05278_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30748__A (
-    .DIODE(_05279_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30749__A (
-    .DIODE(_05280_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30750__A (
-    .DIODE(\soc.cpu.picorv32_core.latched_store ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30751__A (
-    .DIODE(_05282_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30752__A (
-    .DIODE(_05283_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30753__A (
-    .DIODE(_05284_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30754__A (
-    .DIODE(_05285_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30755__A (
-    .DIODE(_05286_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30756__A (
-    .DIODE(_05287_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30757__A (
-    .DIODE(_05288_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30758__A (
-    .DIODE(_05289_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30759__A (
-    .DIODE(_05290_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30760__A (
-    .DIODE(_05291_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30761__A (
-    .DIODE(_05292_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30762__A (
-    .DIODE(_05293_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30763__A (
-    .DIODE(\soc.cpu.picorv32_core.latched_stalu ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30764__A (
-    .DIODE(_05295_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30765__A (
-    .DIODE(_05296_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30766__A (
-    .DIODE(_05297_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30767__A (
-    .DIODE(_05298_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30768__A (
-    .DIODE(_05299_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30769__A (
-    .DIODE(_05300_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30770__A (
-    .DIODE(_05301_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30771__A (
-    .DIODE(_05302_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30772__A (
-    .DIODE(_05303_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30773__A (
+  sky130_fd_sc_hd__diode_2 ANTENNA__30597__A (
     .DIODE(_05304_),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR)
   );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30774__A (
-    .DIODE(\soc.cpu.picorv32_core.latched_stalu ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30775__A (
-    .DIODE(_05306_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30776__A (
-    .DIODE(_05307_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30777__A (
-    .DIODE(_05308_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30778__A (
-    .DIODE(_05309_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30779__A (
-    .DIODE(_05310_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30780__A (
-    .DIODE(_05311_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30781__A (
-    .DIODE(_05312_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30782__A (
-    .DIODE(_05313_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30783__A (
-    .DIODE(_05314_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30784__A1 (
+  sky130_fd_sc_hd__diode_2 ANTENNA__30598__A (
     .DIODE(_05305_),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR)
   );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30784__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[31] ),
+  sky130_fd_sc_hd__diode_2 ANTENNA__30599__A (
+    .DIODE(_05306_),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR)
   );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30784__B1 (
+  sky130_fd_sc_hd__diode_2 ANTENNA__30600__A (
+    .DIODE(_05307_),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__diode_2 ANTENNA__30601__A (
+    .DIODE(_05308_),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__diode_2 ANTENNA__30602__A (
+    .DIODE(_05309_),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__diode_2 ANTENNA__30603__A (
+    .DIODE(_05310_),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__diode_2 ANTENNA__30604__A (
+    .DIODE(_05311_),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__diode_2 ANTENNA__30605__A (
+    .DIODE(_05312_),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__diode_2 ANTENNA__30606__A (
+    .DIODE(_05313_),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__diode_2 ANTENNA__30607__A (
+    .DIODE(\soc.cpu.picorv32_core.latched_store ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__diode_2 ANTENNA__30608__A (
     .DIODE(_05315_),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR)
   );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30784__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[31] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30785__A (
-    .DIODE(\soc.cpu.picorv32_core.latched_branch ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30786__A (
-    .DIODE(_05317_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30787__A (
-    .DIODE(_05318_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30788__A (
-    .DIODE(_05319_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30789__A (
-    .DIODE(_05320_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30790__A (
-    .DIODE(_05321_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30791__A (
-    .DIODE(_05322_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30792__A (
-    .DIODE(_05323_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30793__A (
-    .DIODE(_05324_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30794__A (
-    .DIODE(_05325_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30795__A (
-    .DIODE(_05326_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30796__A1 (
-    .DIODE(_05294_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30796__A2 (
+  sky130_fd_sc_hd__diode_2 ANTENNA__30609__A (
     .DIODE(_05316_),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR)
   );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30796__B1 (
-    .DIODE(_05327_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30797__A (
-    .DIODE(_05281_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30797__B (
-    .DIODE(_05328_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30798__A (
-    .DIODE(\soc.cpu.picorv32_core.latched_store ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30799__A (
-    .DIODE(_05330_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30800__A (
-    .DIODE(_05331_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30801__A (
-    .DIODE(_05332_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30802__A (
-    .DIODE(_05333_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30803__A (
-    .DIODE(_05334_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30804__A (
-    .DIODE(_05335_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30805__A (
-    .DIODE(_05336_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30806__A (
-    .DIODE(_05337_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30807__A1_N (
-    .DIODE(_05267_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30807__A2_N (
-    .DIODE(_05329_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30807__B1 (
-    .DIODE(_05338_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30807__B2 (
-    .DIODE(_05328_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30808__A (
-    .DIODE(_05266_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30808__B (
-    .DIODE(_05339_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30809__A (
-    .DIODE(_05256_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30809__B (
-    .DIODE(_05260_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30809__C (
-    .DIODE(_05340_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30810__A (
-    .DIODE(_05257_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30811__A (
-    .DIODE(_05341_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30812__A (
-    .DIODE(_05342_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30813__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[30] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30814__A1 (
-    .DIODE(_05305_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30814__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[30] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30814__B1 (
-    .DIODE(_05315_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30814__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[30] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30815__A1 (
-    .DIODE(_05294_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30815__A2 (
-    .DIODE(_05345_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30815__B1 (
-    .DIODE(_05327_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30816__A (
-    .DIODE(_05281_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30816__B (
-    .DIODE(_05346_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30817__A1_N (
-    .DIODE(_05344_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30817__A2_N (
-    .DIODE(_05347_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30817__B1 (
-    .DIODE(_05338_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30817__B2 (
-    .DIODE(_05346_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30818__A (
-    .DIODE(_05348_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30819__A (
-    .DIODE(_05264_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30820__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[30] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30821__A (
-    .DIODE(_05351_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30822__A (
-    .DIODE(_05350_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30822__B (
-    .DIODE(_05352_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30823__A1 (
-    .DIODE(_05343_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30823__A2 (
-    .DIODE(_05349_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30823__B1 (
-    .DIODE(_29870_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30823__C1 (
-    .DIODE(_05353_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30824__A (
-    .DIODE(_05354_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30825__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[29] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30826__A1 (
-    .DIODE(_05304_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30826__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[29] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30826__B1 (
-    .DIODE(_05315_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30826__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[29] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30827__A1 (
-    .DIODE(_05293_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30827__A2 (
-    .DIODE(_05356_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30827__B1 (
-    .DIODE(_05326_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30828__A (
-    .DIODE(_05281_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30828__B (
-    .DIODE(_05357_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30829__A1_N (
-    .DIODE(_05355_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30829__A2_N (
-    .DIODE(_05358_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30829__B1 (
-    .DIODE(_05337_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30829__B2 (
-    .DIODE(_05357_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30830__A (
-    .DIODE(_05359_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30831__A (
-    .DIODE(_29840_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30832__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[29] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30833__A (
-    .DIODE(_05362_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30834__A (
-    .DIODE(_05350_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30834__B (
-    .DIODE(_05363_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30835__A1 (
-    .DIODE(_05343_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30835__A2 (
-    .DIODE(_05360_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30835__B1 (
-    .DIODE(_05361_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30835__C1 (
-    .DIODE(_05364_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30836__A (
-    .DIODE(_05365_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30837__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[28] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30838__A1 (
-    .DIODE(_05304_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30838__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[28] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30838__B1 (
-    .DIODE(_05314_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30838__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[28] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30839__A1 (
-    .DIODE(_05292_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30839__A2 (
-    .DIODE(_05367_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30839__B1 (
-    .DIODE(_05326_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30840__A (
-    .DIODE(_05280_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30840__B (
-    .DIODE(_05368_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30841__A1_N (
-    .DIODE(_05366_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30841__A2_N (
-    .DIODE(_05369_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30841__B1 (
-    .DIODE(_05337_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30841__B2 (
-    .DIODE(_05368_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30842__A (
-    .DIODE(_05264_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30843__A (
-    .DIODE(_05371_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30844__A (
-    .DIODE(_05372_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30844__B (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[28] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30845__A1 (
-    .DIODE(_05343_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30845__A2 (
-    .DIODE(_05370_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30845__B1 (
-    .DIODE(_05199_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30845__C1 (
-    .DIODE(_05373_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30846__A (
-    .DIODE(_05342_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30847__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[27] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30848__A1 (
-    .DIODE(_05304_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30848__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[27] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30848__B1 (
-    .DIODE(_05314_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30848__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[27] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30849__A1 (
-    .DIODE(_05293_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30849__A2 (
-    .DIODE(_05376_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30849__B1 (
-    .DIODE(_05326_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30850__A (
-    .DIODE(_05280_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30850__B (
-    .DIODE(_05377_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30851__A (
-    .DIODE(_05377_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30852__A1 (
-    .DIODE(_05375_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30852__A2 (
-    .DIODE(_05378_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30852__B1 (
-    .DIODE(_05293_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30852__B2 (
-    .DIODE(_05379_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30853__A (
-    .DIODE(_05380_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30854__A (
-    .DIODE(_05263_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30855__A (
-    .DIODE(_05382_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30856__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[27] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30857__A (
-    .DIODE(_05384_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30858__A (
-    .DIODE(_05383_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30858__B (
-    .DIODE(_05385_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30859__A1 (
-    .DIODE(_05374_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30859__A2 (
-    .DIODE(_05381_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30859__B1 (
-    .DIODE(_05361_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30859__C1 (
-    .DIODE(_05386_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30860__A (
-    .DIODE(_05387_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30861__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[26] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30862__A1 (
-    .DIODE(_05303_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30862__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[26] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30862__B1 (
-    .DIODE(_05314_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30862__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[26] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30863__A1 (
-    .DIODE(_05292_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30863__A2 (
-    .DIODE(_05389_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30863__B1 (
-    .DIODE(_05325_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30864__A (
-    .DIODE(_05280_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30864__B (
-    .DIODE(_05390_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30865__A1_N (
-    .DIODE(_05388_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30865__A2_N (
-    .DIODE(_05391_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30865__B1 (
-    .DIODE(_05336_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30865__B2 (
-    .DIODE(_05390_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30866__A (
-    .DIODE(_05392_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30867__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[26] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30868__A (
-    .DIODE(_05394_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30869__A (
-    .DIODE(_05383_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30869__B (
-    .DIODE(_05395_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30870__A1 (
-    .DIODE(_05374_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30870__A2 (
-    .DIODE(_05393_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30870__B1 (
-    .DIODE(_05361_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30870__C1 (
-    .DIODE(_05396_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30871__A (
-    .DIODE(_05397_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30872__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[25] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30873__A1 (
-    .DIODE(_05303_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30873__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[25] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30873__B1 (
-    .DIODE(_05313_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30873__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[25] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30874__A1 (
-    .DIODE(_05291_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30874__A2 (
-    .DIODE(_05399_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30874__B1 (
-    .DIODE(_05325_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30875__A (
-    .DIODE(_05279_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30875__B (
-    .DIODE(_05400_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30876__A1_N (
-    .DIODE(_05398_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30876__A2_N (
-    .DIODE(_05401_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30876__B1 (
-    .DIODE(_05336_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30876__B2 (
-    .DIODE(_05400_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30877__A (
-    .DIODE(_05402_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30878__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[25] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30879__A (
-    .DIODE(_05404_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30880__A (
-    .DIODE(_05383_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30880__B (
-    .DIODE(_05405_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30881__A1 (
-    .DIODE(_05374_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30881__A2 (
-    .DIODE(_05403_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30881__B1 (
-    .DIODE(_05361_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30881__C1 (
-    .DIODE(_05406_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30882__A (
-    .DIODE(_05407_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30883__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[24] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30884__A1 (
-    .DIODE(_05302_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30884__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[24] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30884__B1 (
-    .DIODE(_05313_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30884__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[24] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30885__A1 (
-    .DIODE(_05291_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30885__A2 (
-    .DIODE(_05409_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30885__B1 (
-    .DIODE(_05324_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30886__A (
-    .DIODE(_05279_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30886__B (
-    .DIODE(_05410_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30887__A1_N (
-    .DIODE(_05408_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30887__A2_N (
-    .DIODE(_05411_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30887__B1 (
-    .DIODE(_05336_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30887__B2 (
-    .DIODE(_05410_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30888__A (
-    .DIODE(_05412_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30889__A (
-    .DIODE(_29778_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30890__A (
-    .DIODE(_05414_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30891__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[24] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30892__A (
-    .DIODE(_05416_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30893__A (
-    .DIODE(_05383_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30893__B (
-    .DIODE(_05417_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30894__A1 (
-    .DIODE(_05374_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30894__A2 (
-    .DIODE(_05413_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30894__B1 (
-    .DIODE(_05415_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30894__C1 (
-    .DIODE(_05418_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30895__A (
-    .DIODE(_05419_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30896__A (
-    .DIODE(_05342_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30897__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[23] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30898__A1 (
-    .DIODE(_05303_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30898__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[23] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30898__B1 (
-    .DIODE(_05313_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30898__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[23] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30899__A1 (
-    .DIODE(_05291_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30899__A2 (
-    .DIODE(_05422_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30899__B1 (
-    .DIODE(_05325_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30900__A (
-    .DIODE(_05279_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30900__B (
-    .DIODE(_05423_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30901__A (
-    .DIODE(_05423_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30902__A1 (
-    .DIODE(_05421_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30902__A2 (
-    .DIODE(_05424_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30902__B1 (
-    .DIODE(_05292_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30902__B2 (
-    .DIODE(_05425_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30903__A (
-    .DIODE(_05426_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30904__A (
-    .DIODE(_05382_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30905__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[23] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30906__A (
-    .DIODE(_05429_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30907__A (
-    .DIODE(_05428_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30907__B (
-    .DIODE(_05430_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30908__A1 (
-    .DIODE(_05420_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30908__A2 (
-    .DIODE(_05427_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30908__B1 (
-    .DIODE(_05415_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30908__C1 (
-    .DIODE(_05431_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30909__A (
-    .DIODE(_05432_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30910__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[22] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30911__A1 (
-    .DIODE(_05302_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30911__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[22] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30911__B1 (
-    .DIODE(_05312_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30911__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[22] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30912__A1 (
-    .DIODE(_05290_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30912__A2 (
-    .DIODE(_05434_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30912__B1 (
-    .DIODE(_05324_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30913__A (
-    .DIODE(_05278_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30913__B (
-    .DIODE(_05435_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30914__A1_N (
-    .DIODE(_05433_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30914__A2_N (
-    .DIODE(_05436_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30914__B1 (
-    .DIODE(_05335_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30914__B2 (
-    .DIODE(_05435_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30915__A (
-    .DIODE(_05437_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30916__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[22] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30917__A (
-    .DIODE(_05439_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30918__A (
-    .DIODE(_05428_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30918__B (
-    .DIODE(_05440_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30919__A1 (
-    .DIODE(_05420_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30919__A2 (
-    .DIODE(_05438_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30919__B1 (
-    .DIODE(_05415_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30919__C1 (
-    .DIODE(_05441_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30920__A (
-    .DIODE(_05442_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30921__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[21] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30922__A1 (
-    .DIODE(_05302_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30922__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[21] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30922__B1 (
-    .DIODE(_05312_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30922__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[21] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30923__A1 (
-    .DIODE(_05290_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30923__A2 (
-    .DIODE(_05444_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30923__B1 (
-    .DIODE(_05324_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30924__A (
-    .DIODE(_05278_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30924__B (
-    .DIODE(_05445_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30925__A1_N (
-    .DIODE(_05443_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30925__A2_N (
-    .DIODE(_05446_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30925__B1 (
-    .DIODE(_05335_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30925__B2 (
-    .DIODE(_05445_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30926__A (
-    .DIODE(_05447_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30927__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[21] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30928__A (
-    .DIODE(_05449_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30929__A (
-    .DIODE(_05428_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30929__B (
-    .DIODE(_05450_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30930__A1 (
-    .DIODE(_05420_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30930__A2 (
-    .DIODE(_05448_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30930__B1 (
-    .DIODE(_05415_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30930__C1 (
-    .DIODE(_05451_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30931__A (
-    .DIODE(_05452_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30932__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[20] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30933__A1 (
-    .DIODE(_05301_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30933__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[20] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30933__B1 (
-    .DIODE(_05312_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30933__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[20] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30934__A1 (
-    .DIODE(_05289_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30934__A2 (
-    .DIODE(_05454_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30934__B1 (
-    .DIODE(_05323_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30935__A (
-    .DIODE(_05278_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30935__B (
-    .DIODE(_05455_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30936__A1_N (
-    .DIODE(_05453_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30936__A2_N (
-    .DIODE(_05456_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30936__B1 (
-    .DIODE(_05335_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30936__B2 (
-    .DIODE(_05455_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30937__A (
-    .DIODE(_05457_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30938__A (
-    .DIODE(_05458_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30939__A (
-    .DIODE(_05414_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30940__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[20] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30941__A (
-    .DIODE(_05461_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30942__A (
-    .DIODE(_05428_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30942__B (
-    .DIODE(_05462_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30943__A1 (
-    .DIODE(_05420_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30943__A2 (
-    .DIODE(_05459_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30943__B1 (
-    .DIODE(_05460_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30943__C1 (
-    .DIODE(_05463_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30944__A (
-    .DIODE(_05464_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30945__A (
-    .DIODE(_05341_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30946__A (
-    .DIODE(_05465_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30947__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[19] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30948__A1 (
-    .DIODE(_05301_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30948__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[19] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30948__B1 (
-    .DIODE(_05311_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30948__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[19] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30949__A1 (
-    .DIODE(_05289_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30949__A2 (
-    .DIODE(_05468_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30949__B1 (
-    .DIODE(_05323_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30950__A (
-    .DIODE(_05277_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30950__B (
-    .DIODE(_05469_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30951__A (
-    .DIODE(_05469_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30952__A1 (
-    .DIODE(_05467_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30952__A2 (
-    .DIODE(_05470_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30952__B1 (
-    .DIODE(_05290_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30952__B2 (
-    .DIODE(_05471_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30953__A (
-    .DIODE(_05472_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30954__A (
-    .DIODE(_05382_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30955__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[19] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30956__A (
-    .DIODE(_05475_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30957__A (
-    .DIODE(_05474_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30957__B (
-    .DIODE(_05476_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30958__A1 (
-    .DIODE(_05466_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30958__A2 (
-    .DIODE(_05473_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30958__B1 (
-    .DIODE(_05460_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30958__C1 (
-    .DIODE(_05477_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30959__A (
-    .DIODE(_05478_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30960__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[18] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30961__A1 (
-    .DIODE(_05301_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30961__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[18] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30961__B1 (
-    .DIODE(_05311_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30961__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[18] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30962__A1 (
-    .DIODE(_05289_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30962__A2 (
-    .DIODE(_05480_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30962__B1 (
-    .DIODE(_05323_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30963__A (
-    .DIODE(_05277_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30963__B (
-    .DIODE(_05481_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30964__A1_N (
-    .DIODE(_05479_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30964__A2_N (
-    .DIODE(_05482_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30964__B1 (
-    .DIODE(_05334_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30964__B2 (
-    .DIODE(_05481_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30965__A (
-    .DIODE(_05483_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30966__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[18] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30967__A (
-    .DIODE(_05485_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30968__A (
-    .DIODE(_05474_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30968__B (
-    .DIODE(_05486_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30969__A1 (
-    .DIODE(_05466_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30969__A2 (
-    .DIODE(_05484_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30969__B1 (
-    .DIODE(_05460_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30969__C1 (
-    .DIODE(_05487_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30970__A (
-    .DIODE(_05488_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30971__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[17] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30972__A1 (
-    .DIODE(_05300_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30972__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[17] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30972__B1 (
-    .DIODE(_05311_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30972__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[17] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30973__A1 (
-    .DIODE(_05288_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30973__A2 (
-    .DIODE(_05490_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30973__B1 (
-    .DIODE(_05322_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30974__A (
-    .DIODE(_05277_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30974__B (
-    .DIODE(_05491_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30975__A1_N (
-    .DIODE(_05489_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30975__A2_N (
-    .DIODE(_05492_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30975__B1 (
-    .DIODE(_05334_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30975__B2 (
-    .DIODE(_05491_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30976__A (
-    .DIODE(_05493_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30977__A (
-    .DIODE(_05494_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30978__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[17] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30979__A (
-    .DIODE(_05496_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30980__A (
-    .DIODE(_05474_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30980__B (
-    .DIODE(_05497_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30981__A1 (
-    .DIODE(_05466_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30981__A2 (
-    .DIODE(_05495_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30981__B1 (
-    .DIODE(_05460_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30981__C1 (
-    .DIODE(_05498_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30982__A (
-    .DIODE(_05499_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30983__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[16] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30984__A1 (
-    .DIODE(_05300_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30984__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[16] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30984__B1 (
-    .DIODE(_05310_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30984__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[16] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30985__A1 (
-    .DIODE(_05288_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30985__A2 (
-    .DIODE(_05501_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30985__B1 (
-    .DIODE(_05322_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30986__A (
-    .DIODE(_05276_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30986__B (
-    .DIODE(_05502_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30987__A1_N (
-    .DIODE(_05500_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30987__A2_N (
-    .DIODE(_05503_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30987__B1 (
-    .DIODE(_05334_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30987__B2 (
-    .DIODE(_05502_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30988__A (
-    .DIODE(_05504_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30989__A (
-    .DIODE(_05505_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30990__A (
-    .DIODE(_05414_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30991__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[16] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30992__A (
-    .DIODE(_05508_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30993__A (
-    .DIODE(_05474_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30993__B (
-    .DIODE(_05509_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30994__A1 (
-    .DIODE(_05466_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30994__A2 (
-    .DIODE(_05506_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30994__B1 (
-    .DIODE(_05507_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30994__C1 (
-    .DIODE(_05510_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30995__A (
-    .DIODE(_05511_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30996__A (
-    .DIODE(_05465_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30997__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[15] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30998__A1 (
-    .DIODE(_05300_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30998__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[15] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30998__B1 (
-    .DIODE(_05310_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30998__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[15] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30999__A1 (
-    .DIODE(_05287_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30999__A2 (
-    .DIODE(_05514_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__30999__B1 (
-    .DIODE(_05322_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31000__A (
-    .DIODE(_05276_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31000__B (
-    .DIODE(_05515_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31001__A (
-    .DIODE(_05515_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31002__A1 (
-    .DIODE(_05513_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31002__A2 (
-    .DIODE(_05516_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31002__B1 (
-    .DIODE(_05288_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31002__B2 (
-    .DIODE(_05517_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31003__A (
-    .DIODE(_05518_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31004__A (
-    .DIODE(_05263_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31005__A (
-    .DIODE(_05520_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31006__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[15] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31007__A (
-    .DIODE(_05522_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31008__A (
-    .DIODE(_05521_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31008__B (
-    .DIODE(_05523_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31009__A1 (
-    .DIODE(_05512_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31009__A2 (
-    .DIODE(_05519_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31009__B1 (
-    .DIODE(_05507_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31009__C1 (
-    .DIODE(_05524_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31010__A (
-    .DIODE(_05525_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31011__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[14] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31012__A1 (
-    .DIODE(_05299_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31012__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[14] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31012__B1 (
-    .DIODE(_05310_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31012__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[14] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31013__A1 (
-    .DIODE(_05287_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31013__A2 (
-    .DIODE(_05527_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31013__B1 (
-    .DIODE(_05321_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31014__A (
-    .DIODE(_05276_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31014__B (
-    .DIODE(_05528_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31015__A1_N (
-    .DIODE(_05526_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31015__A2_N (
-    .DIODE(_05529_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31015__B1 (
-    .DIODE(_05333_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31015__B2 (
-    .DIODE(_05528_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31016__A (
-    .DIODE(_05530_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31017__A (
-    .DIODE(_05531_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31018__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[14] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31019__A (
-    .DIODE(_05533_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31020__A (
-    .DIODE(_05521_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31020__B (
-    .DIODE(_05534_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31021__A1 (
-    .DIODE(_05512_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31021__A2 (
-    .DIODE(_05532_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31021__B1 (
-    .DIODE(_05507_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31021__C1 (
-    .DIODE(_05535_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31022__A (
-    .DIODE(_05536_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31023__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[13] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31024__A1 (
-    .DIODE(_05299_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31024__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[13] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31024__B1 (
-    .DIODE(_05309_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31024__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[13] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31025__A1 (
-    .DIODE(_05287_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31025__A2 (
-    .DIODE(_05538_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31025__B1 (
-    .DIODE(_05321_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31026__A (
-    .DIODE(_05275_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31026__B (
-    .DIODE(_05539_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31027__A1_N (
-    .DIODE(_05537_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31027__A2_N (
-    .DIODE(_05540_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31027__B1 (
-    .DIODE(_05333_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31027__B2 (
-    .DIODE(_05539_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31028__A (
-    .DIODE(_05541_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31029__A (
-    .DIODE(_05542_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31030__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[13] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31031__A (
-    .DIODE(_05544_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31032__A (
-    .DIODE(_05521_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31032__B (
-    .DIODE(_05545_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31033__A1 (
-    .DIODE(_05512_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31033__A2 (
-    .DIODE(_05543_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31033__B1 (
-    .DIODE(_05507_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31033__C1 (
-    .DIODE(_05546_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31034__A (
-    .DIODE(_05547_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31035__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[12] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31036__A1 (
-    .DIODE(_05299_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31036__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[12] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31036__B1 (
-    .DIODE(_05309_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31036__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[12] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31037__A1 (
-    .DIODE(_05286_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31037__A2 (
-    .DIODE(_05549_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31037__B1 (
-    .DIODE(_05321_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31038__A (
-    .DIODE(_05275_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31038__B (
-    .DIODE(_05550_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31039__A1_N (
-    .DIODE(_05548_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31039__A2_N (
-    .DIODE(_05551_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31039__B1 (
-    .DIODE(_05333_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31039__B2 (
-    .DIODE(_05550_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31040__A (
-    .DIODE(_05552_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31041__A (
-    .DIODE(_05553_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31042__A (
-    .DIODE(_05414_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31043__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[12] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31044__A (
-    .DIODE(_05556_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31045__A (
-    .DIODE(_05521_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31045__B (
-    .DIODE(_05557_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31046__A1 (
-    .DIODE(_05512_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31046__A2 (
-    .DIODE(_05554_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31046__B1 (
-    .DIODE(_05555_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31046__C1 (
-    .DIODE(_05558_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31047__A (
-    .DIODE(_05559_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31048__A (
-    .DIODE(_05465_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31049__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[11] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31050__A1 (
-    .DIODE(_05298_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31050__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[11] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31050__B1 (
-    .DIODE(_05309_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31050__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[11] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31051__A1 (
-    .DIODE(_05286_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31051__A2 (
-    .DIODE(_05562_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31051__B1 (
-    .DIODE(_05320_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31052__A (
-    .DIODE(_05275_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31052__B (
-    .DIODE(_05563_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31053__A (
-    .DIODE(_05563_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31054__A1 (
-    .DIODE(_05561_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31054__A2 (
-    .DIODE(_05564_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31054__B1 (
-    .DIODE(_05286_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31054__B2 (
-    .DIODE(_05565_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31055__A (
-    .DIODE(_05566_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31056__A (
-    .DIODE(_05520_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31057__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[11] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31058__A (
-    .DIODE(_05569_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31059__A (
-    .DIODE(_05568_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31059__B (
-    .DIODE(_05570_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31060__A1 (
-    .DIODE(_05560_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31060__A2 (
-    .DIODE(_05567_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31060__B1 (
-    .DIODE(_05555_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31060__C1 (
-    .DIODE(_05571_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31061__A (
-    .DIODE(_05572_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31062__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[10] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31063__A1 (
-    .DIODE(_05298_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31063__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[10] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31063__B1 (
-    .DIODE(_05308_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31063__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[10] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31064__A1 (
-    .DIODE(_05285_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31064__A2 (
-    .DIODE(_05574_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31064__B1 (
-    .DIODE(_05320_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31065__A (
-    .DIODE(_05274_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31065__B (
-    .DIODE(_05575_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31066__A1_N (
-    .DIODE(_05573_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31066__A2_N (
-    .DIODE(_05576_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31066__B1 (
-    .DIODE(_05332_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31066__B2 (
-    .DIODE(_05575_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31067__A (
-    .DIODE(_05577_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31068__A (
-    .DIODE(_05578_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31069__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[10] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31070__A (
-    .DIODE(_05580_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31071__A (
-    .DIODE(_05568_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31071__B (
-    .DIODE(_05581_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31072__A1 (
-    .DIODE(_05560_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31072__A2 (
-    .DIODE(_05579_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31072__B1 (
-    .DIODE(_05555_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31072__C1 (
-    .DIODE(_05582_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31073__A (
-    .DIODE(_05583_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31074__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[9] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31075__A1 (
-    .DIODE(_05298_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31075__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[9] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31075__B1 (
-    .DIODE(_05308_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31075__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[9] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31076__A1 (
-    .DIODE(_05285_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31076__A2 (
-    .DIODE(_05585_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31076__B1 (
-    .DIODE(_05320_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31077__A (
-    .DIODE(_05274_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31077__B (
-    .DIODE(_05586_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31078__A1_N (
-    .DIODE(_05584_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31078__A2_N (
-    .DIODE(_05587_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31078__B1 (
-    .DIODE(_05332_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31078__B2 (
-    .DIODE(_05586_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31079__A (
-    .DIODE(_05588_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31080__A (
-    .DIODE(_05589_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31081__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[9] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31082__A (
-    .DIODE(_05591_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31083__A (
-    .DIODE(_05568_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31083__B (
-    .DIODE(_05592_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31084__A1 (
-    .DIODE(_05560_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31084__A2 (
-    .DIODE(_05590_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31084__B1 (
-    .DIODE(_05555_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31084__C1 (
-    .DIODE(_05593_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31085__A (
-    .DIODE(_05594_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31086__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[8] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31087__A1 (
-    .DIODE(_05297_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31087__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[8] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31087__B1 (
-    .DIODE(_05308_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31087__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[8] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31088__A1 (
-    .DIODE(_05284_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31088__A2 (
-    .DIODE(_05596_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31088__B1 (
-    .DIODE(_05319_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31089__A (
-    .DIODE(_05274_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31089__B (
-    .DIODE(_05597_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31090__A1_N (
-    .DIODE(_05595_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31090__A2_N (
-    .DIODE(_05598_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31090__B1 (
-    .DIODE(_05332_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31090__B2 (
-    .DIODE(_05597_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31091__A (
-    .DIODE(_05599_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31092__A (
-    .DIODE(_05600_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31093__A (
-    .DIODE(_29778_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31094__A (
-    .DIODE(_05602_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31095__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[8] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31096__A (
-    .DIODE(_05604_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31097__A (
-    .DIODE(_05568_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31097__B (
-    .DIODE(_05605_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31098__A1 (
-    .DIODE(_05560_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31098__A2 (
-    .DIODE(_05601_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31098__B1 (
-    .DIODE(_05603_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31098__C1 (
-    .DIODE(_05606_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31099__A (
-    .DIODE(_05607_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31100__A (
-    .DIODE(_05465_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31101__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[7] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31102__A1 (
-    .DIODE(_05297_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31102__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[7] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31102__B1 (
-    .DIODE(_05307_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31102__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[7] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31103__A1 (
-    .DIODE(_05284_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31103__A2 (
-    .DIODE(_05610_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31103__B1 (
-    .DIODE(_05319_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31104__A (
-    .DIODE(_05273_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31104__B (
-    .DIODE(_05611_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31105__A (
-    .DIODE(_05611_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31106__A1 (
-    .DIODE(_05609_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31106__A2 (
-    .DIODE(_05612_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31106__B1 (
-    .DIODE(_05285_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31106__B2 (
-    .DIODE(_05613_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31107__A (
-    .DIODE(_05614_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31108__A (
-    .DIODE(_05520_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31109__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[7] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31110__A (
-    .DIODE(_05617_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31111__A (
-    .DIODE(_05616_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31111__B (
-    .DIODE(_05618_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31112__A1 (
-    .DIODE(_05608_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31112__A2 (
-    .DIODE(_05615_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31112__B1 (
-    .DIODE(_05603_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31112__C1 (
-    .DIODE(_05619_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31113__A (
-    .DIODE(_05620_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31114__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[6] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31115__A1 (
-    .DIODE(_05297_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31115__A2 (
-    .DIODE(\soc.cpu.picorv32_core.alu_out_q[6] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31115__B1 (
-    .DIODE(_05307_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31115__B2 (
-    .DIODE(\soc.cpu.picorv32_core.reg_out[6] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31116__A1 (
-    .DIODE(_05284_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31116__A2 (
-    .DIODE(_05622_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31116__B1 (
-    .DIODE(_05319_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31117__A (
-    .DIODE(_05273_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31117__B (
-    .DIODE(_05623_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31118__A1_N (
-    .DIODE(_05621_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31118__A2_N (
-    .DIODE(_05624_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31118__B1 (
-    .DIODE(_05331_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31118__B2 (
-    .DIODE(_05623_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31119__A (
-    .DIODE(_05625_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31120__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_pc[6] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31121__A (
-    .DIODE(_05627_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31122__A (
-    .DIODE(_05616_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31122__B (
-    .DIODE(_05628_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31123__A1 (
-    .DIODE(_05608_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31123__A2 (
-    .DIODE(_05626_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31123__B1 (
-    .DIODE(_05603_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31123__C1 (
-    .DIODE(_05629_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31124__A (
-    .DIODE(_05630_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hd__diode_2 ANTENNA__31125__A (
-    .DIODE(\soc.cpu.picorv32_core.reg_next_pc[5] ),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );