blob: 1b9efa60768edbda864f28f53b13cadfeac8857a [file] [log] [blame]
iverilog -o simv.vvp -I /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload -I /project/fun/openlane/caravel_fwpayload-main/verilog/rtl -I /project/fun/openlane/pdk_root-mpw-one-a/open_pdks/sky130/sky130A -I /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl -I /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwprotocol-defs/src/sv -D SIM -D FUNCTIONAL -D TEST_FIRMWARE_HEX=\"fullchip_smoke.hex\" -D MPRJ_IO_PADS=38 -D IVERILOG -D HAVE_HDL_CLOCKGEN /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/defines.v /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/caravel.v /project/fun/openlane/caravel_fwpayload-main/verilog/dv/caravel/spiflash.v /project/fun/openlane/caravel_fwpayload-main/verilog/dv/caravel/tbuart.v /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwpayload.v /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_arb.v /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/spram_32x256.sv /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/spram_32x512.sv /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/spram.v /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_fetch.sv /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_tracer.sv /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_wb.sv /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_c_decode.sv /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_rv32im.sv /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mul_div_shift.sv /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_rv32i.sv /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_alu.sv /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_rv32imc.sv /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_rv32i_wb.sv /project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mem.sv /project/fun/openlane/caravel_fwpayload-main/verilog/dv/fwpayload/common/sv/fullchip_tb.v pybfms_gen.v
/project/fun/openlane/pdk_root-mpw-one-a/open_pdks/sky130/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: choosing typ expression.
/project/fun/openlane/pdk_root-mpw-one-a/open_pdks/sky130/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: choosing typ expression.
/project/fun/openlane/pdk_root-mpw-one-a/open_pdks/sky130/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: choosing typ expression.
/project/fun/openlane/pdk_root-mpw-one-a/open_pdks/sky130/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: choosing typ expression.
/project/fun/openlane/pdk_root-mpw-one-a/open_pdks/sky130/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: choosing typ expression.
/project/fun/openlane/pdk_root-mpw-one-a/open_pdks/sky130/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: choosing typ expression.
/project/fun/openlane/pdk_root-mpw-one-a/open_pdks/sky130/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: choosing typ expression.
/project/fun/openlane/pdk_root-mpw-one-a/open_pdks/sky130/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: choosing typ expression.
/project/fun/openlane/pdk_root-mpw-one-a/open_pdks/sky130/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: choosing typ expression.
/project/fun/openlane/pdk_root-mpw-one-a/open_pdks/sky130/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: choosing typ expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/caravel.v:252: warning: input port clock is coerced to inout.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:82: warning: Port 4 (next_pc_seq) of fwrisc_fetch expects 1 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:82: : Pruning 31 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:109: warning: Port 8 (ra_raddr) of fwrisc_decode expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:109: : Padding 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:109: warning: Port 10 (rb_raddr) of fwrisc_decode expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:109: : Padding 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:148: warning: Port 9 (op) of fwrisc_exec expects 6 bits, got 4.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:148: : Padding 2 high bits of the port.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:148: warning: Port 16 (pc_seq) of fwrisc_exec expects 1 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:148: : Padding 31 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:180: warning: Port 5 (ra_raddr) of fwrisc_regfile expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:180: : Pruning 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:180: warning: Port 7 (rb_raddr) of fwrisc_regfile expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:180: : Pruning 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:197: warning: Port 6 (ra_raddr) of fwrisc_tracer expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:197: : Pruning 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:197: warning: Port 8 (rb_raddr) of fwrisc_tracer expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:197: : Pruning 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwpayload.v:243: warning: Port 2 (a_adr) of spram_32x256 expects 8 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwpayload.v:243: : Pruning 24 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/user_proj_example.v:228: warning: Port 17 (wba_adr_i) of fwpayload expects 16 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/user_proj_example.v:228: : Pruning 16 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/dv/fwpayload/common/sv/fullchip_tb.v:108: warning: input port clock is coerced to inout.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:82: warning: Port 4 (next_pc_seq) of fwrisc_fetch expects 1 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:82: : Pruning 31 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:109: warning: Port 8 (ra_raddr) of fwrisc_decode expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:109: : Padding 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:109: warning: Port 10 (rb_raddr) of fwrisc_decode expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:109: : Padding 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:148: warning: Port 9 (op) of fwrisc_exec expects 6 bits, got 4.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:148: : Padding 2 high bits of the port.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:148: warning: Port 16 (pc_seq) of fwrisc_exec expects 1 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:148: : Padding 31 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:180: warning: Port 5 (ra_raddr) of fwrisc_regfile expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:180: : Pruning 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:180: warning: Port 7 (rb_raddr) of fwrisc_regfile expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:180: : Pruning 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:197: warning: Port 6 (ra_raddr) of fwrisc_tracer expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:197: : Pruning 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:197: warning: Port 8 (rb_raddr) of fwrisc_tracer expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:197: : Pruning 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:82: warning: Port 4 (next_pc_seq) of fwrisc_fetch expects 1 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:82: : Pruning 31 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:109: warning: Port 8 (ra_raddr) of fwrisc_decode expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:109: : Padding 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:109: warning: Port 10 (rb_raddr) of fwrisc_decode expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:109: : Padding 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:148: warning: Port 9 (op) of fwrisc_exec expects 6 bits, got 4.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:148: : Padding 2 high bits of the port.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:148: warning: Port 16 (pc_seq) of fwrisc_exec expects 1 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:148: : Padding 31 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:180: warning: Port 5 (ra_raddr) of fwrisc_regfile expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:180: : Pruning 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:180: warning: Port 7 (rb_raddr) of fwrisc_regfile expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:180: : Pruning 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:197: warning: Port 6 (ra_raddr) of fwrisc_tracer expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:197: : Pruning 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:197: warning: Port 8 (rb_raddr) of fwrisc_tracer expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:197: : Pruning 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:82: warning: Port 4 (next_pc_seq) of fwrisc_fetch expects 1 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:82: : Pruning 31 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:109: warning: Port 8 (ra_raddr) of fwrisc_decode expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:109: : Padding 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:109: warning: Port 10 (rb_raddr) of fwrisc_decode expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:109: : Padding 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:148: warning: Port 9 (op) of fwrisc_exec expects 6 bits, got 4.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:148: : Padding 2 high bits of the port.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:148: warning: Port 16 (pc_seq) of fwrisc_exec expects 1 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:148: : Padding 31 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:180: warning: Port 5 (ra_raddr) of fwrisc_regfile expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:180: : Pruning 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:180: warning: Port 7 (rb_raddr) of fwrisc_regfile expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:180: : Pruning 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:197: warning: Port 6 (ra_raddr) of fwrisc_tracer expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:197: : Pruning 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:197: warning: Port 8 (rb_raddr) of fwrisc_tracer expects 6 bits, got 32.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:197: : Pruning 26 high bits of the expression.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/spram_32x512.sv:21: warning: Port 2 (a_adr) of spram_byte_en expects 9 bits, got 8.
/project/fun/openlane/caravel_fwpayload-main/verilog/rtl/fwpayload/spram_32x512.sv:21: : Padding 1 high bits of the port.
vvp -m /project/fun/openlane/caravel_fwpayload-main/packages/pybfms/src/libpybfms.so -m /project/fun/openlane/caravel_fwpayload-main/packages/python/lib64/python3.6/site-packages/cocotb/libs/libcocotbvpi_icarus.vpl simv.vvp +timeout=1000000 +dumpvars
-.--ns INFO cocotb.gpi ..mbed/gpi_embed.cpp:74 in set_program_name_in_venv Did not detect Python virtual environment. Using system-wide Python interpreter
-.--ns INFO cocotb.gpi ../gpi/GpiCommon.cpp:105 in gpi_print_registered_impl VPI registered
-.--ns INFO cocotb.gpi ..mbed/gpi_embed.cpp:244 in embed_sim_init Python interpreter initialized and cocotb loaded!
0.00ns INFO cocotb __init__.py:202 in _initialise_testbench Running on Icarus Verilog version 11.0 (stable)
0.00ns INFO cocotb __init__.py:209 in _initialise_testbench Running tests with cocotb v1.4.0 from /project/fun/openlane/caravel_fwpayload-main/packages/python/lib64/python3.6/site-packages/cocotb
0.00ns INFO cocotb __init__.py:229 in _initialise_testbench Seeding Python random module with 1607799195
0.00ns CRITICAL cocotb.regression regression.py:177 in _discover_tests Failed to import module fwpayload_tests.fullchip_gpio: No module named 'fwpayload_tests.fullchip_gpio'
0.00ns INFO cocotb.regression regression.py:178 in _discover_tests MODULE variable was "fwpayload_tests.fullchip_gpio"
0.00ns INFO cocotb.regression regression.py:179 in _discover_tests Traceback:
0.00ns INFO cocotb.regression regression.py:180 in _discover_tests Traceback (most recent call last):
File "/project/fun/openlane/caravel_fwpayload-main/packages/python/lib64/python3.6/site-packages/cocotb/regression.py", line 175, in _discover_tests
module = _my_import(module_name)
File "/project/fun/openlane/caravel_fwpayload-main/packages/python/lib64/python3.6/site-packages/cocotb/regression.py", line 69, in _my_import
mod = __import__(name)
ModuleNotFoundError: No module named 'fwpayload_tests.fullchip_gpio'
Traceback (most recent call last):
File "/project/fun/openlane/caravel_fwpayload-main/packages/python/lib64/python3.6/site-packages/cocotb/__init__.py", line 246, in _initialise_testbench
regression_manager = RegressionManager.from_discovery(dut)
File "/project/fun/openlane/caravel_fwpayload-main/packages/python/lib64/python3.6/site-packages/cocotb/regression.py", line 154, in from_discovery
return cls(dut, tests, hooks)
File "/project/fun/openlane/caravel_fwpayload-main/packages/python/lib64/python3.6/site-packages/cocotb/regression.py", line 126, in __init__
for test in tests:
File "/project/fun/openlane/caravel_fwpayload-main/packages/python/lib64/python3.6/site-packages/cocotb/regression.py", line 175, in _discover_tests
module = _my_import(module_name)
File "/project/fun/openlane/caravel_fwpayload-main/packages/python/lib64/python3.6/site-packages/cocotb/regression.py", line 69, in _my_import
mod = __import__(name)
ModuleNotFoundError: No module named 'fwpayload_tests.fullchip_gpio'
0.00ns ERROR cocotb.gpi gpi_embed.cpp:314 in embed_sim_init cocotb initialization failed - exiting
0.00ns ERROR cocotb.scheduler __init__.py:269 in _sim_event Failing test at simulator request before test run completion: Simulator shutdown prematurely