| ############################################### |
| Emulate Docker CLI using podman. Create /etc/containers/nodocker to quiet msg. |
| [36m[INFO]:
|
| ___ ____ ___ ____ _ ____ ____ ___
|
| / \ | \ / _]| \ | | / || \ / _]
|
| | || o ) [_ | _ || | | o || _ | / [_
|
| | O || _/ _]| | || |___ | || | || _]
|
| | || | | [_ | | || || _ || | || [_
|
| \___/ |__| |_____||__|__||_____||__|__||__|__||_____|
|
|
|
| [37m
|
| [36m[INFO]: Version: mpw-one-a[37m
|
| [36m[INFO]: Running non-interactively[37m
|
| [36m[INFO]: Using design configuration at /project/openlane/user_proj_example/config.tcl[37m
|
| [36m[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl[37m
|
| [36m[INFO]: PDKs root directory: /project/fun/openlane/pdk_root-mpw-one-a[37m
|
| [36m[INFO]: PDK: sky130A[37m
|
| [36m[INFO]: Setting PDKPATH to /project/fun/openlane/pdk_root-mpw-one-a/sky130A[37m
|
| [36m[INFO]: Standard Cell Library: sky130_fd_sc_hd[37m
|
| [36m[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl[37m
|
| [36m[INFO]: Current run directory is /project/openlane/user_proj_example/runs/user_proj_example[37m
|
| [33m[WARNING]: Removing exisiting run /project/openlane/user_proj_example/runs/user_proj_example[37m
|
| [36m[INFO]: Preparing LEF Files[37m
|
| mergeLef.py : Merging LEFs
|
| sky130_ef_sc_hd__fakediode_2.lef: SITEs matched found: 0
|
| sky130_ef_sc_hd__fakediode_2.lef: MACROs matched found: 1
|
| sky130_fd_sc_hd.lef: SITEs matched found: 0
|
| sky130_fd_sc_hd.lef: MACROs matched found: 437
|
| mergeLef.py : Merging LEFs complete
|
| [36m[INFO]: Trimming Liberty...[37m
|
| [36m[INFO]: Preparation complete[37m
|
| [36m[INFO]: Running Synthesis...[37m
|
|
|
| /----------------------------------------------------------------------------\
|
| | |
|
| | yosys -- Yosys Open SYnthesis Suite |
|
| | |
|
| | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
|
| | |
|
| | Permission to use, copy, modify, and/or distribute this software for any |
|
| | purpose with or without fee is hereby granted, provided that the above |
|
| | copyright notice and this permission notice appear in all copies. |
|
| | |
|
| | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
|
| | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
|
| | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
|
| | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
|
| | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
|
| | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
|
| | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
|
| | |
|
| \----------------------------------------------------------------------------/
|
|
|
| Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
|
|
|
| [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
|
| [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
|
| [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
|
| [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
|
| [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
|
|
|
| 1. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/defines.v
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/defines.v' to AST representation.
|
| Successfully finished Verilog frontend.
|
|
|
| 2. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/user_proj_example.v
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/user_proj_example.v' to AST representation.
|
| Generating RTLIL representation for module `\user_proj_example'.
|
| /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/user_proj_example.v:102: Warning: Identifier `\payload_clock' is implicitly declared.
|
| /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/user_proj_example.v:103: Warning: Identifier `\payload_sys_reset' is implicitly declared.
|
| /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/user_proj_example.v:104: Warning: Identifier `\payload_core_reset' is implicitly declared.
|
| Successfully finished Verilog frontend.
|
|
|
| 3. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v' to AST representation.
|
| Generating RTLIL representation for module `\fwpayload'.
|
| /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v:193: Warning: Identifier `\u_core.u_core.u_core.pc' is implicitly declared.
|
| /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v:194: Warning: Identifier `\u_core.u_core.u_core.instr_complete' is implicitly declared.
|
| Successfully finished Verilog frontend.
|
|
|
| 4. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v' to AST representation.
|
| Generating RTLIL representation for module `\wb_clockdomain_bridge'.
|
| Warning: Replacing memory \req with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:65
|
| Warning: Replacing memory \ack with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:62
|
| Warning: Replacing memory \we with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:60
|
| Warning: Replacing memory \sel with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:59
|
| Warning: Replacing memory \dat_w with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:57
|
| Warning: Replacing memory \adr with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:56
|
| Warning: Replacing memory \dat_r with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:50
|
| Successfully finished Verilog frontend.
|
|
|
| 5. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v' to AST representation.
|
| Generating RTLIL representation for module `\wb_interconnect_NxN'.
|
| Warning: Replacing memory \initiator_active_target with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:134
|
| Warning: Replacing memory \target_active_initiator with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:115
|
| Successfully finished Verilog frontend.
|
|
|
| 6. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_arb.v
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_arb.v' to AST representation.
|
| Generating RTLIL representation for module `\wb_interconnect_arb'.
|
| Successfully finished Verilog frontend.
|
|
|
| 7. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram_32x256.sv
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram_32x256.sv' to AST representation.
|
| Generating RTLIL representation for module `\spram_32x256'.
|
| Successfully finished Verilog frontend.
|
|
|
| 8. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram_32x512.sv
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram_32x512.sv' to AST representation.
|
| Generating RTLIL representation for module `\spram_32x512'.
|
| Successfully finished Verilog frontend.
|
|
|
| 9. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v' to AST representation.
|
| Generating RTLIL representation for module `\spram_byte_en'.
|
| Successfully finished Verilog frontend.
|
|
|
| 10. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v' to AST representation.
|
| Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:183)
|
| Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:184)
|
| Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:189)
|
| Generating RTLIL representation for module `\simple_spi_master_wb'.
|
| Generating RTLIL representation for module `\simple_spi_master'.
|
| /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:187: Warning: Identifier `\sdoenb' is implicitly declared.
|
| Successfully finished Verilog frontend.
|
|
|
| 11. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v' to AST representation.
|
| Generating RTLIL representation for module `\simpleuart_wb'.
|
| Generating RTLIL representation for module `\simpleuart'.
|
| /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:130: Warning: Identifier `\reg_ena_do' is implicitly declared.
|
| Successfully finished Verilog frontend.
|
|
|
| 12. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv' to AST representation.
|
| Generating RTLIL representation for module `\fwrisc'.
|
| Successfully finished Verilog frontend.
|
|
|
| 13. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_wb.sv
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_wb.sv' to AST representation.
|
| Generating RTLIL representation for module `\fwrisc_wb'.
|
| Successfully finished Verilog frontend.
|
|
|
| 14. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_alu.sv
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_alu.sv' to AST representation.
|
| Generating RTLIL representation for module `\fwrisc_alu'.
|
| Successfully finished Verilog frontend.
|
|
|
| 15. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_c_decode.sv
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_c_decode.sv' to AST representation.
|
| Generating RTLIL representation for module `\fwrisc_c_decode'.
|
| Successfully finished Verilog frontend.
|
|
|
| 16. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv' to AST representation.
|
| Generating RTLIL representation for module `\fwrisc_decode'.
|
| Successfully finished Verilog frontend.
|
|
|
| 17. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv' to AST representation.
|
| Generating RTLIL representation for module `\fwrisc_exec'.
|
| Successfully finished Verilog frontend.
|
|
|
| 18. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_fetch.sv
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_fetch.sv' to AST representation.
|
| Generating RTLIL representation for module `\fwrisc_fetch'.
|
| Successfully finished Verilog frontend.
|
|
|
| 19. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mem.sv
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mem.sv' to AST representation.
|
| Generating RTLIL representation for module `\fwrisc_mem'.
|
| Successfully finished Verilog frontend.
|
|
|
| 20. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mul_div_shift.sv
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mul_div_shift.sv' to AST representation.
|
| Generating RTLIL representation for module `\fwrisc_mul_div_shift'.
|
| Successfully finished Verilog frontend.
|
|
|
| 21. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv' to AST representation.
|
| Generating RTLIL representation for module `\fwrisc_regfile'.
|
| /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:0: Warning: System task `$display' outside initial block is unsupported.
|
| Successfully finished Verilog frontend.
|
|
|
| 22. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_rv32i.sv
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_rv32i.sv' to AST representation.
|
| Generating RTLIL representation for module `\fwrisc_rv32i'.
|
| Successfully finished Verilog frontend.
|
|
|
| 23. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_rv32i_wb.sv
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_rv32i_wb.sv' to AST representation.
|
| Generating RTLIL representation for module `\fwrisc_rv32i_wb'.
|
| Successfully finished Verilog frontend.
|
|
|
| 24. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_tracer.sv
|
| Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_tracer.sv' to AST representation.
|
| Generating RTLIL representation for module `\fwrisc_tracer'.
|
| Successfully finished Verilog frontend.
|
|
|
| 25. Generating Graphviz representation of design.
|
| Writing dot description to `/project/openlane/user_proj_example/runs/user_proj_example/tmp/synthesis/hierarchy.dot'.
|
| Dumping module user_proj_example to page 1.
|
|
|
| 26. Executing HIERARCHY pass (managing design hierarchy).
|
|
|
| 26.1. Analyzing design hierarchy..
|
| Top module: \user_proj_example
|
| Used module: \fwpayload
|
| Used module: \simple_spi_master_wb
|
| Used module: \simple_spi_master
|
| Used module: \simpleuart_wb
|
| Used module: \simpleuart
|
| Used module: \spram_32x256
|
| Used module: \spram_byte_en
|
| Used module: \fwrisc_rv32i_wb
|
| Used module: \fwrisc_wb
|
| Used module: \fwrisc
|
| Used module: \fwrisc_regfile
|
| Used module: \fwrisc_exec
|
| Used module: \fwrisc_mem
|
| Used module: \fwrisc_mul_div_shift
|
| Used module: \fwrisc_alu
|
| Used module: \fwrisc_decode
|
| Used module: \fwrisc_c_decode
|
| Used module: \fwrisc_fetch
|
| Used module: \wb_interconnect_NxN
|
| Used module: \wb_interconnect_arb
|
| Used module: \wb_clockdomain_bridge
|
| Parameter \ADR_WIDTH = 32
|
| Parameter \DAT_WIDTH = 32
|
|
|
| 26.2. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_clockdomain_bridge'.
|
| Parameter \ADR_WIDTH = 32
|
| Parameter \DAT_WIDTH = 32
|
| Generating RTLIL representation for module `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32'.
|
| Warning: Replacing memory \req with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:65
|
| Warning: Replacing memory \ack with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:62
|
| Warning: Replacing memory \we with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:60
|
| Warning: Replacing memory \sel with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:59
|
| Warning: Replacing memory \dat_w with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:57
|
| Warning: Replacing memory \adr with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:56
|
| Warning: Replacing memory \dat_r with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:50
|
| Parameter \BASE_ADR = 0
|
|
|
| 26.3. Executing AST frontend in derive mode using pre-parsed AST for module `\simple_spi_master_wb'.
|
| Parameter \BASE_ADR = 0
|
| Generating RTLIL representation for module `$paramod\simple_spi_master_wb\BASE_ADR=0'.
|
| Parameter \BASE_ADR = 0
|
|
|
| 26.4. Executing AST frontend in derive mode using pre-parsed AST for module `\simpleuart_wb'.
|
| Parameter \BASE_ADR = 0
|
| Generating RTLIL representation for module `$paramod\simpleuart_wb\BASE_ADR=0'.
|
| Parameter \WB_ADDR_WIDTH = 32
|
| Parameter \WB_DATA_WIDTH = 32
|
| Parameter \N_INITIATORS = 4
|
| Parameter \N_TARGETS = 4
|
| Parameter \I_ADR_MASK = 128'00001111000000000000000000000000000011111111111111111111000000000000111111111111111111110000000000001111111111111111111100000000
|
| Parameter \T_ADR = 128'00000000000000000000000000000000000000010000000000000000000000000000000100000000000000010000000000000001000000000000001000000000
|
|
|
| 26.5. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_interconnect_NxN'.
|
| Parameter \WB_ADDR_WIDTH = 32
|
| Parameter \WB_DATA_WIDTH = 32
|
| Parameter \N_INITIATORS = 4
|
| Parameter \N_TARGETS = 4
|
| Parameter \I_ADR_MASK = 128'00001111000000000000000000000000000011111111111111111111000000000000111111111111111111110000000000001111111111111111111100000000
|
| Parameter \T_ADR = 128'00000000000000000000000000000000000000010000000000000000000000000000000100000000000000010000000000000001000000000000001000000000
|
| Generating RTLIL representation for module `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN'.
|
| Warning: Replacing memory \initiator_active_target with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:134
|
| Warning: Replacing memory \target_active_initiator with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:115
|
| Parameter \N_REQ = 1
|
|
|
| 26.6. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_interconnect_arb'.
|
| Parameter \N_REQ = 1
|
| Generating RTLIL representation for module `$paramod\wb_interconnect_arb\N_REQ=1'.
|
| Parameter \ENABLE_COMPRESSED = 0
|
| Parameter \ENABLE_MUL_DIV = 0
|
| Parameter \ENABLE_DEP = 0
|
| Parameter \ENABLE_COUNTERS = 1
|
|
|
| 26.7. Executing AST frontend in derive mode using pre-parsed AST for module `\fwrisc_wb'.
|
| Parameter \ENABLE_COMPRESSED = 0
|
| Parameter \ENABLE_MUL_DIV = 0
|
| Parameter \ENABLE_DEP = 0
|
| Parameter \ENABLE_COUNTERS = 1
|
| Generating RTLIL representation for module `$paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc_wb'.
|
| Parameter \ADDR_BITS = 8
|
| Parameter \DATA_BITS = 32
|
|
|
| 26.8. Executing AST frontend in derive mode using pre-parsed AST for module `\spram_byte_en'.
|
| Parameter \ADDR_BITS = 8
|
| Parameter \DATA_BITS = 32
|
| Generating RTLIL representation for module `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32'.
|
| Parameter \ENABLE_COUNTERS = 1
|
| Parameter \ENABLE_DEP = 1
|
|
|
| 26.9. Executing AST frontend in derive mode using pre-parsed AST for module `\fwrisc_regfile'.
|
| Parameter \ENABLE_COUNTERS = 1
|
| Parameter \ENABLE_DEP = 1
|
| Generating RTLIL representation for module `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=1'.
|
| /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:0: Warning: System task `$display' outside initial block is unsupported.
|
| Parameter \ENABLE_COMPRESSED = 1
|
| Parameter \ENABLE_MUL_DIV = 1
|
|
|
| 26.10. Executing AST frontend in derive mode using pre-parsed AST for module `\fwrisc_exec'.
|
| Parameter \ENABLE_COMPRESSED = 1
|
| Parameter \ENABLE_MUL_DIV = 1
|
| Generating RTLIL representation for module `$paramod\fwrisc_exec\ENABLE_COMPRESSED=1\ENABLE_MUL_DIV=1'.
|
| Parameter \ENABLE_COMPRESSED = 1
|
|
|
| 26.11. Executing AST frontend in derive mode using pre-parsed AST for module `\fwrisc_decode'.
|
| Parameter \ENABLE_COMPRESSED = 1
|
| Generating RTLIL representation for module `$paramod\fwrisc_decode\ENABLE_COMPRESSED=1'.
|
| Parameter \ENABLE_COMPRESSED = 1
|
|
|
| 26.12. Executing AST frontend in derive mode using pre-parsed AST for module `\fwrisc_fetch'.
|
| Parameter \ENABLE_COMPRESSED = 1
|
| Generating RTLIL representation for module `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=1'.
|
| Parameter \ENABLE_MUL_DIV = 1
|
|
|
| 26.13. Executing AST frontend in derive mode using pre-parsed AST for module `\fwrisc_mul_div_shift'.
|
| Parameter \ENABLE_MUL_DIV = 1
|
| Generating RTLIL representation for module `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=1'.
|
| Parameter \ENABLE_COMPRESSED = 1
|
| Parameter \ENABLE_MUL_DIV = 1
|
| Parameter \ENABLE_DEP = 1
|
| Parameter \ENABLE_COUNTERS = 1
|
|
|
| 26.14. Executing AST frontend in derive mode using pre-parsed AST for module `\fwrisc'.
|
| Parameter \ENABLE_COMPRESSED = 1
|
| Parameter \ENABLE_MUL_DIV = 1
|
| Parameter \ENABLE_DEP = 1
|
| Parameter \ENABLE_COUNTERS = 1
|
| Generating RTLIL representation for module `$paramod$4502d8ee4b89a225ea58ad7cb95984ff1b54011d\fwrisc'.
|
|
|
| 26.15. Analyzing design hierarchy..
|
| Top module: \user_proj_example
|
| Used module: \fwpayload
|
| Used module: $paramod\simple_spi_master_wb\BASE_ADR=0
|
| Used module: \simple_spi_master
|
| Used module: $paramod\simpleuart_wb\BASE_ADR=0
|
| Used module: \simpleuart
|
| Used module: \spram_32x256
|
| Used module: $paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32
|
| Used module: \fwrisc_rv32i_wb
|
| Used module: $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc_wb
|
| Used module: \fwrisc
|
| Used module: $paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=1
|
| Used module: $paramod\fwrisc_exec\ENABLE_COMPRESSED=1\ENABLE_MUL_DIV=1
|
| Used module: \fwrisc_mem
|
| Used module: \fwrisc_mul_div_shift
|
| Used module: \fwrisc_alu
|
| Used module: $paramod\fwrisc_decode\ENABLE_COMPRESSED=1
|
| Used module: \fwrisc_c_decode
|
| Used module: $paramod\fwrisc_fetch\ENABLE_COMPRESSED=1
|
| Used module: $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN
|
| Used module: \wb_interconnect_arb
|
| Used module: $paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32
|
| Parameter \N_REQ = 4
|
|
|
| 26.16. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_interconnect_arb'.
|
| Parameter \N_REQ = 4
|
| Generating RTLIL representation for module `$paramod\wb_interconnect_arb\N_REQ=4'.
|
| Parameter \N_REQ = 4
|
| Found cached RTLIL representation for module `$paramod\wb_interconnect_arb\N_REQ=4'.
|
| Parameter \N_REQ = 4
|
| Found cached RTLIL representation for module `$paramod\wb_interconnect_arb\N_REQ=4'.
|
| Parameter \N_REQ = 4
|
| Found cached RTLIL representation for module `$paramod\wb_interconnect_arb\N_REQ=4'.
|
| Parameter \ENABLE_COMPRESSED = 0
|
| Parameter \ENABLE_MUL_DIV = 0
|
| Parameter \ENABLE_DEP = 0
|
| Parameter \ENABLE_COUNTERS = 1
|
|
|
| 26.17. Executing AST frontend in derive mode using pre-parsed AST for module `\fwrisc'.
|
| Parameter \ENABLE_COMPRESSED = 0
|
| Parameter \ENABLE_MUL_DIV = 0
|
| Parameter \ENABLE_DEP = 0
|
| Parameter \ENABLE_COUNTERS = 1
|
| Generating RTLIL representation for module `$paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc'.
|
| Parameter \ENABLE_MUL_DIV = 1
|
| Found cached RTLIL representation for module `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=1'.
|
|
|
| 26.18. Analyzing design hierarchy..
|
| Top module: \user_proj_example
|
| Used module: \fwpayload
|
| Used module: $paramod\simple_spi_master_wb\BASE_ADR=0
|
| Used module: \simple_spi_master
|
| Used module: $paramod\simpleuart_wb\BASE_ADR=0
|
| Used module: \simpleuart
|
| Used module: \spram_32x256
|
| Used module: $paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32
|
| Used module: \fwrisc_rv32i_wb
|
| Used module: $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc_wb
|
| Used module: $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc
|
| Used module: \fwrisc_regfile
|
| Used module: \fwrisc_exec
|
| Used module: \fwrisc_mem
|
| Used module: $paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=1
|
| Used module: \fwrisc_alu
|
| Used module: \fwrisc_decode
|
| Used module: \fwrisc_c_decode
|
| Used module: \fwrisc_fetch
|
| Used module: $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN
|
| Used module: $paramod\wb_interconnect_arb\N_REQ=4
|
| Used module: $paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32
|
| Parameter \ENABLE_COUNTERS = 1
|
| Parameter \ENABLE_DEP = 0
|
|
|
| 26.19. Executing AST frontend in derive mode using pre-parsed AST for module `\fwrisc_regfile'.
|
| Parameter \ENABLE_COUNTERS = 1
|
| Parameter \ENABLE_DEP = 0
|
| Generating RTLIL representation for module `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0'.
|
| /project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:0: Warning: System task `$display' outside initial block is unsupported.
|
| Parameter \ENABLE_COMPRESSED = 0
|
| Parameter \ENABLE_MUL_DIV = 0
|
|
|
| 26.20. Executing AST frontend in derive mode using pre-parsed AST for module `\fwrisc_exec'.
|
| Parameter \ENABLE_COMPRESSED = 0
|
| Parameter \ENABLE_MUL_DIV = 0
|
| Generating RTLIL representation for module `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0'.
|
| Parameter \ENABLE_COMPRESSED = 0
|
|
|
| 26.21. Executing AST frontend in derive mode using pre-parsed AST for module `\fwrisc_decode'.
|
| Parameter \ENABLE_COMPRESSED = 0
|
| Generating RTLIL representation for module `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0'.
|
| Parameter \ENABLE_COMPRESSED = 0
|
|
|
| 26.22. Executing AST frontend in derive mode using pre-parsed AST for module `\fwrisc_fetch'.
|
| Parameter \ENABLE_COMPRESSED = 0
|
| Generating RTLIL representation for module `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0'.
|
|
|
| 26.23. Analyzing design hierarchy..
|
| Top module: \user_proj_example
|
| Used module: \fwpayload
|
| Used module: $paramod\simple_spi_master_wb\BASE_ADR=0
|
| Used module: \simple_spi_master
|
| Used module: $paramod\simpleuart_wb\BASE_ADR=0
|
| Used module: \simpleuart
|
| Used module: \spram_32x256
|
| Used module: $paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32
|
| Used module: \fwrisc_rv32i_wb
|
| Used module: $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc_wb
|
| Used module: $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc
|
| Used module: $paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0
|
| Used module: $paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0
|
| Used module: \fwrisc_mem
|
| Used module: \fwrisc_mul_div_shift
|
| Used module: \fwrisc_alu
|
| Used module: $paramod\fwrisc_decode\ENABLE_COMPRESSED=0
|
| Used module: $paramod\fwrisc_fetch\ENABLE_COMPRESSED=0
|
| Used module: $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN
|
| Used module: $paramod\wb_interconnect_arb\N_REQ=4
|
| Used module: $paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32
|
| Parameter \ENABLE_MUL_DIV = 0
|
|
|
| 26.24. Executing AST frontend in derive mode using pre-parsed AST for module `\fwrisc_mul_div_shift'.
|
| Parameter \ENABLE_MUL_DIV = 0
|
| Generating RTLIL representation for module `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0'.
|
|
|
| 26.25. Analyzing design hierarchy..
|
| Top module: \user_proj_example
|
| Used module: \fwpayload
|
| Used module: $paramod\simple_spi_master_wb\BASE_ADR=0
|
| Used module: \simple_spi_master
|
| Used module: $paramod\simpleuart_wb\BASE_ADR=0
|
| Used module: \simpleuart
|
| Used module: \spram_32x256
|
| Used module: $paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32
|
| Used module: \fwrisc_rv32i_wb
|
| Used module: $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc_wb
|
| Used module: $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc
|
| Used module: $paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0
|
| Used module: $paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0
|
| Used module: \fwrisc_mem
|
| Used module: $paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0
|
| Used module: \fwrisc_alu
|
| Used module: $paramod\fwrisc_decode\ENABLE_COMPRESSED=0
|
| Used module: $paramod\fwrisc_fetch\ENABLE_COMPRESSED=0
|
| Used module: $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN
|
| Used module: $paramod\wb_interconnect_arb\N_REQ=4
|
| Used module: $paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32
|
|
|
| 26.26. Analyzing design hierarchy..
|
| Top module: \user_proj_example
|
| Used module: \fwpayload
|
| Used module: $paramod\simple_spi_master_wb\BASE_ADR=0
|
| Used module: \simple_spi_master
|
| Used module: $paramod\simpleuart_wb\BASE_ADR=0
|
| Used module: \simpleuart
|
| Used module: \spram_32x256
|
| Used module: $paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32
|
| Used module: \fwrisc_rv32i_wb
|
| Used module: $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc_wb
|
| Used module: $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc
|
| Used module: $paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0
|
| Used module: $paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0
|
| Used module: \fwrisc_mem
|
| Used module: $paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0
|
| Used module: \fwrisc_alu
|
| Used module: $paramod\fwrisc_decode\ENABLE_COMPRESSED=0
|
| Used module: $paramod\fwrisc_fetch\ENABLE_COMPRESSED=0
|
| Used module: $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN
|
| Used module: $paramod\wb_interconnect_arb\N_REQ=4
|
| Used module: $paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32
|
| Removing unused module `$paramod$4502d8ee4b89a225ea58ad7cb95984ff1b54011d\fwrisc'.
|
| Removing unused module `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=1'.
|
| Removing unused module `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=1'.
|
| Removing unused module `$paramod\fwrisc_decode\ENABLE_COMPRESSED=1'.
|
| Removing unused module `$paramod\fwrisc_exec\ENABLE_COMPRESSED=1\ENABLE_MUL_DIV=1'.
|
| Removing unused module `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=1'.
|
| Removing unused module `$paramod\wb_interconnect_arb\N_REQ=1'.
|
| Removing unused module `\fwrisc_rv32i'.
|
| Removing unused module `\fwrisc_regfile'.
|
| Removing unused module `\fwrisc_mul_div_shift'.
|
| Removing unused module `\fwrisc_fetch'.
|
| Removing unused module `\fwrisc_exec'.
|
| Removing unused module `\fwrisc_decode'.
|
| Removing unused module `\fwrisc_c_decode'.
|
| Removing unused module `\fwrisc_wb'.
|
| Removing unused module `\fwrisc'.
|
| Removing unused module `\simpleuart_wb'.
|
| Removing unused module `\simple_spi_master_wb'.
|
| Removing unused module `\spram_byte_en'.
|
| Removing unused module `\spram_32x512'.
|
| Removing unused module `\wb_interconnect_arb'.
|
| Removing unused module `\wb_interconnect_NxN'.
|
| Removing unused module `\wb_clockdomain_bridge'.
|
| Removed 23 unused modules.
|
| Warning: Resizing cell port $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.u_tracer.rb_raddr from 32 bits to 6 bits.
|
| Warning: Resizing cell port $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.u_tracer.ra_raddr from 32 bits to 6 bits.
|
| Warning: Resizing cell port $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.u_regfile.rb_raddr from 32 bits to 6 bits.
|
| Warning: Resizing cell port $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.u_regfile.ra_raddr from 32 bits to 6 bits.
|
| Warning: Resizing cell port $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.u_exec.pc_seq from 32 bits to 1 bits.
|
| Warning: Resizing cell port $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.u_exec.op from 4 bits to 6 bits.
|
| Warning: Resizing cell port $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.u_decode.rb_raddr from 32 bits to 6 bits.
|
| Warning: Resizing cell port $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.u_decode.ra_raddr from 32 bits to 6 bits.
|
| Warning: Resizing cell port $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.u_fetch.next_pc_seq from 32 bits to 1 bits.
|
| Warning: Resizing cell port fwpayload.u_sram.a_adr from 32 bits to 8 bits.
|
| Warning: Resizing cell port user_proj_example.u_payload.wba_adr_i from 32 bits to 16 bits.
|
|
|
| 27. Executing TRIBUF pass.
|
|
|
| 28. Executing SYNTH pass.
|
|
|
| 28.1. Executing HIERARCHY pass (managing design hierarchy).
|
|
|
| 28.1.1. Analyzing design hierarchy..
|
| Top module: \user_proj_example
|
| Used module: \fwpayload
|
| Used module: $paramod\simple_spi_master_wb\BASE_ADR=0
|
| Used module: \simple_spi_master
|
| Used module: $paramod\simpleuart_wb\BASE_ADR=0
|
| Used module: \simpleuart
|
| Used module: \spram_32x256
|
| Used module: $paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32
|
| Used module: \fwrisc_rv32i_wb
|
| Used module: $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc_wb
|
| Used module: $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc
|
| Used module: $paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0
|
| Used module: $paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0
|
| Used module: \fwrisc_mem
|
| Used module: $paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0
|
| Used module: \fwrisc_alu
|
| Used module: $paramod\fwrisc_decode\ENABLE_COMPRESSED=0
|
| Used module: $paramod\fwrisc_fetch\ENABLE_COMPRESSED=0
|
| Used module: $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN
|
| Used module: $paramod\wb_interconnect_arb\N_REQ=4
|
| Used module: $paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32
|
|
|
| 28.1.2. Analyzing design hierarchy..
|
| Top module: \user_proj_example
|
| Used module: \fwpayload
|
| Used module: $paramod\simple_spi_master_wb\BASE_ADR=0
|
| Used module: \simple_spi_master
|
| Used module: $paramod\simpleuart_wb\BASE_ADR=0
|
| Used module: \simpleuart
|
| Used module: \spram_32x256
|
| Used module: $paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32
|
| Used module: \fwrisc_rv32i_wb
|
| Used module: $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc_wb
|
| Used module: $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc
|
| Used module: $paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0
|
| Used module: $paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0
|
| Used module: \fwrisc_mem
|
| Used module: $paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0
|
| Used module: \fwrisc_alu
|
| Used module: $paramod\fwrisc_decode\ENABLE_COMPRESSED=0
|
| Used module: $paramod\fwrisc_fetch\ENABLE_COMPRESSED=0
|
| Used module: $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN
|
| Used module: $paramod\wb_interconnect_arb\N_REQ=4
|
| Used module: $paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32
|
| Removed 0 unused modules.
|
|
|
| 28.2. Executing PROC pass (convert processes to netlists).
|
|
|
| 28.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
| Found and cleaned up 1 empty switch in `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:351$2259'.
|
| Found and cleaned up 1 empty switch in `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:125$2032'.
|
| Found and cleaned up 6 empty switches in `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mul_div_shift.sv:59$2274'.
|
| Cleaned up 8 empty switches.
|
|
|
| 28.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
|
| Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_fetch.sv:74$2269 in module $paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.
|
| Marked 3 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:351$2259 in module $paramod\fwrisc_decode\ENABLE_COMPRESSED=0.
|
| Removed 1 dead cases from process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:131$2231 in module $paramod\fwrisc_decode\ENABLE_COMPRESSED=0.
|
| Marked 26 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:131$2231 in module $paramod\fwrisc_decode\ENABLE_COMPRESSED=0.
|
| Marked 10 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mem.sv:60$490 in module fwrisc_mem.
|
| Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:422$2205 in module $paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.
|
| Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:393$2169 in module $paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.
|
| Marked 9 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:199$2133 in module $paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.
|
| Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:188$2129 in module $paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.
|
| Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:166$2120 in module $paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.
|
| Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:153$2117 in module $paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.
|
| Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:140$2112 in module $paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.
|
| Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:125$2032 in module $paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.
|
| Marked 3 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954 in module $paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.
|
| Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:130$1820 in module $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.
|
| Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:66$1817 in module $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.
|
| Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_alu.sv:37$307 in module fwrisc_alu.
|
| Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_arb.v:106$1781 in module $paramod\wb_interconnect_arb\N_REQ=4.
|
| Marked 3 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:191$288 in module simpleuart.
|
| Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:148$278 in module simpleuart.
|
| Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:135$276 in module simpleuart.
|
| Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1177 in module $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.
|
| Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1163 in module $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.
|
| Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1149 in module $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.
|
| Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1135 in module $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.
|
| Marked 8 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1118 in module $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.
|
| Marked 8 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1101 in module $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.
|
| Marked 8 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1084 in module $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.
|
| Marked 8 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1067 in module $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.
|
| Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1062 in module $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.
|
| Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1057 in module $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.
|
| Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1052 in module $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.
|
| Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1047 in module $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.
|
| Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1042 in module $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.
|
| Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1037 in module $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.
|
| Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1032 in module $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.
|
| Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1027 in module $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.
|
| Marked 5 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:344$235 in module simple_spi_master.
|
| Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:331$229 in module simple_spi_master.
|
| Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:312$223 in module simple_spi_master.
|
| Marked 6 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:276$212 in module simple_spi_master.
|
| Marked 6 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:232$195 in module simple_spi_master.
|
| Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:201$193 in module simple_spi_master.
|
| Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:100$827 in module $paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.
|
| Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:47$817 in module $paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.
|
| Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mul_div_shift.sv:59$2274 in module $paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0.
|
| Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v:321$49 in module fwpayload.
|
| Removed 1 dead cases from process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v:219$45 in module fwpayload.
|
| Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v:219$45 in module fwpayload.
|
| Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/user_proj_example.v:89$6 in module user_proj_example.
|
| Removed a total of 2 dead cases.
|
|
|
| 28.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
|
| Removed 16 redundant assignments.
|
| Promoted 151 assignments to connections.
|
|
|
| 28.2.4. Executing PROC_INIT pass (extract init attributes).
|
| Found init rule in `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:111$2226'.
|
| Set init value: \mtval = 0
|
| Found init rule in `$paramod\wb_interconnect_arb\N_REQ=4.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_arb.v:23$1814'.
|
| Set init value: \last_gnt = 4'0000
|
| Found init rule in `\fwpayload.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v:206$54'.
|
| Set init value: \wb_bridge_state = 2'00
|
|
|
| 28.2.5. Executing PROC_ARST pass (detect async resets in processes).
|
| Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:344$235'.
|
| Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:331$229'.
|
| Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:312$223'.
|
| Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:276$212'.
|
| Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:232$195'.
|
| Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:201$193'.
|
|
|
| 28.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
|
| Creating decoders for process `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_fetch.sv:74$2269'.
|
| 1/9: $0\instr[31:0] [31:16]
|
| 2/9: $0\instr[31:0] [15:0]
|
| 3/9: $0\fetch_valid_r[0:0]
|
| 4/9: $0\instr_cache_valid[0:0]
|
| 5/9: $0\instr_cache[15:0]
|
| 6/9: $0\instr_c[0:0]
|
| 7/9: $0\ivalid_r[0:0]
|
| 8/9: $0\iaddr[31:0]
|
| 9/9: $0\state[2:0]
|
| Creating decoders for process `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:351$2259'.
|
| 1/5: $0\decode_state[1:0]
|
| 2/5: $0\decode_valid_r[0:0]
|
| 3/5: $0\imm_lui[31:0]
|
| 4/5: $0\op_type[4:0]
|
| 5/5: $0\rd_raddr[5:0]
|
| Creating decoders for process `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:131$2231'.
|
| 1/26: $9\op_w[3:0]
|
| 2/26: $8\op_w[3:0]
|
| 3/26: $7\op_w[3:0]
|
| 4/26: $6\op_w[3:0]
|
| 5/26: $5\op_w[3:0]
|
| 6/26: $4\op_w[3:0]
|
| 7/26: $3\op_w[3:0]
|
| 8/26: $2\op_w[3:0]
|
| 9/26: $1\op_w[3:0]
|
| 10/26: $1\op_c[31:0]
|
| 11/26: $3\op_b[31:0]
|
| 12/26: $2\op_b[31:0]
|
| 13/26: $1\op_b[31:0]
|
| 14/26: $2\op_a[31:0]
|
| 15/26: $1\op_a[31:0]
|
| 16/26: $3\rb_raddr[5:0]
|
| 17/26: $2\rb_raddr[5:0]
|
| 18/26: $1\rb_raddr[5:0]
|
| 19/26: $1\ra_raddr[5:0]
|
| 20/26: $5\op_type_w[4:0]
|
| 21/26: $4\op_type_w[4:0]
|
| 22/26: $3\op_type_w[4:0]
|
| 23/26: $2\op_type_w[4:0]
|
| 24/26: $1\op_type_w[4:0]
|
| 25/26: $2\i_type[2:0]
|
| 26/26: $1\i_type[2:0]
|
| Creating decoders for process `\fwrisc_mem.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mem.sv:60$490'.
|
| 1/8: $0\mem_state[1:0]
|
| 2/8: $0\ack_data[31:0]
|
| 3/8: $0\ack_valid[0:0]
|
| 4/8: $0\dwrite[0:0]
|
| 5/8: $0\dwstb[3:0]
|
| 6/8: $0\dwdata[31:0]
|
| 7/8: $0\daddr[31:0]
|
| 8/8: $0\dvalid[0:0]
|
| Creating decoders for process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:111$2226'.
|
| Creating decoders for process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:422$2205'.
|
| 1/2: $1\rd_waddr[5:0]
|
| 2/2: $1\rd_wdata[31:0]
|
| Creating decoders for process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:404$2170'.
|
| Creating decoders for process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:393$2169'.
|
| 1/1: $1\alu_op[3:0]
|
| Creating decoders for process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:199$2133'.
|
| 1/5: $0\mcause[3:0]
|
| 2/5: $0\exec_state[3:0]
|
| 3/5: $0\pc_seq[0:0]
|
| 4/5: $0\instr_complete[0:0]
|
| 5/5: $0\pc[31:0]
|
| Creating decoders for process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:188$2129'.
|
| 1/2: $1\pc_seq_next[0:0]
|
| 2/2: $1\pc_next[31:0]
|
| Creating decoders for process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:166$2120'.
|
| 1/1: $1\next_pc_seq_incr[2:0]
|
| Creating decoders for process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:153$2117'.
|
| 1/1: $0\mtval[31:0]
|
| Creating decoders for process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:140$2112'.
|
| 1/2: $2\ldst_addr_misaligned[0:0]
|
| 2/2: $1\ldst_addr_misaligned[0:0]
|
| Creating decoders for process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:125$2032'.
|
| 1/4: $0\rb_rdata[31:0]
|
| 2/4: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:129$1951_EN[31:0]$2035
|
| 3/4: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:129$1951_DATA[31:0]$2034
|
| 4/4: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:129$1951_ADDR[5:0]$2033
|
| Creating decoders for process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| 1/70: $1\reg_i[31:0]
|
| 2/70: $0\instr_count[63:0]
|
| 3/70: $0\cycle_count[63:0]
|
| 4/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955
|
| 5/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956
|
| 6/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957
|
| 7/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958
|
| 8/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959
|
| 9/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960
|
| 10/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961
|
| 11/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962
|
| 12/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963
|
| 13/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964
|
| 14/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965
|
| 15/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966
|
| 16/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967
|
| 17/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968
|
| 18/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969
|
| 19/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970
|
| 20/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971
|
| 21/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972
|
| 22/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973
|
| 23/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974
|
| 24/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975
|
| 25/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976
|
| 26/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977
|
| 27/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978
|
| 28/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979
|
| 29/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980
|
| 30/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981
|
| 31/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982
|
| 32/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983
|
| 33/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984
|
| 34/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985
|
| 35/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986
|
| 36/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987
|
| 37/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988
|
| 38/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989
|
| 39/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990
|
| 40/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991
|
| 41/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992
|
| 42/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993
|
| 43/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1926_EN[31:0]$1994
|
| 44/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1927_EN[31:0]$1995
|
| 45/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1928_EN[31:0]$1996
|
| 46/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1929_EN[31:0]$1997
|
| 47/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1930_EN[31:0]$1998
|
| 48/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1931_EN[31:0]$1999
|
| 49/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1932_EN[31:0]$2000
|
| 50/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1933_EN[31:0]$2001
|
| 51/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1934_EN[31:0]$2002
|
| 52/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1935_EN[31:0]$2003
|
| 53/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1936_EN[31:0]$2004
|
| 54/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1937_EN[31:0]$2005
|
| 55/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1938_EN[31:0]$2006
|
| 56/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1939_EN[31:0]$2007
|
| 57/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1940_EN[31:0]$2008
|
| 58/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1941_EN[31:0]$2009
|
| 59/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1942_EN[31:0]$2010
|
| 60/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1943_EN[31:0]$2011
|
| 61/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1944_EN[31:0]$2012
|
| 62/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1945_EN[31:0]$2013
|
| 63/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1946_EN[31:0]$2014
|
| 64/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1947_EN[31:0]$2015
|
| 65/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1948_EN[31:0]$2016
|
| 66/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1949_EN[31:0]$2017
|
| 67/70: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1950_EN[31:0]$2018
|
| 68/70: $0\mtvec_r[31:0]
|
| 69/70: $0\dep_hi_r[31:0]
|
| 70/70: $0\dep_lo_r[31:0]
|
| Creating decoders for process `$paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:130$1820'.
|
| 1/2: $0\tracer_instr[31:0]
|
| 2/2: $0\tracer_pc[31:0]
|
| Creating decoders for process `$paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:66$1817'.
|
| 1/1: $0\soft_reset_count[4:0]
|
| Creating decoders for process `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:19$1269'.
|
| 1/12: $0$memwr$\ram_0$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:21$1265_EN[7:0]$1272
|
| 2/12: $0$memwr$\ram_0$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:21$1265_DATA[7:0]$1271
|
| 3/12: $0$memwr$\ram_0$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:21$1265_ADDR[7:0]$1270
|
| 4/12: $0$memwr$\ram_1$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:22$1266_EN[7:0]$1275
|
| 5/12: $0$memwr$\ram_1$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:22$1266_DATA[7:0]$1274
|
| 6/12: $0$memwr$\ram_1$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:22$1266_ADDR[7:0]$1273
|
| 7/12: $0$memwr$\ram_2$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:23$1267_EN[7:0]$1278
|
| 8/12: $0$memwr$\ram_2$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:23$1267_DATA[7:0]$1277
|
| 9/12: $0$memwr$\ram_2$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:23$1267_ADDR[7:0]$1276
|
| 10/12: $0$memwr$\ram_3$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:24$1268_EN[7:0]$1281
|
| 11/12: $0$memwr$\ram_3$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:24$1268_DATA[7:0]$1280
|
| 12/12: $0$memwr$\ram_3$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:24$1268_ADDR[7:0]$1279
|
| Creating decoders for process `\fwrisc_alu.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_alu.sv:37$307'.
|
| 1/1: $1\out[31:0]
|
| Creating decoders for process `$paramod\wb_interconnect_arb\N_REQ=4.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_arb.v:23$1814'.
|
| Creating decoders for process `$paramod\wb_interconnect_arb\N_REQ=4.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_arb.v:106$1781'.
|
| 1/2: $0\last_gnt[3:0]
|
| 2/2: $0\state[0:0]
|
| Creating decoders for process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:191$288'.
|
| 1/4: $0\send_divcnt[31:0]
|
| 2/4: $0\send_dummy[0:0]
|
| 3/4: $0\send_bitcnt[3:0]
|
| 4/4: $0\send_pattern[9:0]
|
| Creating decoders for process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:148$278'.
|
| 1/5: $0\recv_divcnt[31:0]
|
| 2/5: $0\recv_buf_valid[0:0]
|
| 3/5: $0\recv_buf_data[7:0]
|
| 4/5: $0\recv_pattern[7:0]
|
| 5/5: $0\recv_state[3:0]
|
| Creating decoders for process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:135$276'.
|
| 1/5: $0\cfg_divider[31:0] [31:24]
|
| 2/5: $0\cfg_divider[31:0] [23:16]
|
| 3/5: $0\cfg_divider[31:0] [15:8]
|
| 4/5: $0\cfg_divider[31:0] [7:0]
|
| 5/5: $0\enabled[0:0]
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1191'.
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1177'.
|
| 1/12: $4\tsel[15:12]
|
| 2/12: $4\tdat_w[127:96]
|
| 3/12: $4\tadr[127:96]
|
| 4/12: $3\tsel[15:12]
|
| 5/12: $3\tdat_w[127:96]
|
| 6/12: $3\tadr[127:96]
|
| 7/12: $2\tsel[15:12]
|
| 8/12: $2\tdat_w[127:96]
|
| 9/12: $2\tadr[127:96]
|
| 10/12: $1\tsel[15:12]
|
| 11/12: $1\tdat_w[127:96]
|
| 12/12: $1\tadr[127:96]
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1163'.
|
| 1/12: $4\tsel[11:8]
|
| 2/12: $4\tdat_w[95:64]
|
| 3/12: $4\tadr[95:64]
|
| 4/12: $3\tsel[11:8]
|
| 5/12: $3\tdat_w[95:64]
|
| 6/12: $3\tadr[95:64]
|
| 7/12: $2\tsel[11:8]
|
| 8/12: $2\tdat_w[95:64]
|
| 9/12: $2\tadr[95:64]
|
| 10/12: $1\tsel[11:8]
|
| 11/12: $1\tdat_w[95:64]
|
| 12/12: $1\tadr[95:64]
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1149'.
|
| 1/12: $4\tsel[7:4]
|
| 2/12: $4\tdat_w[63:32]
|
| 3/12: $4\tadr[63:32]
|
| 4/12: $3\tsel[7:4]
|
| 5/12: $3\tdat_w[63:32]
|
| 6/12: $3\tadr[63:32]
|
| 7/12: $2\tsel[7:4]
|
| 8/12: $2\tdat_w[63:32]
|
| 9/12: $2\tadr[63:32]
|
| 10/12: $1\tsel[7:4]
|
| 11/12: $1\tdat_w[63:32]
|
| 12/12: $1\tadr[63:32]
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1135'.
|
| 1/12: $4\tsel[3:0]
|
| 2/12: $4\tdat_w[31:0]
|
| 3/12: $4\tadr[31:0]
|
| 4/12: $3\tsel[3:0]
|
| 5/12: $3\tdat_w[31:0]
|
| 6/12: $3\tadr[31:0]
|
| 7/12: $2\tsel[3:0]
|
| 8/12: $2\tdat_w[31:0]
|
| 9/12: $2\tadr[31:0]
|
| 10/12: $1\tsel[3:0]
|
| 11/12: $1\tdat_w[31:0]
|
| 12/12: $1\tadr[31:0]
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1118'.
|
| 1/12: $8\ack[3:3]
|
| 2/12: $7\ack[3:3]
|
| 3/12: $4\dat_r[127:96]
|
| 4/12: $6\ack[3:3]
|
| 5/12: $5\ack[3:3]
|
| 6/12: $3\dat_r[127:96]
|
| 7/12: $4\ack[3:3]
|
| 8/12: $3\ack[3:3]
|
| 9/12: $2\dat_r[127:96]
|
| 10/12: $2\ack[3:3]
|
| 11/12: $1\ack[3:3]
|
| 12/12: $1\dat_r[127:96]
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1101'.
|
| 1/12: $8\ack[2:2]
|
| 2/12: $7\ack[2:2]
|
| 3/12: $4\dat_r[95:64]
|
| 4/12: $6\ack[2:2]
|
| 5/12: $5\ack[2:2]
|
| 6/12: $3\dat_r[95:64]
|
| 7/12: $4\ack[2:2]
|
| 8/12: $3\ack[2:2]
|
| 9/12: $2\dat_r[95:64]
|
| 10/12: $2\ack[2:2]
|
| 11/12: $1\ack[2:2]
|
| 12/12: $1\dat_r[95:64]
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1084'.
|
| 1/12: $8\ack[1:1]
|
| 2/12: $7\ack[1:1]
|
| 3/12: $4\dat_r[63:32]
|
| 4/12: $6\ack[1:1]
|
| 5/12: $5\ack[1:1]
|
| 6/12: $3\dat_r[63:32]
|
| 7/12: $4\ack[1:1]
|
| 8/12: $3\ack[1:1]
|
| 9/12: $2\dat_r[63:32]
|
| 10/12: $2\ack[1:1]
|
| 11/12: $1\ack[1:1]
|
| 12/12: $1\dat_r[63:32]
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1067'.
|
| 1/12: $8\ack[0:0]
|
| 2/12: $7\ack[0:0]
|
| 3/12: $4\dat_r[31:0]
|
| 4/12: $6\ack[0:0]
|
| 5/12: $5\ack[0:0]
|
| 6/12: $3\dat_r[31:0]
|
| 7/12: $4\ack[0:0]
|
| 8/12: $3\ack[0:0]
|
| 9/12: $2\dat_r[31:0]
|
| 10/12: $2\ack[0:0]
|
| 11/12: $1\ack[0:0]
|
| 12/12: $1\dat_r[31:0]
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1062'.
|
| 1/4: $4\initiator_active_target[3][2:0]
|
| 2/4: $3\initiator_active_target[3][2:0]
|
| 3/4: $2\initiator_active_target[3][2:0]
|
| 4/4: $1\initiator_active_target[3][2:0]
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1057'.
|
| 1/4: $4\initiator_active_target[2][2:0]
|
| 2/4: $3\initiator_active_target[2][2:0]
|
| 3/4: $2\initiator_active_target[2][2:0]
|
| 4/4: $1\initiator_active_target[2][2:0]
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1052'.
|
| 1/4: $4\initiator_active_target[1][2:0]
|
| 2/4: $3\initiator_active_target[1][2:0]
|
| 3/4: $2\initiator_active_target[1][2:0]
|
| 4/4: $1\initiator_active_target[1][2:0]
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1047'.
|
| 1/4: $4\initiator_active_target[0][2:0]
|
| 2/4: $3\initiator_active_target[0][2:0]
|
| 3/4: $2\initiator_active_target[0][2:0]
|
| 4/4: $1\initiator_active_target[0][2:0]
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1042'.
|
| 1/4: $4\target_active_initiator[3][2:0]
|
| 2/4: $3\target_active_initiator[3][2:0]
|
| 3/4: $2\target_active_initiator[3][2:0]
|
| 4/4: $1\target_active_initiator[3][2:0]
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1037'.
|
| 1/4: $4\target_active_initiator[2][2:0]
|
| 2/4: $3\target_active_initiator[2][2:0]
|
| 3/4: $2\target_active_initiator[2][2:0]
|
| 4/4: $1\target_active_initiator[2][2:0]
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1032'.
|
| 1/4: $4\target_active_initiator[1][2:0]
|
| 2/4: $3\target_active_initiator[1][2:0]
|
| 3/4: $2\target_active_initiator[1][2:0]
|
| 4/4: $1\target_active_initiator[1][2:0]
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1027'.
|
| 1/4: $4\target_active_initiator[0][2:0]
|
| 2/4: $3\target_active_initiator[0][2:0]
|
| 3/4: $2\target_active_initiator[0][2:0]
|
| 4/4: $1\target_active_initiator[0][2:0]
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1025'.
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1023'.
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1021'.
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1019'.
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1017'.
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1015'.
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1013'.
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1011'.
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1009'.
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1007'.
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1005'.
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1003'.
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1001'.
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$999'.
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$997'.
|
| Creating decoders for process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$995'.
|
| Creating decoders for process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:344$235'.
|
| 1/3: $0\rreg[7:0]
|
| 2/3: $0\treg[7:0]
|
| 3/3: $0\isdo[0:0]
|
| Creating decoders for process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:331$229'.
|
| 1/1: $0\isck[0:0]
|
| Creating decoders for process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:312$223'.
|
| 1/2: $0\count[7:0]
|
| 2/2: $0\hsck[0:0]
|
| Creating decoders for process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:276$212'.
|
| 1/4: $0\nbit[2:0]
|
| 2/4: $0\icsb[0:0]
|
| 3/4: $0\done[0:0]
|
| 4/4: $0\state[1:0]
|
| Creating decoders for process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:232$195'.
|
| 1/4: $0\r_latched[0:0]
|
| 2/4: $0\w_latched[0:0]
|
| 3/4: $0\d_latched[7:0]
|
| 4/4: $0\err_out[0:0]
|
| Creating decoders for process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:201$193'.
|
| 1/9: $0\hkconn[0:0]
|
| 2/9: $0\enable[0:0]
|
| 3/9: $0\mode[0:0]
|
| 4/9: $0\stream[0:0]
|
| 5/9: $0\irqena[0:0]
|
| 6/9: $0\mlb[0:0]
|
| 7/9: $0\invcsb[0:0]
|
| 8/9: $0\invsck[0:0]
|
| 9/9: $0\prescaler[7:0]
|
| Creating decoders for process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:100$827'.
|
| 1/13: $0\ack[0][0:0]
|
| 2/13: $0\adr[1][31:0]
|
| 3/13: $0\adr[0][31:0]
|
| 4/13: $0\dat_r[2][31:0]
|
| 5/13: $0\dat_w[1][31:0]
|
| 6/13: $0\dat_w[0][31:0]
|
| 7/13: $0\req[2][0:0]
|
| 8/13: $0\req[1][0:0]
|
| 9/13: $0\we[2][0:0]
|
| 10/13: $0\we[1][0:0]
|
| 11/13: $0\sel[2][3:0]
|
| 12/13: $0\sel[1][3:0]
|
| 13/13: $0\t_state[1:0]
|
| Creating decoders for process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:47$817'.
|
| 1/10: $0\dat_r[1][31:0]
|
| 2/10: $0\dat_r[0][31:0]
|
| 3/10: $0\req[0][0:0]
|
| 4/10: $0\ack[2][0:0]
|
| 5/10: $0\ack[1][0:0]
|
| 6/10: $0\we[0][0:0]
|
| 7/10: $0\sel[0][3:0]
|
| 8/10: $0\dat_w[2][31:0]
|
| 9/10: $0\adr[2][31:0]
|
| 10/10: $0\i_state[1:0]
|
| Creating decoders for process `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mul_div_shift.sv:59$2274'.
|
| 1/6: $0\div_sign[0:0]
|
| 2/6: $0\working[0:0]
|
| 3/6: $0\shift_amt_r[4:0]
|
| 4/6: $0\op_r[3:0]
|
| 5/6: $0\out_valid[0:0]
|
| 6/6: $0\out[31:0]
|
| Creating decoders for process `\fwpayload.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v:206$54'.
|
| Creating decoders for process `\fwpayload.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v:321$49'.
|
| 1/2: $0\gpio_ack_o[0:0]
|
| 2/2: $0\gpio_out_r[7:0]
|
| Creating decoders for process `\fwpayload.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v:219$45'.
|
| 1/1: $0\wb_bridge_state[1:0]
|
| Creating decoders for process `\user_proj_example.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/user_proj_example.v:89$6'.
|
| 1/2: $0\clkcnt[3:0]
|
| 2/2: $0\clock_r[0:0]
|
|
|
| 28.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).
|
| No latch inferred for signal `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.\ra_raddr' from process `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:131$2231'.
|
| No latch inferred for signal `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.\rb_raddr' from process `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:131$2231'.
|
| No latch inferred for signal `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.\op_a' from process `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:131$2231'.
|
| No latch inferred for signal `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.\op_b' from process `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:131$2231'.
|
| No latch inferred for signal `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.\op_c' from process `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:131$2231'.
|
| No latch inferred for signal `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.\op_type_w' from process `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:131$2231'.
|
| No latch inferred for signal `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.\op_w' from process `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:131$2231'.
|
| No latch inferred for signal `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.\i_type' from process `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:131$2231'.
|
| No latch inferred for signal `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.\rd_raddr_w' from process `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:131$2231'.
|
| No latch inferred for signal `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.\rd_waddr' from process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:422$2205'.
|
| No latch inferred for signal `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.\rd_wdata' from process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:422$2205'.
|
| No latch inferred for signal `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.\rd_wen' from process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:404$2170'.
|
| No latch inferred for signal `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.\alu_op' from process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:393$2169'.
|
| No latch inferred for signal `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.\pc_next' from process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:188$2129'.
|
| No latch inferred for signal `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.\pc_seq_next' from process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:188$2129'.
|
| No latch inferred for signal `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.\next_pc_seq_incr' from process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:166$2120'.
|
| No latch inferred for signal `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.\ldst_addr_misaligned' from process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:140$2112'.
|
| No latch inferred for signal `\fwrisc_alu.\out' from process `\fwrisc_alu.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_alu.sv:37$307'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\initiator_target_sel[0]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1191'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\target_initiator_sel[0]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1191'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\initiator_target_sel[1]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1191'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\initiator_target_sel[2]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1191'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\initiator_target_sel[3]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1191'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\target_initiator_sel[1]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1191'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\target_initiator_sel[2]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1191'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\target_initiator_sel[3]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1191'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\tadr [127:96]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1177'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\tdat_w [127:96]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1177'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\tsel [15:12]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1177'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\i2t_mux_ii' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1177'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\tadr [95:64]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1163'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\tdat_w [95:64]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1163'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\tsel [11:8]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1163'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\i2t_mux_ii' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1163'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\tadr [63:32]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1149'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\tdat_w [63:32]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1149'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\tsel [7:4]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1149'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\i2t_mux_ii' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1149'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\tadr [31:0]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1135'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\tdat_w [31:0]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1135'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\tsel [3:0]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1135'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\i2t_mux_ii' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1135'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\dat_r [127:96]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1118'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\ack [3]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1118'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\t2i_ii' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1118'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\dat_r [95:64]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1101'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\ack [2]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1101'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\t2i_ii' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1101'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\dat_r [63:32]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1084'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\ack [1]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1084'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\t2i_ii' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1084'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\dat_r [31:0]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1067'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\ack [0]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1067'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\t2i_ii' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1067'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\i_at_ii' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1062'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_target_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:137$959' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1062'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_target_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:137$960' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1062'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_target_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:137$961' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1062'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_target_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:137$962' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1062'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\initiator_active_target[3]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1062'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\i_at_ii' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1057'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_target_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:137$951' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1057'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_target_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:137$952' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1057'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_target_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:137$953' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1057'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_target_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:137$954' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1057'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\initiator_active_target[2]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1057'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\i_at_ii' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1052'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_target_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:137$943' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1052'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_target_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:137$944' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1052'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_target_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:137$945' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1052'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_target_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:137$946' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1052'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\initiator_active_target[1]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1052'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\i_at_ii' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1047'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\initiator_active_target[0]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1047'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_target_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:137$935' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1047'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_target_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:137$936' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1047'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_target_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:137$937' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1047'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_target_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:137$938' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1047'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\t_ai_ii' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1042'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_gnt$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:117$927' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1042'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_gnt$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:117$928' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1042'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_gnt$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:117$929' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1042'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_gnt$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:117$930' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1042'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\target_active_initiator[3]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1042'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\t_ai_ii' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1037'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_gnt$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:117$919' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1037'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_gnt$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:117$920' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1037'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_gnt$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:117$921' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1037'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_gnt$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:117$922' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1037'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\target_active_initiator[2]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1037'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\t_ai_ii' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1032'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_gnt$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:117$911' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1032'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_gnt$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:117$912' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1032'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_gnt$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:117$913' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1032'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_gnt$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:117$914' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1032'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\target_active_initiator[1]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1032'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\t_ai_ii' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1027'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.\target_active_initiator[0]' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1027'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_gnt$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:117$903' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1027'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_gnt$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:117$904' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1027'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_gnt$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:117$905' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1027'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\initiator_gnt$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:117$906' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1027'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\target_initiator_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:82$898' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1025'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\target_initiator_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:82$897' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1023'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\target_initiator_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:82$896' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1021'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\target_initiator_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:82$895' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1019'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\target_initiator_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:82$894' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1017'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\target_initiator_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:82$893' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1015'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\target_initiator_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:82$892' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1013'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\target_initiator_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:82$891' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1011'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\target_initiator_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:82$890' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1009'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\target_initiator_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:82$889' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1007'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\target_initiator_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:82$888' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1005'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\target_initiator_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:82$887' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1003'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\target_initiator_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:82$886' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1001'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\target_initiator_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:82$885' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$999'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\target_initiator_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:82$884' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$997'.
|
| No latch inferred for signal `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$mem2bits$\target_initiator_sel$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:82$883' from process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$995'.
|
|
|
| 28.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
|
| Creating register for signal `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.\state' using process `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_fetch.sv:74$2269'.
|
| created $dff cell `$procdff$4310' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.\iaddr' using process `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_fetch.sv:74$2269'.
|
| created $dff cell `$procdff$4311' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.\instr' using process `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_fetch.sv:74$2269'.
|
| created $dff cell `$procdff$4312' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.\instr_c' using process `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_fetch.sv:74$2269'.
|
| created $dff cell `$procdff$4313' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.\instr_cache' using process `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_fetch.sv:74$2269'.
|
| created $dff cell `$procdff$4314' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.\instr_cache_valid' using process `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_fetch.sv:74$2269'.
|
| created $dff cell `$procdff$4315' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.\fetch_valid_r' using process `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_fetch.sv:74$2269'.
|
| created $dff cell `$procdff$4316' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.\ivalid_r' using process `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_fetch.sv:74$2269'.
|
| created $dff cell `$procdff$4317' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.\rd_raddr' using process `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:351$2259'.
|
| created $dff cell `$procdff$4318' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.\op_type' using process `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:351$2259'.
|
| created $dff cell `$procdff$4319' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.\imm_lui' using process `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:351$2259'.
|
| created $dff cell `$procdff$4320' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.\decode_valid_r' using process `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:351$2259'.
|
| created $dff cell `$procdff$4321' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.\decode_state' using process `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:351$2259'.
|
| created $dff cell `$procdff$4322' with positive edge clock.
|
| Creating register for signal `\fwrisc_mem.\dvalid' using process `\fwrisc_mem.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mem.sv:60$490'.
|
| created $dff cell `$procdff$4323' with positive edge clock.
|
| Creating register for signal `\fwrisc_mem.\daddr' using process `\fwrisc_mem.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mem.sv:60$490'.
|
| created $dff cell `$procdff$4324' with positive edge clock.
|
| Creating register for signal `\fwrisc_mem.\dwdata' using process `\fwrisc_mem.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mem.sv:60$490'.
|
| created $dff cell `$procdff$4325' with positive edge clock.
|
| Creating register for signal `\fwrisc_mem.\dwstb' using process `\fwrisc_mem.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mem.sv:60$490'.
|
| created $dff cell `$procdff$4326' with positive edge clock.
|
| Creating register for signal `\fwrisc_mem.\dwrite' using process `\fwrisc_mem.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mem.sv:60$490'.
|
| created $dff cell `$procdff$4327' with positive edge clock.
|
| Creating register for signal `\fwrisc_mem.\ack_valid' using process `\fwrisc_mem.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mem.sv:60$490'.
|
| created $dff cell `$procdff$4328' with positive edge clock.
|
| Creating register for signal `\fwrisc_mem.\ack_data' using process `\fwrisc_mem.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mem.sv:60$490'.
|
| created $dff cell `$procdff$4329' with positive edge clock.
|
| Creating register for signal `\fwrisc_mem.\mem_state' using process `\fwrisc_mem.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mem.sv:60$490'.
|
| created $dff cell `$procdff$4330' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.\pc' using process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:199$2133'.
|
| created $dff cell `$procdff$4331' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.\instr_complete' using process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:199$2133'.
|
| created $dff cell `$procdff$4332' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.\pc_seq' using process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:199$2133'.
|
| created $dff cell `$procdff$4333' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.\exec_state' using process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:199$2133'.
|
| created $dff cell `$procdff$4334' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.\mcause' using process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:199$2133'.
|
| created $dff cell `$procdff$4335' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.\mtval' using process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:153$2117'.
|
| created $dff cell `$procdff$4336' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.\ra_rdata' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:125$2032'.
|
| created $dff cell `$procdff$4337' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.\rb_rdata' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:125$2032'.
|
| created $dff cell `$procdff$4338' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:129$1951_ADDR' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:125$2032'.
|
| created $dff cell `$procdff$4339' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:129$1951_DATA' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:125$2032'.
|
| created $dff cell `$procdff$4340' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:129$1951_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:125$2032'.
|
| created $dff cell `$procdff$4341' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.\cycle_count' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4342' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.\instr_count' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4343' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.\dep_lo_r' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4344' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.\dep_hi_r' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4345' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.\mtvec_r' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4346' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.\reg_i' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4347' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4348' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4349' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4350' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4351' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4352' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4353' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4354' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4355' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4356' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4357' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4358' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4359' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4360' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4361' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4362' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4363' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4364' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4365' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4366' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4367' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4368' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4369' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4370' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4371' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4372' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4373' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4374' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4375' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4376' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4377' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4378' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4379' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4380' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4381' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4382' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4383' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4384' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4385' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4386' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1926_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4387' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1927_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4388' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1928_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4389' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1929_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4390' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1930_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4391' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1931_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4392' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1932_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4393' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1933_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4394' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1934_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4395' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1935_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4396' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1936_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4397' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1937_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4398' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1938_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4399' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1939_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4400' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1940_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4401' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1941_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4402' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1942_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4403' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1943_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4404' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1944_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4405' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1945_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4406' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1946_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4407' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1947_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4408' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1948_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4409' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1949_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4410' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1950_EN' using process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| created $dff cell `$procdff$4411' with positive edge clock.
|
| Creating register for signal `$paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.\tracer_pc' using process `$paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:130$1820'.
|
| created $dff cell `$procdff$4412' with positive edge clock.
|
| Creating register for signal `$paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.\tracer_instr' using process `$paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:130$1820'.
|
| created $dff cell `$procdff$4413' with positive edge clock.
|
| Creating register for signal `$paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.\soft_reset_count' using process `$paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:66$1817'.
|
| created $dff cell `$procdff$4414' with positive edge clock.
|
| Creating register for signal `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.\a_dat_o' using process `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:19$1269'.
|
| created $dff cell `$procdff$4415' with positive edge clock.
|
| Creating register for signal `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$memwr$\ram_0$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:21$1265_ADDR' using process `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:19$1269'.
|
| created $dff cell `$procdff$4416' with positive edge clock.
|
| Creating register for signal `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$memwr$\ram_0$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:21$1265_DATA' using process `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:19$1269'.
|
| created $dff cell `$procdff$4417' with positive edge clock.
|
| Creating register for signal `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$memwr$\ram_0$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:21$1265_EN' using process `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:19$1269'.
|
| created $dff cell `$procdff$4418' with positive edge clock.
|
| Creating register for signal `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$memwr$\ram_1$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:22$1266_ADDR' using process `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:19$1269'.
|
| created $dff cell `$procdff$4419' with positive edge clock.
|
| Creating register for signal `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$memwr$\ram_1$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:22$1266_DATA' using process `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:19$1269'.
|
| created $dff cell `$procdff$4420' with positive edge clock.
|
| Creating register for signal `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$memwr$\ram_1$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:22$1266_EN' using process `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:19$1269'.
|
| created $dff cell `$procdff$4421' with positive edge clock.
|
| Creating register for signal `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$memwr$\ram_2$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:23$1267_ADDR' using process `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:19$1269'.
|
| created $dff cell `$procdff$4422' with positive edge clock.
|
| Creating register for signal `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$memwr$\ram_2$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:23$1267_DATA' using process `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:19$1269'.
|
| created $dff cell `$procdff$4423' with positive edge clock.
|
| Creating register for signal `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$memwr$\ram_2$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:23$1267_EN' using process `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:19$1269'.
|
| created $dff cell `$procdff$4424' with positive edge clock.
|
| Creating register for signal `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$memwr$\ram_3$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:24$1268_ADDR' using process `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:19$1269'.
|
| created $dff cell `$procdff$4425' with positive edge clock.
|
| Creating register for signal `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$memwr$\ram_3$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:24$1268_DATA' using process `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:19$1269'.
|
| created $dff cell `$procdff$4426' with positive edge clock.
|
| Creating register for signal `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$memwr$\ram_3$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:24$1268_EN' using process `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:19$1269'.
|
| created $dff cell `$procdff$4427' with positive edge clock.
|
| Creating register for signal `$paramod\wb_interconnect_arb\N_REQ=4.\state' using process `$paramod\wb_interconnect_arb\N_REQ=4.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_arb.v:106$1781'.
|
| created $dff cell `$procdff$4428' with positive edge clock.
|
| Creating register for signal `$paramod\wb_interconnect_arb\N_REQ=4.\last_gnt' using process `$paramod\wb_interconnect_arb\N_REQ=4.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_arb.v:106$1781'.
|
| created $dff cell `$procdff$4429' with positive edge clock.
|
| Creating register for signal `\simpleuart.\send_pattern' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:191$288'.
|
| created $dff cell `$procdff$4430' with positive edge clock.
|
| Creating register for signal `\simpleuart.\send_bitcnt' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:191$288'.
|
| created $dff cell `$procdff$4431' with positive edge clock.
|
| Creating register for signal `\simpleuart.\send_divcnt' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:191$288'.
|
| created $dff cell `$procdff$4432' with positive edge clock.
|
| Creating register for signal `\simpleuart.\send_dummy' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:191$288'.
|
| created $dff cell `$procdff$4433' with positive edge clock.
|
| Creating register for signal `\simpleuart.\recv_state' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:148$278'.
|
| created $dff cell `$procdff$4434' with positive edge clock.
|
| Creating register for signal `\simpleuart.\recv_divcnt' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:148$278'.
|
| created $dff cell `$procdff$4435' with positive edge clock.
|
| Creating register for signal `\simpleuart.\recv_pattern' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:148$278'.
|
| created $dff cell `$procdff$4436' with positive edge clock.
|
| Creating register for signal `\simpleuart.\recv_buf_data' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:148$278'.
|
| created $dff cell `$procdff$4437' with positive edge clock.
|
| Creating register for signal `\simpleuart.\recv_buf_valid' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:148$278'.
|
| created $dff cell `$procdff$4438' with positive edge clock.
|
| Creating register for signal `\simpleuart.\enabled' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:135$276'.
|
| created $dff cell `$procdff$4439' with positive edge clock.
|
| Creating register for signal `\simpleuart.\cfg_divider' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:135$276'.
|
| created $dff cell `$procdff$4440' with positive edge clock.
|
| Creating register for signal `\simple_spi_master.\isdo' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:344$235'.
|
| created $adff cell `$procdff$4441' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\treg' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:344$235'.
|
| created $adff cell `$procdff$4442' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\rreg' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:344$235'.
|
| created $adff cell `$procdff$4443' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\isck' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:331$229'.
|
| created $adff cell `$procdff$4444' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\hsck' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:312$223'.
|
| created $adff cell `$procdff$4445' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\count' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:312$223'.
|
| created $adff cell `$procdff$4446' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\state' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:276$212'.
|
| created $adff cell `$procdff$4447' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\done' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:276$212'.
|
| created $adff cell `$procdff$4448' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\icsb' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:276$212'.
|
| created $adff cell `$procdff$4449' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\nbit' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:276$212'.
|
| created $adff cell `$procdff$4450' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\err_out' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:232$195'.
|
| created $adff cell `$procdff$4451' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\d_latched' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:232$195'.
|
| created $adff cell `$procdff$4452' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\w_latched' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:232$195'.
|
| created $adff cell `$procdff$4453' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\r_latched' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:232$195'.
|
| created $adff cell `$procdff$4454' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\prescaler' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:201$193'.
|
| created $adff cell `$procdff$4455' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\invsck' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:201$193'.
|
| created $adff cell `$procdff$4456' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\invcsb' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:201$193'.
|
| created $adff cell `$procdff$4457' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\mlb' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:201$193'.
|
| created $adff cell `$procdff$4458' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\irqena' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:201$193'.
|
| created $adff cell `$procdff$4459' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\stream' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:201$193'.
|
| created $adff cell `$procdff$4460' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\mode' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:201$193'.
|
| created $adff cell `$procdff$4461' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\enable' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:201$193'.
|
| created $adff cell `$procdff$4462' with positive edge clock and negative level reset.
|
| Creating register for signal `\simple_spi_master.\hkconn' using process `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:201$193'.
|
| created $adff cell `$procdff$4463' with positive edge clock and negative level reset.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\t_state' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:100$827'.
|
| created $dff cell `$procdff$4464' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\dat_r[2]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:100$827'.
|
| created $dff cell `$procdff$4465' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\adr[0]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:100$827'.
|
| created $dff cell `$procdff$4466' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\adr[1]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:100$827'.
|
| created $dff cell `$procdff$4467' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\dat_w[0]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:100$827'.
|
| created $dff cell `$procdff$4468' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\dat_w[1]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:100$827'.
|
| created $dff cell `$procdff$4469' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\sel[1]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:100$827'.
|
| created $dff cell `$procdff$4470' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\sel[2]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:100$827'.
|
| created $dff cell `$procdff$4471' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\we[1]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:100$827'.
|
| created $dff cell `$procdff$4472' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\we[2]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:100$827'.
|
| created $dff cell `$procdff$4473' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\ack[0]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:100$827'.
|
| created $dff cell `$procdff$4474' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\req[1]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:100$827'.
|
| created $dff cell `$procdff$4475' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\req[2]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:100$827'.
|
| created $dff cell `$procdff$4476' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\i_state' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:47$817'.
|
| created $dff cell `$procdff$4477' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\dat_r[0]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:47$817'.
|
| created $dff cell `$procdff$4478' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\dat_r[1]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:47$817'.
|
| created $dff cell `$procdff$4479' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\adr[2]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:47$817'.
|
| created $dff cell `$procdff$4480' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\dat_w[2]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:47$817'.
|
| created $dff cell `$procdff$4481' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\sel[0]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:47$817'.
|
| created $dff cell `$procdff$4482' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\we[0]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:47$817'.
|
| created $dff cell `$procdff$4483' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\ack[1]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:47$817'.
|
| created $dff cell `$procdff$4484' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\ack[2]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:47$817'.
|
| created $dff cell `$procdff$4485' with positive edge clock.
|
| Creating register for signal `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.\req[0]' using process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:47$817'.
|
| created $dff cell `$procdff$4486' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0.\out' using process `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mul_div_shift.sv:59$2274'.
|
| created $dff cell `$procdff$4487' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0.\out_valid' using process `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mul_div_shift.sv:59$2274'.
|
| created $dff cell `$procdff$4488' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0.\op_r' using process `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mul_div_shift.sv:59$2274'.
|
| created $dff cell `$procdff$4489' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0.\shift_amt_r' using process `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mul_div_shift.sv:59$2274'.
|
| created $dff cell `$procdff$4490' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0.\working' using process `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mul_div_shift.sv:59$2274'.
|
| created $dff cell `$procdff$4491' with positive edge clock.
|
| Creating register for signal `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0.\div_sign' using process `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mul_div_shift.sv:59$2274'.
|
| created $dff cell `$procdff$4492' with positive edge clock.
|
| Creating register for signal `\fwpayload.\gpio_out_r' using process `\fwpayload.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v:321$49'.
|
| created $dff cell `$procdff$4493' with positive edge clock.
|
| Creating register for signal `\fwpayload.\gpio_ack_o' using process `\fwpayload.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v:321$49'.
|
| created $dff cell `$procdff$4494' with positive edge clock.
|
| Creating register for signal `\fwpayload.\wb_bridge_state' using process `\fwpayload.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v:219$45'.
|
| created $dff cell `$procdff$4495' with positive edge clock.
|
| Creating register for signal `\user_proj_example.\clkcnt' using process `\user_proj_example.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/user_proj_example.v:89$6'.
|
| created $dff cell `$procdff$4496' with positive edge clock.
|
| Creating register for signal `\user_proj_example.\clock_r' using process `\user_proj_example.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/user_proj_example.v:89$6'.
|
| created $dff cell `$procdff$4497' with positive edge clock.
|
|
|
| 28.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
| Found and cleaned up 6 empty switches in `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_fetch.sv:74$2269'.
|
| Removing empty process `$paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_fetch.sv:74$2269'.
|
| Found and cleaned up 4 empty switches in `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:351$2259'.
|
| Removing empty process `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:351$2259'.
|
| Found and cleaned up 26 empty switches in `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:131$2231'.
|
| Removing empty process `$paramod\fwrisc_decode\ENABLE_COMPRESSED=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_decode.sv:131$2231'.
|
| Found and cleaned up 12 empty switches in `\fwrisc_mem.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mem.sv:60$490'.
|
| Removing empty process `fwrisc_mem.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mem.sv:60$490'.
|
| Removing empty process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:111$2226'.
|
| Found and cleaned up 2 empty switches in `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:422$2205'.
|
| Removing empty process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:422$2205'.
|
| Removing empty process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:404$2170'.
|
| Found and cleaned up 1 empty switch in `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:393$2169'.
|
| Removing empty process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:393$2169'.
|
| Found and cleaned up 12 empty switches in `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:199$2133'.
|
| Removing empty process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:199$2133'.
|
| Found and cleaned up 1 empty switch in `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:188$2129'.
|
| Removing empty process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:188$2129'.
|
| Found and cleaned up 1 empty switch in `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:166$2120'.
|
| Removing empty process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:166$2120'.
|
| Found and cleaned up 3 empty switches in `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:153$2117'.
|
| Removing empty process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:153$2117'.
|
| Found and cleaned up 2 empty switches in `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:140$2112'.
|
| Removing empty process `$paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:140$2112'.
|
| Found and cleaned up 3 empty switches in `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:125$2032'.
|
| Removing empty process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:125$2032'.
|
| Found and cleaned up 6 empty switches in `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| Removing empty process `$paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:86$1954'.
|
| Found and cleaned up 2 empty switches in `$paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:130$1820'.
|
| Removing empty process `$paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:130$1820'.
|
| Found and cleaned up 3 empty switches in `$paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:66$1817'.
|
| Removing empty process `$paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc.sv:66$1817'.
|
| Found and cleaned up 5 empty switches in `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:19$1269'.
|
| Removing empty process `$paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/spram.v:19$1269'.
|
| Found and cleaned up 1 empty switch in `\fwrisc_alu.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_alu.sv:37$307'.
|
| Removing empty process `fwrisc_alu.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_alu.sv:37$307'.
|
| Removing empty process `$paramod\wb_interconnect_arb\N_REQ=4.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_arb.v:23$1814'.
|
| Found and cleaned up 4 empty switches in `$paramod\wb_interconnect_arb\N_REQ=4.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_arb.v:106$1781'.
|
| Removing empty process `$paramod\wb_interconnect_arb\N_REQ=4.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_arb.v:106$1781'.
|
| Found and cleaned up 5 empty switches in `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:191$288'.
|
| Removing empty process `simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:191$288'.
|
| Found and cleaned up 7 empty switches in `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:148$278'.
|
| Removing empty process `simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:148$278'.
|
| Found and cleaned up 6 empty switches in `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:135$276'.
|
| Removing empty process `simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simpleuart.v:135$276'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1191'.
|
| Found and cleaned up 4 empty switches in `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1177'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1177'.
|
| Found and cleaned up 4 empty switches in `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1163'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1163'.
|
| Found and cleaned up 4 empty switches in `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1149'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1149'.
|
| Found and cleaned up 4 empty switches in `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1135'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:193$1135'.
|
| Found and cleaned up 8 empty switches in `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1118'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1118'.
|
| Found and cleaned up 8 empty switches in `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1101'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1101'.
|
| Found and cleaned up 8 empty switches in `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1084'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1084'.
|
| Found and cleaned up 8 empty switches in `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1067'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:170$1067'.
|
| Found and cleaned up 4 empty switches in `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1062'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1062'.
|
| Found and cleaned up 4 empty switches in `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1057'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1057'.
|
| Found and cleaned up 4 empty switches in `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1052'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1052'.
|
| Found and cleaned up 4 empty switches in `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1047'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:133$1047'.
|
| Found and cleaned up 4 empty switches in `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1042'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1042'.
|
| Found and cleaned up 4 empty switches in `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1037'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1037'.
|
| Found and cleaned up 4 empty switches in `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1032'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1032'.
|
| Found and cleaned up 4 empty switches in `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1027'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:114$1027'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1025'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1023'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1021'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1019'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1017'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1015'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1013'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1011'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1009'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1007'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1005'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1003'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$1001'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$999'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$997'.
|
| Removing empty process `$paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_NxN.v:0$995'.
|
| Found and cleaned up 6 empty switches in `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:344$235'.
|
| Removing empty process `simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:344$235'.
|
| Found and cleaned up 1 empty switch in `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:331$229'.
|
| Removing empty process `simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:331$229'.
|
| Found and cleaned up 2 empty switches in `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:312$223'.
|
| Removing empty process `simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:312$223'.
|
| Found and cleaned up 6 empty switches in `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:276$212'.
|
| Removing empty process `simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:276$212'.
|
| Found and cleaned up 9 empty switches in `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:232$195'.
|
| Removing empty process `simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:232$195'.
|
| Found and cleaned up 2 empty switches in `\simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:201$193'.
|
| Removing empty process `simple_spi_master.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/simple_spi_master.v:201$193'.
|
| Found and cleaned up 5 empty switches in `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:100$827'.
|
| Removing empty process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:100$827'.
|
| Found and cleaned up 5 empty switches in `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:47$817'.
|
| Removing empty process `$paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-bridges/verilog/rtl/wb_clockdomain_bridge.v:47$817'.
|
| Found and cleaned up 10 empty switches in `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mul_div_shift.sv:59$2274'.
|
| Removing empty process `$paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_mul_div_shift.sv:59$2274'.
|
| Removing empty process `fwpayload.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v:206$54'.
|
| Found and cleaned up 2 empty switches in `\fwpayload.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v:321$49'.
|
| Removing empty process `fwpayload.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v:321$49'.
|
| Found and cleaned up 3 empty switches in `\fwpayload.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v:219$45'.
|
| Removing empty process `fwpayload.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwpayload.v:219$45'.
|
| Found and cleaned up 2 empty switches in `\user_proj_example.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/user_proj_example.v:89$6'.
|
| Removing empty process `user_proj_example.$proc$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/user_proj_example.v:89$6'.
|
| Cleaned up 245 empty switches.
|
|
|
| 28.3. Executing FLATTEN pass (flatten design).
|
| Deleting now unused module $paramod\fwrisc_fetch\ENABLE_COMPRESSED=0.
|
| Deleting now unused module $paramod\fwrisc_decode\ENABLE_COMPRESSED=0.
|
| Deleting now unused module fwrisc_mem.
|
| Deleting now unused module $paramod\fwrisc_exec\ENABLE_COMPRESSED=0\ENABLE_MUL_DIV=0.
|
| Deleting now unused module $paramod\fwrisc_regfile\ENABLE_COUNTERS=1\ENABLE_DEP=0.
|
| Deleting now unused module $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc.
|
| Deleting now unused module $paramod\spram_byte_en\ADDR_BITS=8\DATA_BITS=32.
|
| Deleting now unused module fwrisc_alu.
|
| Deleting now unused module $paramod$efff260aa0aa068c8a6e1c1a71417eb71b8013c8\fwrisc_wb.
|
| Deleting now unused module $paramod\wb_interconnect_arb\N_REQ=4.
|
| Deleting now unused module simpleuart.
|
| Deleting now unused module $paramod$e4f9eed6a3ef0553cd9ce1fc49d4e8623710dadf\wb_interconnect_NxN.
|
| Deleting now unused module simple_spi_master.
|
| Deleting now unused module $paramod\simpleuart_wb\BASE_ADR=0.
|
| Deleting now unused module $paramod\simple_spi_master_wb\BASE_ADR=0.
|
| Deleting now unused module $paramod\wb_clockdomain_bridge\ADR_WIDTH=32\DAT_WIDTH=32.
|
| Deleting now unused module spram_32x256.
|
| Deleting now unused module fwrisc_rv32i_wb.
|
| Deleting now unused module $paramod\fwrisc_mul_div_shift\ENABLE_MUL_DIV=0.
|
| Deleting now unused module fwpayload.
|
| <suppressed ~23 debug messages>
|
|
|
| 28.4. Executing OPT_EXPR pass (perform const folding).
|
| Optimizing module user_proj_example.
|
| <suppressed ~264 debug messages>
|
|
|
| 28.5. Executing OPT_CLEAN pass (remove unused cells and wires).
|
| Finding unused cells or wires in module \user_proj_example..
|
| Removed 178 unused cells and 1568 unused wires.
|
| <suppressed ~235 debug messages>
|
|
|
| 28.6. Executing CHECK pass (checking for obvious problems).
|
| checking module user_proj_example..
|
| Warning: multiple conflicting drivers for user_proj_example.\io_in [31]:
|
| port Y[0] of cell $ternary$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/user_proj_example.v:186$44 ($mux)
|
| module input io_in[31]
|
| Warning: multiple conflicting drivers for user_proj_example.\io_in [32]:
|
| port Y[0] of cell $ternary$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/user_proj_example.v:185$42 ($mux)
|
| module input io_in[32]
|
| Warning: multiple conflicting drivers for user_proj_example.\io_in [33]:
|
| port Y[0] of cell $ternary$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/user_proj_example.v:184$40 ($mux)
|
| module input io_in[33]
|
| Warning: multiple conflicting drivers for user_proj_example.\io_in [34]:
|
| port Y[0] of cell $ternary$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/user_proj_example.v:183$38 ($mux)
|
| module input io_in[34]
|
| Warning: Wire user_proj_example.\la_data_out [127] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [126] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [125] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [124] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [123] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [122] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [121] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [120] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [119] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [118] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [117] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [116] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [111] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [110] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [109] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [108] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [107] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [106] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [105] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [104] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [103] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [102] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [101] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [100] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [99] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [98] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [96] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [64] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [63] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [62] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [61] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [60] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [59] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [58] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [57] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [56] is used but has no driver.
|
| Warning: Wire user_proj_example.\la_data_out [55] is used but has no driver.
|
| Warning: Wire user_proj_example.\io_out [37] is used but has no driver.
|
| Warning: Wire user_proj_example.\io_out [34] is used but has no driver.
|
| Warning: Wire user_proj_example.\io_out [33] is used but has no driver.
|
| Warning: Wire user_proj_example.\io_out [32] is used but has no driver.
|
| Warning: Wire user_proj_example.\io_out [31] is used but has no driver.
|
| Warning: Wire user_proj_example.\io_out [30] is used but has no driver.
|
| Warning: Wire user_proj_example.\io_out [29] is used but has no driver.
|
| Warning: Wire user_proj_example.\io_out [28] is used but has no driver.
|
| Warning: Wire user_proj_example.\io_out [27] is used but has no driver.
|
| Warning: Wire user_proj_example.\io_out [22] is used but has no driver.
|
| Warning: Wire user_proj_example.\io_out [18] is used but has no driver.
|
| Warning: Wire user_proj_example.\io_out [17] is used but has no driver.
|
| Warning: Wire user_proj_example.\io_oeb [37] is used but has no driver.
|
| Warning: Wire user_proj_example.\io_oeb [19] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [31] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [30] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [29] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [28] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [27] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [26] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [25] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [24] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [23] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [22] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [21] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [20] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [19] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [18] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [17] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [16] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [15] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [14] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [13] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [12] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [11] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [10] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [9] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [8] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [7] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [6] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [5] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [4] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [3] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [2] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [1] is used but has no driver.
|
| Warning: Wire user_proj_example.\u_payload.u_uart.simpleuart_reg_cfg_do [0] is used but has no driver.
|
| found and reported 87 problems.
|
|
|
| 28.7. Executing OPT pass (performing simple optimizations).
|
|
|
| 28.7.1. Executing OPT_EXPR pass (perform const folding).
|
| Optimizing module user_proj_example.
|
| <suppressed ~1 debug messages>
|
|
|
| 28.7.2. Executing OPT_MERGE pass (detect identical cells).
|
| Finding identical cells in module `\user_proj_example'.
|
| <suppressed ~873 debug messages>
|
| Removed a total of 291 cells.
|
|
|
| 28.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
| Running muxtree optimizer on module \user_proj_example..
|
| Creating internal representation of mux trees.
|
| Evaluating internal representation of mux trees.
|
| Replacing known input bits on port A of cell $flatten\u_payload.\u_ic.\s_arb[0].aw_arb.$procmux$3396: \u_payload.u_ic.s_arb[0].aw_arb.state -> 1'0
|
| Replacing known input bits on port A of cell $flatten\u_payload.\u_ic.\s_arb[0].aw_arb.$procmux$3394: \u_payload.u_ic.s_arb[0].aw_arb.state -> 1'1
|
| Replacing known input bits on port A of cell $flatten\u_payload.\u_ic.\s_arb[0].aw_arb.$procmux$3398: \u_payload.u_ic.s_arb[0].aw_arb.state -> 1'0
|
| Replacing known input bits on port A of cell $flatten\u_payload.\u_ic.\s_arb[1].aw_arb.$procmux$3396: \u_payload.u_ic.s_arb[1].aw_arb.state -> 1'0
|
| Replacing known input bits on port A of cell $flatten\u_payload.\u_ic.\s_arb[1].aw_arb.$procmux$3394: \u_payload.u_ic.s_arb[1].aw_arb.state -> 1'1
|
| Replacing known input bits on port A of cell $flatten\u_payload.\u_ic.\s_arb[1].aw_arb.$procmux$3398: \u_payload.u_ic.s_arb[1].aw_arb.state -> 1'0
|
| Replacing known input bits on port A of cell $flatten\u_payload.\u_ic.\s_arb[2].aw_arb.$procmux$3396: \u_payload.u_ic.s_arb[2].aw_arb.state -> 1'0
|
| Replacing known input bits on port A of cell $flatten\u_payload.\u_ic.\s_arb[2].aw_arb.$procmux$3394: \u_payload.u_ic.s_arb[2].aw_arb.state -> 1'1
|
| Replacing known input bits on port A of cell $flatten\u_payload.\u_ic.\s_arb[2].aw_arb.$procmux$3398: \u_payload.u_ic.s_arb[2].aw_arb.state -> 1'0
|
| Replacing known input bits on port A of cell $flatten\u_payload.\u_ic.\s_arb[3].aw_arb.$procmux$3396: \u_payload.u_ic.s_arb[3].aw_arb.state -> 1'0
|
| Replacing known input bits on port A of cell $flatten\u_payload.\u_ic.\s_arb[3].aw_arb.$procmux$3394: \u_payload.u_ic.s_arb[3].aw_arb.state -> 1'1
|
| Replacing known input bits on port A of cell $flatten\u_payload.\u_ic.\s_arb[3].aw_arb.$procmux$3398: \u_payload.u_ic.s_arb[3].aw_arb.state -> 1'0
|
| Analyzing evaluation results.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2482.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2490.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2498.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2513.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_exec.$procmux$3057.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2528.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2544.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2547.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2549.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2565.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2567.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2578.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2599.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2608.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2622.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2636.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2638.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2649.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2663.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2665.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2672.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2682.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2684.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3674.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3683.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3686.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3695.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3698.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3707.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3710.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3722.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3731.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3734.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3743.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3746.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3755.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3758.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3770.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3779.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3782.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3791.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3794.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3803.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3806.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3818.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3827.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3830.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3839.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3842.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3851.
|
| dead port 1/2 on $mux $flatten\u_payload.\u_ic.$procmux$3854.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2693.
|
| dead port 2/2 on $mux $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2708.
|
| Removed 53 multiplexer ports.
|
| <suppressed ~267 debug messages>
|
|
|
| 28.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
| Optimizing cells in module \user_proj_example.
|
| New input vector for $reduce_or cell $flatten\u_payload.\u_ic.\s_arb[3].aw_arb.$reduce_or$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_arb.v:103$1779: \u_payload.u_ic.s_arb[3].aw_arb.masked_gnt [3:1]
|
| New input vector for $reduce_or cell $flatten\u_payload.\u_ic.\s_arb[2].aw_arb.$reduce_or$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_arb.v:103$1779: \u_payload.u_ic.s_arb[2].aw_arb.masked_gnt [3:1]
|
| New input vector for $reduce_or cell $flatten\u_payload.\u_ic.\s_arb[1].aw_arb.$reduce_or$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_arb.v:103$1779: \u_payload.u_ic.s_arb[1].aw_arb.masked_gnt [3:1]
|
| New input vector for $reduce_or cell $flatten\u_payload.\u_ic.\s_arb[0].aw_arb.$reduce_or$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fw-wishbone-interconnect/verilog/rtl/wb_interconnect_arb.v:103$1779: \u_payload.u_ic.s_arb[0].aw_arb.masked_gnt [3:1]
|
| New ctrl vector for $pmux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_exec.$procmux$2883: { $flatten\u_payload.\u_core.\u_core.\u_core.\u_exec.$eq$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:141$2113_Y $flatten\u_payload.\u_core.\u_core.\u_core.\u_exec.$eq$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:132$2222_Y $flatten\u_payload.\u_core.\u_core.\u_core.\u_exec.$eq$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:132$2223_Y $flatten\u_payload.\u_core.\u_core.\u_core.\u_exec.$eq$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:414$2195_Y $flatten\u_payload.\u_core.\u_core.\u_core.\u_exec.$eq$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:411$2182_Y $flatten\u_payload.\u_core.\u_core.\u_core.\u_exec.$eq$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:415$2198_Y $flatten\u_payload.\u_core.\u_core.\u_core.\u_exec.$eq$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:415$2199_Y $auto$opt_reduce.cc:134:opt_mux$4499 }
|
| New ctrl vector for $pmux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_exec.$procmux$2963: { $flatten\u_payload.\u_core.\u_core.\u_core.\u_exec.$eq$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:141$2113_Y $flatten\u_payload.\u_core.\u_core.\u_core.\u_exec.$eq$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:132$2222_Y $flatten\u_payload.\u_core.\u_core.\u_core.\u_exec.$eq$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:132$2223_Y $flatten\u_payload.\u_core.\u_core.\u_core.\u_exec.$eq$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:414$2195_Y $flatten\u_payload.\u_core.\u_core.\u_core.\u_exec.$eq$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_exec.sv:411$2182_Y $auto$opt_reduce.cc:134:opt_mux$4501 }
|
| New ctrl vector for $pmux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_fetch.$procmux$2310: { $auto$opt_reduce.cc:134:opt_mux$4505 $auto$opt_reduce.cc:134:opt_mux$4503 }
|
| New ctrl vector for $pmux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_fetch.$procmux$2318: $auto$opt_reduce.cc:134:opt_mux$4507
|
| New ctrl vector for $pmux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_fetch.$procmux$2327: $auto$opt_reduce.cc:134:opt_mux$4509
|
| New ctrl vector for $pmux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_fetch.$procmux$2380: $auto$opt_reduce.cc:134:opt_mux$4511
|
| New ctrl vector for $pmux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2605: $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2607_CTRL
|
| New ctrl vector for $pmux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_fetch.$procmux$2387: { $flatten\u_payload.\u_core.\u_core.\u_core.\u_fetch.$procmux$2312_CMP $auto$opt_reduce.cc:134:opt_mux$4513 }
|
| New ctrl vector for $pmux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2611: { $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2593_CMP [0] $auto$opt_reduce.cc:134:opt_mux$4515 $flatten\u_payload.\u_core.\u_core.\u_core.\u_decode.$procmux$2600_CMP }
|
| New ctrl vector for $pmux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_fetch.$procmux$2411: { $flatten\u_payload.\u_core.\u_core.\u_core.\u_fetch.$procmux$2312_CMP $auto$opt_reduce.cc:134:opt_mux$4517 }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3069_Y [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3099:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1887_EN[31:0]$1955 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3102:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1888_EN[31:0]$1956 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3105:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1889_EN[31:0]$1957 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3108:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1890_EN[31:0]$1958 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3111:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1891_EN[31:0]$1959 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3114:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1892_EN[31:0]$1960 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3117:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1893_EN[31:0]$1961 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3120:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1894_EN[31:0]$1962 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3123:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1895_EN[31:0]$1963 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3126:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1896_EN[31:0]$1964 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3129:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1897_EN[31:0]$1965 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3132:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1898_EN[31:0]$1966 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3135:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1899_EN[31:0]$1967 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3138:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1900_EN[31:0]$1968 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3141:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1901_EN[31:0]$1969 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3144:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1902_EN[31:0]$1970 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3147:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1903_EN[31:0]$1971 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3150:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1904_EN[31:0]$1972 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3153:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1905_EN[31:0]$1973 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3156:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1906_EN[31:0]$1974 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3159:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1907_EN[31:0]$1975 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3162:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1908_EN[31:0]$1976 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3165:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1909_EN[31:0]$1977 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3168:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1910_EN[31:0]$1978 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3171:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1911_EN[31:0]$1979 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3174:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1912_EN[31:0]$1980 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3177:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1913_EN[31:0]$1981 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3180:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1914_EN[31:0]$1982 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3183:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1915_EN[31:0]$1983 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3186:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1916_EN[31:0]$1984 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3189:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1917_EN[31:0]$1985 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3192:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1918_EN[31:0]$1986 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3195:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1919_EN[31:0]$1987 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3198:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1920_EN[31:0]$1988 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3201:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1921_EN[31:0]$1989 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3204:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1922_EN[31:0]$1990 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3207:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1923_EN[31:0]$1991 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3210:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1924_EN[31:0]$1992 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3213:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1925_EN[31:0]$1993 [0] }
|
| Consolidated identical input bits for $mux cell $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$procmux$3216:
|
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1926_EN[31:0]$1994
|
| New ports: A=1'0, B=1'1, Y=$flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1926_EN[31:0]$1994 [0]
|
| New connections: $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1926_EN[31:0]$1994 [31:1] = { $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1926_EN[31:0]$1994 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1926_EN[31:0]$1994 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1926_EN[31:0]$1994 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1926_EN[31:0]$1994 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1926_EN[31:0]$1994 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1926_EN[31:0]$1994 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1926_EN[31:0]$1994 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/fwpayload/fwrisc/rtl/fwrisc_regfile.sv:95$1926_EN[31:0]$1994 [0] $flatten\u_payload.\u_core.\u_core.\u_core.\u_regfile.$0$memwr$\regs$/project/openlane/user_proj
|
