You can utilize the Makefile existing here in this directory to do that.
But, first you need to specify 3 things:
export OPENLANE_TAG=<the openlane tag/version you are using. This could be rc4 or rc5 based on when you cloned openlane and what branch you are using.> export PDK_ROOT=<The location where the pdk is installed> export OPENLANE_ROOT=<the absolute path to the cloned openlane directory>
NOTE: we recommend using openlane:rc4. Note the following FAQ.
If you don't have openlane already, then you can get it from here. Alternatively, you can clone and build the openlane master through:
NOTE: We are developing caravel using openlane:rc5 which is the current develop branch. openlane:rc5 will be merged to master once the caravel chip is finalized.
Then, you have two options:
Create a macro for your design and harden it, then insert it into user_project_wrapper.
Flatten your design with the user_project_wrapper and harden them as one.
NOTE: The OpenLANE documentation should cover everything you might need to create your design. You can find that here.
This could be done by creating a directory for your design here in this directory, and adding a configuration file for it under the same directory. You can follow the instructions given here to generate an initial configuration file for your design, or you can start with the following:
set script_dir [file dirname [file normalize [info script]]] set ::env(DESIGN_NAME) <Your Design Name> set ::env(DESIGN_IS_CORE) 0 set ::env(FP_PDN_CORE_RING) 0 set ::env(GLB_RT_MAXLAYER) 5 set ::env(VERILOG_FILES) "$script_dir/../../verilog/rtl/<Your RTL.v>" set ::env(CLOCK_PORT) <Clock port name if it exists> set ::env(CLOCK_PERIOD) <Desired clock period>
Then you can add them as you see fit to get the desired DRC/LVS clean outcome.
After that, run the following command:
make <your design directory name>
Then, follow the instructions given in Option 2.
NOTE: You might have other macros inside your design. In which case, you may need to have some special power configurations. This is covered here.
Add your design to the RTL of the user_project_wrapper.
Modify the configuration file here to include any extra files you may need. Make sure to change these accordingly:
set ::env(CLOCK_NET) "mprj.clk" set ::env(VERILOG_FILES) "\ $script_dir/../../verilog/rtl/defines.v \ $script_dir/../../verilog/rtl/user_project_wrapper.v" set ::env(VERILOG_FILES_BLACKBOX) "\ $script_dir/../../verilog/rtl/defines.v \ $script_dir/../../verilog/rtl/user_proj_example.v" set ::env(EXTRA_LEFS) "\ $script_dir/../../lef/user_proj_example.lef" set ::env(EXTRA_GDS_FILES) "\ $script_dir/../../gds/user_proj_example.gds"
NOTE: Don't change the size or the pin order!
Remove this line
add_macro_placement mprj 1150 1700 N from the interactive script here and replace it with the placement for your macro instances. Or, remove it entirely if you have no macros, along with this line
Run your design through the flow:
Re-iterate until you have what you want.
Go back to the main README.md and continue the process of boarding the chip.
NOTE: In both cases you might have other macros inside your design. In which case, you may need to have some special power configurations. This is covered here.