[Docs]: Minor documentation update
diff --git a/README.md b/README.md
index d05d9aa..9679858 100644
@@ -29,14 +29,14 @@
## Aboard Caravel:
-Your area is the full user_project_wrapper, so feel free to add your project there or create a differnt macro and harden it seperately then insert it into the user_project_wrapper.
+Your area is the full user_project_wrapper, so feel free to add your project there or create a differnt macro and harden it seperately then insert it into the user_project_wrapper. For example, if your design is analog or you're using a different tool other than OpenLANE.
If you will use OpenLANE to harden your design, go through the instructions in this [README.md].
-Then, you will need to put your design aboard the Caravel chip. In the Caravel directory, make sure you have the following:
+Then, you will need to put your design aboard the Caravel chip. Make sure you have the following:
- Magic installed on your machine. We may provide a Dockerized version later.
-- You have your user_project_wrapper.gds under `./gds/` directory.
+- You have your user_project_wrapper.gds under `./gds/` in the Caravel directory.
Run the following command:
@@ -45,7 +45,7 @@
-This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`.
+This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`. You should expect hundred of thousands of magic DRC violations with the current "development" state of caravel.
## Managment SoC
The managment SoC runs firmware that can be used to:
diff --git a/openlane/README.md b/openlane/README.md
index a1674fd..7cba65f 100644
@@ -9,6 +9,8 @@
export OPENLANE_ROOT=<the absolute path to the cloned openlane directory>
+**NOTE:** we recommend using openlane:rc4. Note the following [FAQ](https://github.com/efabless/openlane/wiki#why-am-i-getting-n-well-related-drc-violations-from-magic-when-using-the-latest-version-of-the-skywater-pdk).
If you don't have openlane already, then you can get it from [here](https://github.com/efabless/openlane). Alternatively, you can clone and build the openlane master through:
@@ -35,6 +37,7 @@
set ::env(DESIGN_IS_CORE) 0
set ::env(FP_PDN_CORE_RING) 0
+set ::env(GLB_RT_MAXLAYER) 5
set ::env(VERILOG_FILES) "$script_dir/../../verilog/rtl/<Your RTL.v>"
@@ -51,6 +54,8 @@
Then, follow the instructions given in Option 2.
+**NOTE:** You might have other macros inside your design. In which case, you may need to have some special power configurations. This is covered [here](https://github.com/efabless/openlane/blob/develop/doc/hardening_macros.md#power-grid-pdn).
## Option 2:
1. Add your design to the RTL of the [user_project_wrapper](../verilog/rtl/user_project_wrapper.v).
@@ -59,8 +64,6 @@
set ::env(CLOCK_NET) "mprj.clk"
-set ::env(DESIGN_IS_CORE) 0
set ::env(VERILOG_FILES) "\