blob: 3ec0c576391b20da9d901ae58381901304b25429 [file] [log] [blame]
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
1. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/defines.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/DFFRAM.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/DFFRAM.v' to AST representation.
Generating RTLIL representation for module `\DFFRAM'.
Successfully finished Verilog frontend.
3. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/digital_pll.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/digital_pll.v' to AST representation.
Generating RTLIL representation for module `\digital_pll_controller'.
Generating RTLIL representation for module `\delay_stage'.
Generating RTLIL representation for module `\start_stage'.
Generating RTLIL representation for module `\ring_osc2x13'.
Generating RTLIL representation for module `\digital_pll'.
Successfully finished Verilog frontend.
4. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/defines.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.
5. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v' to AST representation.
Generating RTLIL representation for module `\storage_bridge_wb'.
Successfully finished Verilog frontend.
6. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/clock_div.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v' to AST representation.
Generating RTLIL representation for module `\clock_div'.
Generating RTLIL representation for module `\odd'.
Generating RTLIL representation for module `\even'.
Successfully finished Verilog frontend.
7. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v' to AST representation.
Generating RTLIL representation for module `\caravel_clocking'.
Successfully finished Verilog frontend.
8. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v' to AST representation.
Generating RTLIL representation for module `\mgmt_core'.
Successfully finished Verilog frontend.
9. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:192)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:193)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:198)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:162)
Generating RTLIL representation for module `\picorv32'.
Generating RTLIL representation for module `\picorv32_regs'.
Generating RTLIL representation for module `\picorv32_pcpi_mul'.
Generating RTLIL representation for module `\picorv32_pcpi_fast_mul'.
Generating RTLIL representation for module `\picorv32_pcpi_div'.
Generating RTLIL representation for module `\picorv32_axi'.
Generating RTLIL representation for module `\picorv32_axi_adapter'.
Generating RTLIL representation for module `\picorv32_wb'.
Generating RTLIL representation for module `\spimemio_wb'.
Generating RTLIL representation for module `\spimemio'.
Generating RTLIL representation for module `\spimemio_xfer'.
Generating RTLIL representation for module `\simpleuart_wb'.
Generating RTLIL representation for module `\simpleuart'.
Generating RTLIL representation for module `\simple_spi_master_wb'.
Generating RTLIL representation for module `\simple_spi_master'.
Generating RTLIL representation for module `\counter_timer_high_wb'.
Generating RTLIL representation for module `\counter_timer_high'.
Generating RTLIL representation for module `\counter_timer_low_wb'.
Generating RTLIL representation for module `\counter_timer_low'.
Generating RTLIL representation for module `\wb_intercon'.
Generating RTLIL representation for module `\mem_wb'.
Generating RTLIL representation for module `\soc_mem'.
Generating RTLIL representation for module `\gpio_wb'.
Generating RTLIL representation for module `\gpio'.
Generating RTLIL representation for module `\sysctrl_wb'.
Generating RTLIL representation for module `\sysctrl'.
Generating RTLIL representation for module `\la_wb'.
Generating RTLIL representation for module `\la'.
Generating RTLIL representation for module `\mprj_ctrl_wb'.
Generating RTLIL representation for module `\mprj_ctrl'.
Warning: Replacing memory \io_ctrl with list of registers. See /project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:270
Generating RTLIL representation for module `\convert_gpio_sigs'.
Generating RTLIL representation for module `\mgmt_soc'.
Generating RTLIL representation for module `\mgmt_soc_regs'.
Successfully finished Verilog frontend.
10. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:129)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:130)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:131)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:133)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:134)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:135)
Generating RTLIL representation for module `\housekeeping_spi'.
Generating RTLIL representation for module `\housekeeping_spi_slave'.
Successfully finished Verilog frontend.
11. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/mgmt_core/runs/mgmt_core/tmp/synthesis/hierarchy.dot'.
Dumping module mgmt_core to page 1.
12. Executing HIERARCHY pass (managing design hierarchy).
12.1. Analyzing design hierarchy..
Top module: \mgmt_core
Used module: \housekeeping_spi
Used module: \housekeeping_spi_slave
Used module: \mgmt_soc
Used module: \wb_intercon
Used module: \storage_bridge_wb
Used module: \mem_wb
Used module: \soc_mem
Used module: \mprj_ctrl_wb
Used module: \mprj_ctrl
Used module: \la_wb
Used module: \la
Used module: \sysctrl_wb
Used module: \sysctrl
Used module: \gpio_wb
Used module: \gpio
Used module: \counter_timer_high_wb
Used module: \counter_timer_high
Used module: \counter_timer_low_wb
Used module: \counter_timer_low
Used module: \simple_spi_master_wb
Used module: \simple_spi_master
Used module: \simpleuart_wb
Used module: \simpleuart
Used module: \spimemio_wb
Used module: \spimemio
Used module: \spimemio_xfer
Used module: \picorv32_wb
Used module: \picorv32
Used module: \mgmt_soc_regs
Used module: \convert_gpio_sigs
Used module: \caravel_clocking
Used module: \clock_div
Used module: \odd
Used module: \even
Parameter \SIZE = 3
12.2. Executing AST frontend in derive mode using pre-parsed AST for module `\clock_div'.
Parameter \SIZE = 3
Generating RTLIL representation for module `$paramod\clock_div\SIZE=3'.
Parameter \SIZE = 3
Found cached RTLIL representation for module `$paramod\clock_div\SIZE=3'.
Parameter \DW = 32
Parameter \AW = 32
Parameter \NS = 14
Parameter \ADR_MASK = 448'1111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000
Parameter \SLAVE_ADR = 448'0010111100000000000000000000000000101101000000000000000000000000001100000000000000000000000000000010011000000000000000000000000000100101000000000000000000000000001001000000000000000000000000000010001100000000000000000000000000100010000000000000000000000000001000010000000000000000000000000010000000000000000000000000000000010000000000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000000000000000000000000000000
12.3. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_intercon'.
Parameter \DW = 32
Parameter \AW = 32
Parameter \NS = 14
Parameter \ADR_MASK = 448'1111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000
Parameter \SLAVE_ADR = 448'0010111100000000000000000000000000101101000000000000000000000000001100000000000000000000000000000010011000000000000000000000000000100101000000000000000000000000001001000000000000000000000000000010001100000000000000000000000000100010000000000000000000000000001000010000000000000000000000000010000000000000000000000000000000010000000000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000000000000000000000000000000
Generating RTLIL representation for module `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon'.
Parameter \RW_BLOCKS_ADR = 48'000100000000000000000000000000000000000000000000
Parameter \RO_BLOCKS_ADR = 24'000000000000000000000000
12.4. Executing AST frontend in derive mode using pre-parsed AST for module `\storage_bridge_wb'.
Parameter \RW_BLOCKS_ADR = 48'000100000000000000000000000000000000000000000000
Parameter \RO_BLOCKS_ADR = 24'000000000000000000000000
Generating RTLIL representation for module `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb'.
Parameter \BASE_ADR = 637534208
12.5. Executing AST frontend in derive mode using pre-parsed AST for module `\mprj_ctrl_wb'.
Parameter \BASE_ADR = 637534208
Generating RTLIL representation for module `$paramod\mprj_ctrl_wb\BASE_ADR=637534208'.
Parameter \BASE_ADR = 620756992
Parameter \LA_DATA_0 = 8'00000000
Parameter \LA_DATA_1 = 8'00000100
Parameter \LA_DATA_3 = 8'00001100
Parameter \LA_ENA_0 = 8'00010000
Parameter \LA_ENA_1 = 8'00010100
Parameter \LA_ENA_2 = 8'00011000
Parameter \LA_ENA_3 = 8'00011100
12.6. Executing AST frontend in derive mode using pre-parsed AST for module `\la_wb'.
Parameter \BASE_ADR = 620756992
Parameter \LA_DATA_0 = 8'00000000
Parameter \LA_DATA_1 = 8'00000100
Parameter \LA_DATA_3 = 8'00001100
Parameter \LA_ENA_0 = 8'00010000
Parameter \LA_ENA_1 = 8'00010100
Parameter \LA_ENA_2 = 8'00011000
Parameter \LA_ENA_3 = 8'00011100
Generating RTLIL representation for module `$paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb'.
Parameter \BASE_ADR = 788529152
Parameter \PWRGOOD = 8'00000000
Parameter \CLK_OUT = 8'00000100
Parameter \TRAP_OUT = 8'00001000
Parameter \IRQ_SRC = 8'00001100
12.7. Executing AST frontend in derive mode using pre-parsed AST for module `\sysctrl_wb'.
Parameter \BASE_ADR = 788529152
Parameter \PWRGOOD = 8'00000000
Parameter \CLK_OUT = 8'00000100
Parameter \TRAP_OUT = 8'00001000
Parameter \IRQ_SRC = 8'00001100
Generating RTLIL representation for module `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb'.
Parameter \BASE_ADR = 553648128
Parameter \GPIO_DATA = 8'00000000
Parameter \GPIO_ENA = 8'00000100
Parameter \GPIO_PU = 8'00001000
Parameter \GPIO_PD = 8'00001100
12.8. Executing AST frontend in derive mode using pre-parsed AST for module `\gpio_wb'.
Parameter \BASE_ADR = 553648128
Parameter \GPIO_DATA = 8'00000000
Parameter \GPIO_ENA = 8'00000100
Parameter \GPIO_PU = 8'00001000
Parameter \GPIO_PD = 8'00001100
Generating RTLIL representation for module `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb'.
Parameter \BASE_ADR = 587202560
Parameter \CONFIG = 8'00000000
Parameter \VALUE = 8'00000100
Parameter \DATA = 8'00001000
12.9. Executing AST frontend in derive mode using pre-parsed AST for module `\counter_timer_high_wb'.
Parameter \BASE_ADR = 587202560
Parameter \CONFIG = 8'00000000
Parameter \VALUE = 8'00000100
Parameter \DATA = 8'00001000
Generating RTLIL representation for module `$paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb'.
Parameter \BASE_ADR = 570425344
Parameter \CONFIG = 8'00000000
Parameter \VALUE = 8'00000100
Parameter \DATA = 8'00001000
12.10. Executing AST frontend in derive mode using pre-parsed AST for module `\counter_timer_low_wb'.
Parameter \BASE_ADR = 570425344
Parameter \CONFIG = 8'00000000
Parameter \VALUE = 8'00000100
Parameter \DATA = 8'00001000
Generating RTLIL representation for module `$paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb'.
Parameter \BASE_ADR = 603979776
Parameter \CONFIG = 8'00000000
Parameter \DATA = 8'00000100
12.11. Executing AST frontend in derive mode using pre-parsed AST for module `\simple_spi_master_wb'.
Parameter \BASE_ADR = 603979776
Parameter \CONFIG = 8'00000000
Parameter \DATA = 8'00000100
Generating RTLIL representation for module `$paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100'.
Parameter \BASE_ADR = 536870912
Parameter \CLK_DIV = 8'00000000
Parameter \DATA = 8'00000100
12.12. Executing AST frontend in derive mode using pre-parsed AST for module `\simpleuart_wb'.
Parameter \BASE_ADR = 536870912
Parameter \CLK_DIV = 8'00000000
Parameter \DATA = 8'00000100
Generating RTLIL representation for module `$paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100'.
Parameter \BARREL_SHIFTER = 1
Parameter \COMPRESSED_ISA = 1
Parameter \ENABLE_MUL = 1
Parameter \ENABLE_DIV = 1
Parameter \ENABLE_IRQ = 1
Parameter \ENABLE_IRQ_QREGS = 0
Parameter \PROGADDR_RESET = 268435456
Parameter \PROGADDR_IRQ = 0
Parameter \STACKADDR = 1024
12.13. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32_wb'.
Parameter \BARREL_SHIFTER = 1
Parameter \COMPRESSED_ISA = 1
Parameter \ENABLE_MUL = 1
Parameter \ENABLE_DIV = 1
Parameter \ENABLE_IRQ = 1
Parameter \ENABLE_IRQ_QREGS = 0
Parameter \PROGADDR_RESET = 268435456
Parameter \PROGADDR_IRQ = 0
Parameter \STACKADDR = 1024
Generating RTLIL representation for module `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb'.
Parameter \ENABLE_COUNTERS = 1'1
Parameter \ENABLE_COUNTERS64 = 1'1
Parameter \ENABLE_REGS_16_31 = 1'1
Parameter \ENABLE_REGS_DUALPORT = 1'1
Parameter \TWO_STAGE_SHIFT = 1'1
Parameter \BARREL_SHIFTER = 1'0
Parameter \TWO_CYCLE_COMPARE = 1'0
Parameter \TWO_CYCLE_ALU = 1'0
Parameter \COMPRESSED_ISA = 1'0
Parameter \CATCH_MISALIGN = 1'1
Parameter \CATCH_ILLINSN = 1'1
Parameter \ENABLE_PCPI = 1'0
Parameter \ENABLE_MUL = 1'0
Parameter \ENABLE_FAST_MUL = 1'0
Parameter \ENABLE_DIV = 1'0
Parameter \ENABLE_IRQ = 1'0
Parameter \ENABLE_IRQ_QREGS = 1'1
Parameter \ENABLE_IRQ_TIMER = 1'1
Parameter \ENABLE_TRACE = 1'0
Parameter \REGS_INIT_ZERO = 1'0
Parameter \MASKED_IRQ = 0
Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
Parameter \PROGADDR_RESET = 0
Parameter \PROGADDR_IRQ = 16
Parameter \STACKADDR = 32'11111111111111111111111111111111
12.14. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'.
Parameter \ENABLE_COUNTERS = 1'1
Parameter \ENABLE_COUNTERS64 = 1'1
Parameter \ENABLE_REGS_16_31 = 1'1
Parameter \ENABLE_REGS_DUALPORT = 1'1
Parameter \TWO_STAGE_SHIFT = 1'1
Parameter \BARREL_SHIFTER = 1'0
Parameter \TWO_CYCLE_COMPARE = 1'0
Parameter \TWO_CYCLE_ALU = 1'0
Parameter \COMPRESSED_ISA = 1'0
Parameter \CATCH_MISALIGN = 1'1
Parameter \CATCH_ILLINSN = 1'1
Parameter \ENABLE_PCPI = 1'0
Parameter \ENABLE_MUL = 1'0
Parameter \ENABLE_FAST_MUL = 1'0
Parameter \ENABLE_DIV = 1'0
Parameter \ENABLE_IRQ = 1'0
Parameter \ENABLE_IRQ_QREGS = 1'1
Parameter \ENABLE_IRQ_TIMER = 1'1
Parameter \ENABLE_TRACE = 1'0
Parameter \REGS_INIT_ZERO = 1'0
Parameter \MASKED_IRQ = 0
Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
Parameter \PROGADDR_RESET = 0
Parameter \PROGADDR_IRQ = 16
Parameter \STACKADDR = 32'11111111111111111111111111111111
Generating RTLIL representation for module `$paramod$4d2dfdcc1db1a7362453fb449ccdda75bb1b39f9\picorv32'.
Parameter \WORDS = 256
Parameter \ADR_WIDTH = 8
12.15. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_mem'.
Parameter \WORDS = 256
Parameter \ADR_WIDTH = 8
Generating RTLIL representation for module `$paramod\soc_mem\WORDS=256\ADR_WIDTH=8'.
Parameter \BASE_ADR = 553648128
Parameter \GPIO_DATA = 8'00000000
Parameter \GPIO_ENA = 8'00000100
Parameter \GPIO_PU = 8'00001000
Parameter \GPIO_PD = 8'00001100
12.16. Executing AST frontend in derive mode using pre-parsed AST for module `\gpio'.
Parameter \BASE_ADR = 553648128
Parameter \GPIO_DATA = 8'00000000
Parameter \GPIO_ENA = 8'00000100
Parameter \GPIO_PU = 8'00001000
Parameter \GPIO_PD = 8'00001100
Generating RTLIL representation for module `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio'.
Parameter \BASE_ADR = 788529152
Parameter \PWRGOOD = 8'00000000
Parameter \CLK_OUT = 8'00000100
Parameter \TRAP_OUT = 8'00001000
Parameter \IRQ_SRC = 8'00001100
12.17. Executing AST frontend in derive mode using pre-parsed AST for module `\sysctrl'.
Parameter \BASE_ADR = 788529152
Parameter \PWRGOOD = 8'00000000
Parameter \CLK_OUT = 8'00000100
Parameter \TRAP_OUT = 8'00001000
Parameter \IRQ_SRC = 8'00001100
Generating RTLIL representation for module `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl'.
Parameter \BASE_ADR = 570425344
Parameter \LA_DATA_0 = 8'00000000
Parameter \LA_DATA_1 = 8'00000100
Parameter \LA_DATA_2 = 8'00001000
Parameter \LA_DATA_3 = 8'00001100
Parameter \LA_ENA_0 = 8'00010000
Parameter \LA_ENA_1 = 8'00010100
Parameter \LA_ENA_2 = 8'00011000
Parameter \LA_ENA_3 = 8'00011100
12.18. Executing AST frontend in derive mode using pre-parsed AST for module `\la'.
Parameter \BASE_ADR = 570425344
Parameter \LA_DATA_0 = 8'00000000
Parameter \LA_DATA_1 = 8'00000100
Parameter \LA_DATA_2 = 8'00001000
Parameter \LA_DATA_3 = 8'00001100
Parameter \LA_ENA_0 = 8'00010000
Parameter \LA_ENA_1 = 8'00010100
Parameter \LA_ENA_2 = 8'00011000
Parameter \LA_ENA_3 = 8'00011100
Generating RTLIL representation for module `$paramod$499b0a1c054fbe1b70d6dc28b15376e5cd987bff\la'.
Parameter \BASE_ADR = 587202560
Parameter \XFER = 8'00000000
Parameter \PWRDATA = 8'00000100
Parameter \IODATA = 8'00001000
Parameter \IOCONFIG = 8'00100000
12.19. Executing AST frontend in derive mode using pre-parsed AST for module `\mprj_ctrl'.
Parameter \BASE_ADR = 587202560
Parameter \XFER = 8'00000000
Parameter \PWRDATA = 8'00000100
Parameter \IODATA = 8'00001000
Parameter \IOCONFIG = 8'00100000
Generating RTLIL representation for module `$paramod$ed88d8bd975b89882ecfbd510fe3c5e6ac127a6b\mprj_ctrl'.
Warning: Replacing memory \io_ctrl with list of registers. See /project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:270
12.20. Analyzing design hierarchy..
Top module: \mgmt_core
Used module: \housekeeping_spi
Used module: \housekeeping_spi_slave
Used module: \mgmt_soc
Used module: $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon
Used module: $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb
Used module: \mem_wb
Used module: $paramod\soc_mem\WORDS=256\ADR_WIDTH=8
Used module: $paramod\mprj_ctrl_wb\BASE_ADR=637534208
Used module: \mprj_ctrl
Used module: $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb
Used module: \la
Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb
Used module: \sysctrl
Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb
Used module: \gpio
Used module: $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb
Used module: \counter_timer_high
Used module: $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb
Used module: \counter_timer_low
Used module: $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100
Used module: \simple_spi_master
Used module: $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100
Used module: \simpleuart
Used module: \spimemio_wb
Used module: \spimemio
Used module: \spimemio_xfer
Used module: $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb
Used module: \picorv32
Used module: \mgmt_soc_regs
Used module: \convert_gpio_sigs
Used module: \caravel_clocking
Used module: $paramod\clock_div\SIZE=3
Used module: \odd
Used module: \even
Parameter \BASE_ADR = 637534208
Parameter \XFER = 8'00000000
Parameter \PWRDATA = 8'00000100
Parameter \IODATA = 8'00001000
Parameter \IOCONFIG = 8'00100000
12.21. Executing AST frontend in derive mode using pre-parsed AST for module `\mprj_ctrl'.
Parameter \BASE_ADR = 637534208
Parameter \XFER = 8'00000000
Parameter \PWRDATA = 8'00000100
Parameter \IODATA = 8'00001000
Parameter \IOCONFIG = 8'00100000
Generating RTLIL representation for module `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl'.
Warning: Replacing memory \io_ctrl with list of registers. See /project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:270
Parameter \BASE_ADR = 620756992
Parameter \LA_DATA_0 = 8'00000000
Parameter \LA_DATA_1 = 8'00000100
Parameter \LA_DATA_2 = 8'00001000
Parameter \LA_DATA_3 = 8'00001100
Parameter \LA_ENA_0 = 8'00010000
Parameter \LA_ENA_1 = 8'00010100
Parameter \LA_ENA_2 = 8'00011000
Parameter \LA_ENA_3 = 8'00011100
12.22. Executing AST frontend in derive mode using pre-parsed AST for module `\la'.
Parameter \BASE_ADR = 620756992
Parameter \LA_DATA_0 = 8'00000000
Parameter \LA_DATA_1 = 8'00000100
Parameter \LA_DATA_2 = 8'00001000
Parameter \LA_DATA_3 = 8'00001100
Parameter \LA_ENA_0 = 8'00010000
Parameter \LA_ENA_1 = 8'00010100
Parameter \LA_ENA_2 = 8'00011000
Parameter \LA_ENA_3 = 8'00011100
Generating RTLIL representation for module `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la'.
Parameter \BASE_ADR = 788529152
Parameter \PWRGOOD = 8'00000000
Parameter \CLK_OUT = 8'00000100
Parameter \TRAP_OUT = 8'00001000
Parameter \IRQ_SRC = 8'00001100
Found cached RTLIL representation for module `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl'.
Parameter \BASE_ADR = 553648128
Parameter \GPIO_DATA = 8'00000000
Parameter \GPIO_ENA = 8'00000100
Parameter \GPIO_PU = 8'00001000
Parameter \GPIO_PD = 8'00001100
Found cached RTLIL representation for module `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio'.
Parameter \ENABLE_COUNTERS = 1'1
Parameter \ENABLE_COUNTERS64 = 1'1
Parameter \ENABLE_REGS_16_31 = 1'1
Parameter \ENABLE_REGS_DUALPORT = 1'1
Parameter \TWO_STAGE_SHIFT = 1'1
Parameter \BARREL_SHIFTER = 1'1
Parameter \TWO_CYCLE_COMPARE = 1'0
Parameter \TWO_CYCLE_ALU = 1'0
Parameter \COMPRESSED_ISA = 1'1
Parameter \CATCH_MISALIGN = 1'1
Parameter \CATCH_ILLINSN = 1'1
Parameter \ENABLE_PCPI = 1'0
Parameter \ENABLE_MUL = 1'1
Parameter \ENABLE_FAST_MUL = 1'0
Parameter \ENABLE_DIV = 1'1
Parameter \ENABLE_IRQ = 1'1
Parameter \ENABLE_IRQ_QREGS = 1'0
Parameter \ENABLE_IRQ_TIMER = 1'1
Parameter \ENABLE_TRACE = 1'0
Parameter \REGS_INIT_ZERO = 1'0
Parameter \MASKED_IRQ = 0
Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
Parameter \PROGADDR_RESET = 268435456
Parameter \PROGADDR_IRQ = 0
Parameter \STACKADDR = 1024
12.23. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'.
Parameter \ENABLE_COUNTERS = 1'1
Parameter \ENABLE_COUNTERS64 = 1'1
Parameter \ENABLE_REGS_16_31 = 1'1
Parameter \ENABLE_REGS_DUALPORT = 1'1
Parameter \TWO_STAGE_SHIFT = 1'1
Parameter \BARREL_SHIFTER = 1'1
Parameter \TWO_CYCLE_COMPARE = 1'0
Parameter \TWO_CYCLE_ALU = 1'0
Parameter \COMPRESSED_ISA = 1'1
Parameter \CATCH_MISALIGN = 1'1
Parameter \CATCH_ILLINSN = 1'1
Parameter \ENABLE_PCPI = 1'0
Parameter \ENABLE_MUL = 1'1
Parameter \ENABLE_FAST_MUL = 1'0
Parameter \ENABLE_DIV = 1'1
Parameter \ENABLE_IRQ = 1'1
Parameter \ENABLE_IRQ_QREGS = 1'0
Parameter \ENABLE_IRQ_TIMER = 1'1
Parameter \ENABLE_TRACE = 1'0
Parameter \REGS_INIT_ZERO = 1'0
Parameter \MASKED_IRQ = 0
Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
Parameter \PROGADDR_RESET = 268435456
Parameter \PROGADDR_IRQ = 0
Parameter \STACKADDR = 1024
Generating RTLIL representation for module `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32'.
12.24. Analyzing design hierarchy..
Top module: \mgmt_core
Used module: \housekeeping_spi
Used module: \housekeeping_spi_slave
Used module: \mgmt_soc
Used module: $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon
Used module: $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb
Used module: \mem_wb
Used module: $paramod\soc_mem\WORDS=256\ADR_WIDTH=8
Used module: $paramod\mprj_ctrl_wb\BASE_ADR=637534208
Used module: $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl
Used module: $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb
Used module: $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la
Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb
Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl
Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb
Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio
Used module: $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb
Used module: \counter_timer_high
Used module: $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb
Used module: \counter_timer_low
Used module: $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100
Used module: \simple_spi_master
Used module: $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100
Used module: \simpleuart
Used module: \spimemio_wb
Used module: \spimemio
Used module: \spimemio_xfer
Used module: $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb
Used module: $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32
Used module: \picorv32_pcpi_div
Used module: \picorv32_pcpi_mul
Used module: \mgmt_soc_regs
Used module: \convert_gpio_sigs
Used module: \caravel_clocking
Used module: $paramod\clock_div\SIZE=3
Used module: \odd
Used module: \even
12.25. Analyzing design hierarchy..
Top module: \mgmt_core
Used module: \housekeeping_spi
Used module: \housekeeping_spi_slave
Used module: \mgmt_soc
Used module: $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon
Used module: $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb
Used module: \mem_wb
Used module: $paramod\soc_mem\WORDS=256\ADR_WIDTH=8
Used module: $paramod\mprj_ctrl_wb\BASE_ADR=637534208
Used module: $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl
Used module: $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb
Used module: $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la
Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb
Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl
Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb
Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio
Used module: $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb
Used module: \counter_timer_high
Used module: $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb
Used module: \counter_timer_low
Used module: $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100
Used module: \simple_spi_master
Used module: $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100
Used module: \simpleuart
Used module: \spimemio_wb
Used module: \spimemio
Used module: \spimemio_xfer
Used module: $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb
Used module: $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32
Used module: \picorv32_pcpi_div
Used module: \picorv32_pcpi_mul
Used module: \mgmt_soc_regs
Used module: \convert_gpio_sigs
Used module: \caravel_clocking
Used module: $paramod\clock_div\SIZE=3
Used module: \odd
Used module: \even
Removing unused module `$paramod$ed88d8bd975b89882ecfbd510fe3c5e6ac127a6b\mprj_ctrl'.
Removing unused module `$paramod$499b0a1c054fbe1b70d6dc28b15376e5cd987bff\la'.
Removing unused module `$paramod$4d2dfdcc1db1a7362453fb449ccdda75bb1b39f9\picorv32'.
Removing unused module `\mprj_ctrl'.
Removing unused module `\mprj_ctrl_wb'.
Removing unused module `\la'.
Removing unused module `\la_wb'.
Removing unused module `\sysctrl'.
Removing unused module `\sysctrl_wb'.
Removing unused module `\gpio'.
Removing unused module `\gpio_wb'.
Removing unused module `\soc_mem'.
Removing unused module `\wb_intercon'.
Removing unused module `\counter_timer_low_wb'.
Removing unused module `\counter_timer_high_wb'.
Removing unused module `\simple_spi_master_wb'.
Removing unused module `\simpleuart_wb'.
Removing unused module `\picorv32_wb'.
Removing unused module `\picorv32_axi_adapter'.
Removing unused module `\picorv32_axi'.
Removing unused module `\picorv32_pcpi_fast_mul'.
Removing unused module `\picorv32_regs'.
Removing unused module `\picorv32'.
Removing unused module `\clock_div'.
Removing unused module `\storage_bridge_wb'.
Removed 25 unused modules.
Mapping positional arguments of cell $paramod\clock_div\SIZE=3.odd_0 (odd).
Mapping positional arguments of cell $paramod\clock_div\SIZE=3.even_0 (even).
13. Executing SYNTH pass.
13.1. Executing HIERARCHY pass (managing design hierarchy).
13.1.1. Analyzing design hierarchy..
Top module: \mgmt_core
Used module: \housekeeping_spi
Used module: \housekeeping_spi_slave
Used module: \mgmt_soc
Used module: $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon
Used module: $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb
Used module: \mem_wb
Used module: $paramod\soc_mem\WORDS=256\ADR_WIDTH=8
Used module: $paramod\mprj_ctrl_wb\BASE_ADR=637534208
Used module: $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl
Used module: $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb
Used module: $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la
Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb
Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl
Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb
Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio
Used module: $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb
Used module: \counter_timer_high
Used module: $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb
Used module: \counter_timer_low
Used module: $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100
Used module: \simple_spi_master
Used module: $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100
Used module: \simpleuart
Used module: \spimemio_wb
Used module: \spimemio
Used module: \spimemio_xfer
Used module: $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb
Used module: $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32
Used module: \picorv32_pcpi_div
Used module: \picorv32_pcpi_mul
Used module: \mgmt_soc_regs
Used module: \convert_gpio_sigs
Used module: \caravel_clocking
Used module: $paramod\clock_div\SIZE=3
Used module: \odd
Used module: \even
13.1.2. Analyzing design hierarchy..
Top module: \mgmt_core
Used module: \housekeeping_spi
Used module: \housekeeping_spi_slave
Used module: \mgmt_soc
Used module: $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon
Used module: $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb
Used module: \mem_wb
Used module: $paramod\soc_mem\WORDS=256\ADR_WIDTH=8
Used module: $paramod\mprj_ctrl_wb\BASE_ADR=637534208
Used module: $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl
Used module: $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb
Used module: $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la
Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb
Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl
Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb
Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio
Used module: $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb
Used module: \counter_timer_high
Used module: $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb
Used module: \counter_timer_low
Used module: $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100
Used module: \simple_spi_master
Used module: $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100
Used module: \simpleuart
Used module: \spimemio_wb
Used module: \spimemio
Used module: \spimemio_xfer
Used module: $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb
Used module: $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32
Used module: \picorv32_pcpi_div
Used module: \picorv32_pcpi_mul
Used module: \mgmt_soc_regs
Used module: \convert_gpio_sigs
Used module: \caravel_clocking
Used module: $paramod\clock_div\SIZE=3
Used module: \odd
Used module: \even
Removed 0 unused modules.
13.2. Executing PROC pass (convert processes to netlists).
13.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 16 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
Found and cleaned up 1 empty switch in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'.
Found and cleaned up 6 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:546$6993'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:546$6993'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'.
Found and cleaned up 1 empty switch in `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
Cleaned up 62 empty switches.
13.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 41 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 8 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 47 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Removed 2 dead cases from process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 8 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855 in module $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.
Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443 in module $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.
Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433 in module $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 11 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 43 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757 in module $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156 in module mem_wb.
Marked 22 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519 in module counter_timer_low.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509 in module counter_timer_low.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507 in module counter_timer_low.
Marked 17 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458 in module counter_timer_high.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450 in module counter_timer_high.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448 in module counter_timer_high.
Marked 5 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413 in module simple_spi_master.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407 in module simple_spi_master.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401 in module simple_spi_master.
Marked 6 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390 in module simple_spi_master.
Marked 6 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373 in module simple_spi_master.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371 in module simple_spi_master.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326 in module simpleuart.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316 in module simpleuart.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314 in module simpleuart.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268 in module spimemio_xfer.
Marked 5 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244 in module spimemio_xfer.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214 in module spimemio.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146 in module spimemio.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506 in module $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.
Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066 in module picorv32_pcpi_div.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045 in module $paramod\clock_div\SIZE=3.
Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023 in module picorv32_pcpi_mul.
Marked 16 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011 in module housekeeping_spi_slave.
Marked 6 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001 in module housekeeping_spi_slave.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994 in module housekeeping_spi.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263 in module caravel_clocking.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258 in module caravel_clocking.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252 in module even.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244 in module odd.
Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236 in module odd.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230 in module odd.
Removed a total of 2 dead cases.
13.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 24 redundant assignments.
Promoted 263 assignments to connections.
13.2.4. Executing PROC_INIT pass (extract init attributes).
13.2.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \resetn in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
Found async reset \resetn in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
Found async reset \resetn in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'.
Found async reset \resetn in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
Found async reset \resetn in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
Found async reset \resetn in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'.
Found async reset \resetn in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'.
Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'.
Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
Found async reset \resetb in `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'.
Found async reset \csb_reset in `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
Found async reset \csb_reset in `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
Found async reset \RSTB in `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
Found async reset \resetb in `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263'.
Found async reset \resetb in `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
Found async reset \resetb in `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'.
Found async reset \resetb in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244'.
Found async reset \resetb in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
Found async reset \resetb in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'.
13.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
1/86: $23\next_irq_pending[2:2]
2/86: $22\next_irq_pending[2:2]
3/86: $21\next_irq_pending[2:2]
4/86: $20\next_irq_pending[2:2]
5/86: $19\next_irq_pending[2:2]
6/86: $18\next_irq_pending[2:2]
7/86: $17\next_irq_pending[2:2]
8/86: $16\next_irq_pending[0:0]
9/86: $15\next_irq_pending[0:0]
10/86: $14\next_irq_pending[31:0] [0]
11/86: $14\next_irq_pending[31:0] [31:1]
12/86: $2\next_irq_pending[31:0] [31:2]
13/86: $3\set_mem_do_rdata[0:0]
14/86: $2\next_irq_pending[31:0] [1]
15/86: $3\set_mem_do_wdata[0:0]
16/86: $2\next_irq_pending[31:0] [0]
17/86: $4\set_mem_do_rinst[0:0]
18/86: $3\set_mem_do_rinst[0:0]
19/86: $4\set_mem_do_wdata[0:0]
20/86: $12\next_irq_pending[1:1]
21/86: $11\next_irq_pending[1:1]
22/86: $10\next_irq_pending[1:1]
23/86: $4\set_mem_do_rdata[0:0]
24/86: $8\next_irq_pending[1:1]
25/86: $7\next_irq_pending[1:1]
26/86: $6\next_irq_pending[1:1]
27/86: $5\next_irq_pending[1:1]
28/86: $4\next_irq_pending[1:1]
29/86: $13\next_irq_pending[1:1]
30/86: $5\set_mem_do_rinst[0:0]
31/86: $9\next_irq_pending[1:1]
32/86: $3\next_irq_pending[31:0]
33/86: $3\current_pc[31:0]
34/86: $2\current_pc[31:0]
35/86: $2\set_mem_do_wdata[0:0]
36/86: $2\set_mem_do_rdata[0:0]
37/86: $2\set_mem_do_rinst[0:0]
38/86: $1\next_irq_pending[31:0]
39/86: $1\current_pc[31:0]
40/86: $1\set_mem_do_wdata[0:0]
41/86: $1\set_mem_do_rdata[0:0]
42/86: $1\set_mem_do_rinst[0:0]
43/86: $0\trace_data[35:0]
44/86: $0\count_cycle[63:0]
45/86: $0\pcpi_timeout[0:0]
46/86: $0\trace_valid[0:0]
47/86: $0\do_waitirq[0:0]
48/86: $0\decoder_pseudo_trigger[0:0]
49/86: $0\decoder_trigger[0:0]
50/86: $0\alu_wait_2[0:0]
51/86: $0\alu_wait[0:0]
52/86: $0\reg_out[31:0]
53/86: $0\reg_sh[4:0]
54/86: $0\trap[0:0]
55/86: $0\pcpi_timeout_counter[3:0]
56/86: $0\latched_rd[4:0]
57/86: $0\latched_is_lb[0:0]
58/86: $0\latched_is_lh[0:0]
59/86: $0\latched_is_lu[0:0]
60/86: $0\latched_trace[0:0]
61/86: $0\latched_compr[0:0]
62/86: $0\latched_branch[0:0]
63/86: $0\latched_stalu[0:0]
64/86: $0\latched_store[0:0]
65/86: $0\irq_state[1:0]
66/86: $0\cpu_state[7:0]
67/86: $0\dbg_rs2val_valid[0:0]
68/86: $0\dbg_rs1val_valid[0:0]
69/86: $0\dbg_rs2val[31:0]
70/86: $0\dbg_rs1val[31:0]
71/86: $0\mem_do_wdata[0:0]
72/86: $0\mem_do_rdata[0:0]
73/86: $0\mem_do_rinst[0:0]
74/86: $0\mem_do_prefetch[0:0]
75/86: $0\mem_wordsize[1:0]
76/86: $0\timer[31:0]
77/86: $0\irq_mask[31:0]
78/86: $0\irq_active[0:0]
79/86: $0\irq_delay[0:0]
80/86: $0\reg_op2[31:0]
81/86: $0\reg_op1[31:0]
82/86: $0\reg_next_pc[31:0]
83/86: $0\reg_pc[31:0]
84/86: $0\count_instr[63:0]
85/86: $0\eoi[31:0]
86/86: $0\pcpi_valid[0:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'.
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'.
1/4: $2\cpuregs_write[0:0]
2/4: $2\cpuregs_wrdata[31:0]
3/4: $1\cpuregs_wrdata[31:0]
4/4: $1\cpuregs_write[0:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328'.
1/2: $2\clear_prefetched_high_word[0:0]
2/2: $1\clear_prefetched_high_word[0:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1288$7327'.
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'.
1/2: $1\alu_out[31:0]
2/2: $1\alu_out_0[0:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293'.
1/8: $8\dbg_ascii_state[127:0]
2/8: $7\dbg_ascii_state[127:0]
3/8: $6\dbg_ascii_state[127:0]
4/8: $5\dbg_ascii_state[127:0]
5/8: $4\dbg_ascii_state[127:0]
6/8: $3\dbg_ascii_state[127:0]
7/8: $2\dbg_ascii_state[127:0]
8/8: $1\dbg_ascii_state[127:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
1/76: $0\decoded_rs1[4:0] [4]
2/76: $0\decoded_imm_j[31:0] [10]
3/76: $0\decoded_imm_j[31:0] [7]
4/76: $0\decoded_imm_j[31:0] [6]
5/76: $0\decoded_imm_j[31:0] [3:1]
6/76: $0\decoded_imm_j[31:0] [5]
7/76: $0\decoded_imm_j[31:0] [9:8]
8/76: $0\decoded_imm_j[31:0] [31:20]
9/76: $0\decoded_imm_j[31:0] [4]
10/76: $0\decoded_imm_j[31:0] [11]
11/76: $0\decoded_imm_j[31:0] [0]
12/76: $0\decoded_rs1[4:0] [3:0]
13/76: $0\is_lui_auipc_jal_jalr_addi_add_sub[0:0]
14/76: $0\is_alu_reg_reg[0:0]
15/76: $0\is_alu_reg_imm[0:0]
16/76: $0\is_beq_bne_blt_bge_bltu_bgeu[0:0]
17/76: $0\is_sll_srl_sra[0:0]
18/76: $0\is_sb_sh_sw[0:0]
19/76: $0\is_jalr_addi_slti_sltiu_xori_ori_andi[0:0]
20/76: $0\is_slli_srli_srai[0:0]
21/76: $0\is_lb_lh_lw_lbu_lhu[0:0]
22/76: $0\compressed_instr[0:0]
23/76: $0\is_compare[0:0]
24/76: $0\decoded_imm[31:0]
25/76: $0\decoded_rs2[4:0]
26/76: $0\decoded_imm_j[31:0] [19:12]
27/76: $0\decoded_rd[4:0]
28/76: $0\instr_timer[0:0]
29/76: $0\instr_waitirq[0:0]
30/76: $0\instr_maskirq[0:0]
31/76: $0\instr_retirq[0:0]
32/76: $0\instr_setq[0:0]
33/76: $0\instr_getq[0:0]
34/76: $0\instr_ecall_ebreak[0:0]
35/76: $0\instr_rdinstrh[0:0]
36/76: $0\instr_rdinstr[0:0]
37/76: $0\instr_rdcycleh[0:0]
38/76: $0\instr_rdcycle[0:0]
39/76: $0\instr_and[0:0]
40/76: $0\instr_or[0:0]
41/76: $0\instr_sra[0:0]
42/76: $0\instr_srl[0:0]
43/76: $0\instr_xor[0:0]
44/76: $0\instr_sltu[0:0]
45/76: $0\instr_slt[0:0]
46/76: $0\instr_sll[0:0]
47/76: $0\instr_sub[0:0]
48/76: $0\instr_add[0:0]
49/76: $0\instr_srai[0:0]
50/76: $0\instr_srli[0:0]
51/76: $0\instr_slli[0:0]
52/76: $0\instr_andi[0:0]
53/76: $0\instr_ori[0:0]
54/76: $0\instr_xori[0:0]
55/76: $0\instr_sltiu[0:0]
56/76: $0\instr_slti[0:0]
57/76: $0\instr_addi[0:0]
58/76: $0\instr_sw[0:0]
59/76: $0\instr_sh[0:0]
60/76: $0\instr_sb[0:0]
61/76: $0\instr_lhu[0:0]
62/76: $0\instr_lbu[0:0]
63/76: $0\instr_lw[0:0]
64/76: $0\instr_lh[0:0]
65/76: $0\instr_lb[0:0]
66/76: $0\instr_bgeu[0:0]
67/76: $0\instr_bltu[0:0]
68/76: $0\instr_bge[0:0]
69/76: $0\instr_blt[0:0]
70/76: $0\instr_bne[0:0]
71/76: $0\instr_beq[0:0]
72/76: $0\instr_jalr[0:0]
73/76: $0\instr_jal[0:0]
74/76: $0\instr_auipc[0:0]
75/76: $0\instr_lui[0:0]
76/76: $0\pcpi_insn[31:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
1/13: $3\dbg_insn_opcode[31:0]
2/13: $2\dbg_insn_rd[4:0]
3/13: $2\dbg_insn_rs2[4:0]
4/13: $2\dbg_insn_rs1[4:0]
5/13: $2\dbg_insn_opcode[31:0]
6/13: $2\dbg_insn_imm[31:0]
7/13: $2\dbg_ascii_instr[63:0]
8/13: $1\dbg_insn_rd[4:0]
9/13: $1\dbg_insn_rs2[4:0]
10/13: $1\dbg_insn_rs1[4:0]
11/13: $1\dbg_insn_imm[31:0]
12/13: $1\dbg_ascii_instr[63:0]
13/13: $1\dbg_insn_opcode[31:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
1/8: $0\cached_insn_rd[4:0]
2/8: $0\cached_insn_rs2[4:0]
3/8: $0\cached_insn_rs1[4:0]
4/8: $0\cached_insn_opcode[31:0]
5/8: $0\cached_insn_imm[31:0]
6/8: $0\cached_ascii_instr[63:0]
7/8: $0\dbg_valid_insn[0:0]
8/8: $0\dbg_insn_addr[31:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026'.
1/47: $47\new_ascii_instr[63:0]
2/47: $46\new_ascii_instr[63:0]
3/47: $45\new_ascii_instr[63:0]
4/47: $44\new_ascii_instr[63:0]
5/47: $43\new_ascii_instr[63:0]
6/47: $42\new_ascii_instr[63:0]
7/47: $41\new_ascii_instr[63:0]
8/47: $40\new_ascii_instr[63:0]
9/47: $39\new_ascii_instr[63:0]
10/47: $38\new_ascii_instr[63:0]
11/47: $37\new_ascii_instr[63:0]
12/47: $36\new_ascii_instr[63:0]
13/47: $35\new_ascii_instr[63:0]
14/47: $34\new_ascii_instr[63:0]
15/47: $33\new_ascii_instr[63:0]
16/47: $32\new_ascii_instr[63:0]
17/47: $31\new_ascii_instr[63:0]
18/47: $30\new_ascii_instr[63:0]
19/47: $29\new_ascii_instr[63:0]
20/47: $28\new_ascii_instr[63:0]
21/47: $27\new_ascii_instr[63:0]
22/47: $26\new_ascii_instr[63:0]
23/47: $25\new_ascii_instr[63:0]
24/47: $24\new_ascii_instr[63:0]
25/47: $23\new_ascii_instr[63:0]
26/47: $22\new_ascii_instr[63:0]
27/47: $21\new_ascii_instr[63:0]
28/47: $20\new_ascii_instr[63:0]
29/47: $19\new_ascii_instr[63:0]
30/47: $18\new_ascii_instr[63:0]
31/47: $17\new_ascii_instr[63:0]
32/47: $16\new_ascii_instr[63:0]
33/47: $15\new_ascii_instr[63:0]
34/47: $14\new_ascii_instr[63:0]
35/47: $13\new_ascii_instr[63:0]
36/47: $12\new_ascii_instr[63:0]
37/47: $11\new_ascii_instr[63:0]
38/47: $10\new_ascii_instr[63:0]
39/47: $9\new_ascii_instr[63:0]
40/47: $8\new_ascii_instr[63:0]
41/47: $7\new_ascii_instr[63:0]
42/47: $6\new_ascii_instr[63:0]
43/47: $5\new_ascii_instr[63:0]
44/47: $4\new_ascii_instr[63:0]
45/47: $3\new_ascii_instr[63:0]
46/47: $2\new_ascii_instr[63:0]
47/47: $1\new_ascii_instr[63:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
1/9: $0\mem_16bit_buffer[15:0]
2/9: $0\prefetched_high_word[0:0]
3/9: $0\mem_la_secondword[0:0]
4/9: $0\mem_state[1:0]
5/9: $0\mem_wstrb[3:0]
6/9: $0\mem_wdata[31:0]
7/9: $0\mem_addr[31:0]
8/9: $0\mem_instr[0:0]
9/9: $0\mem_valid[0:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'.
1/9: $0\mem_rdata_q[31:0] [31]
2/9: $0\mem_rdata_q[31:0] [7]
3/9: $0\mem_rdata_q[31:0] [24:20]
4/9: $0\mem_rdata_q[31:0] [19:15]
5/9: $0\mem_rdata_q[31:0] [6:0]
6/9: $0\mem_rdata_q[31:0] [14:12]
7/9: $0\mem_rdata_q[31:0] [11:8]
8/9: $0\mem_rdata_q[31:0] [30:25]
9/9: $0\next_insn_opcode[31:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'.
1/5: $3\mem_rdata_word[31:0]
2/5: $2\mem_rdata_word[31:0]
3/5: $1\mem_rdata_word[31:0]
4/5: $1\mem_la_wstrb[3:0]
5/5: $1\mem_la_wdata[31:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'.
1/2: $0\last_mem_valid[0:0]
2/2: $0\mem_la_firstword_reg[0:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
1/2: $1\pcpi_int_rd[31:0]
2/2: $1\pcpi_int_wr[0:0]
Creating decoders for process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
1/34: $0\la_ena_3[31:0] [31:24]
2/34: $0\la_ena_3[31:0] [23:16]
3/34: $0\la_ena_3[31:0] [15:8]
4/34: $0\la_ena_3[31:0] [7:0]
5/34: $0\la_ena_2[31:0] [23:16]
6/34: $0\la_ena_2[31:0] [15:8]
7/34: $0\la_ena_2[31:0] [7:0]
8/34: $0\la_ena_1[31:0] [23:16]
9/34: $0\la_ena_1[31:0] [15:8]
10/34: $0\la_ena_1[31:0] [7:0]
11/34: $0\la_ena_0[31:0] [23:16]
12/34: $0\la_ena_0[31:0] [15:8]
13/34: $0\la_ena_0[31:0] [7:0]
14/34: $0\la_data_3[31:0] [23:16]
15/34: $0\la_data_3[31:0] [15:8]
16/34: $0\la_data_3[31:0] [7:0]
17/34: $0\la_data_2[31:0] [23:16]
18/34: $0\la_data_2[31:0] [15:8]
19/34: $0\la_data_2[31:0] [7:0]
20/34: $0\la_data_1[31:0] [23:16]
21/34: $0\la_data_1[31:0] [15:8]
22/34: $0\la_data_1[31:0] [7:0]
23/34: $0\la_data_0[31:0] [23:16]
24/34: $0\la_data_0[31:0] [15:8]
25/34: $0\la_data_0[31:0] [7:0]
26/34: $0\la_ena_1[31:0] [31:24]
27/34: $0\la_ena_0[31:0] [31:24]
28/34: $0\la_data_3[31:0] [31:24]
29/34: $0\la_data_2[31:0] [31:24]
30/34: $0\la_data_1[31:0] [31:24]
31/34: $0\la_data_0[31:0] [31:24]
32/34: $0\la_ena_2[31:0] [31:24]
33/34: $0\iomem_ready[0:0]
34/34: $0\iomem_rdata[31:0]
Creating decoders for process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
1/7: $0\irq_8_inputsrc[0:0]
2/7: $0\irq_7_inputsrc[0:0]
3/7: $0\trap_output_dest[0:0]
4/7: $0\clk2_output_dest[0:0]
5/7: $0\clk1_output_dest[0:0]
6/7: $0\iomem_ready[0:0]
7/7: $0\iomem_rdata[31:0]
Creating decoders for process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
1/6: $0\iomem_ready[0:0]
2/6: $0\iomem_rdata[31:0]
3/6: $0\gpio_pd[0:0]
4/6: $0\gpio_pu[0:0]
5/6: $0\gpio_oeb[0:0]
6/6: $0\gpio[0:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'.
1/1: $0\io_ctrl[37][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'.
1/1: $0\io_ctrl[36][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'.
1/1: $0\io_ctrl[35][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'.
1/1: $0\io_ctrl[34][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'.
1/1: $0\io_ctrl[33][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'.
1/1: $0\io_ctrl[32][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'.
1/1: $0\io_ctrl[31][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'.
1/1: $0\io_ctrl[30][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'.
1/1: $0\io_ctrl[29][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'.
1/1: $0\io_ctrl[28][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'.
1/1: $0\io_ctrl[27][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'.
1/1: $0\io_ctrl[26][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'.
1/1: $0\io_ctrl[25][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'.
1/1: $0\io_ctrl[24][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'.
1/1: $0\io_ctrl[23][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'.
1/1: $0\io_ctrl[22][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'.
1/1: $0\io_ctrl[21][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'.
1/1: $0\io_ctrl[20][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'.
1/1: $0\io_ctrl[19][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'.
1/1: $0\io_ctrl[18][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'.
1/1: $0\io_ctrl[17][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'.
1/1: $0\io_ctrl[16][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'.
1/1: $0\io_ctrl[15][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'.
1/1: $0\io_ctrl[14][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'.
1/1: $0\io_ctrl[13][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'.
1/1: $0\io_ctrl[12][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'.
1/1: $0\io_ctrl[11][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'.
1/1: $0\io_ctrl[10][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'.
1/1: $0\io_ctrl[9][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'.
1/1: $0\io_ctrl[8][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'.
1/1: $0\io_ctrl[7][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'.
1/1: $0\io_ctrl[6][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'.
1/1: $0\io_ctrl[5][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'.
1/1: $0\io_ctrl[4][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'.
1/1: $0\io_ctrl[3][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'.
1/1: $0\io_ctrl[2][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'.
1/1: $0\io_ctrl[1][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'.
1/1: $0\io_ctrl[0][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612'.
1/1: $0\mgmt_gpio_outr[37:32]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606'.
1/1: $0\mgmt_gpio_outr[31:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6602'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6597'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6592'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6587'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6582'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6577'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6572'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6567'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6562'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6557'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6552'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6547'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6542'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6537'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6532'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6527'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6522'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6517'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6512'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6507'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6502'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6497'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6492'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6487'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6482'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6477'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6472'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6467'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6462'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6457'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6452'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6447'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6442'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6437'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6432'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6427'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6422'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6417'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6412'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6410'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
1/13: $4$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA[12:0]$6397
2/13: $3$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA[12:0]$6394
3/13: $3$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_ADDR[5:0]$6393
4/13: $2$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA[12:0]$6390
5/13: $2$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_ADDR[5:0]$6389
6/13: $1$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA[12:0]$6387
7/13: $1$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_ADDR[5:0]$6386
8/13: $0\serial_data_staging[12:0]
9/13: $0\xfer_state[1:0]
10/13: $0\pad_count[5:0]
11/13: $0\xfer_count[3:0]
12/13: $0\serial_resetn[0:0]
13/13: $0\serial_clock[0:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'.
1/2: $0\xfer_ctrl[0:0]
2/2: $0\pwr_ctrl_out[3:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'.
1/2: $0\iomem_ready[0:0]
2/2: $0\iomem_rdata[31:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367'.
1/46: $43\iomem_rdata_pre[31:0]
2/46: $42\iomem_rdata_pre[31:0]
3/46: $41\iomem_rdata_pre[31:0]
4/46: $40\iomem_rdata_pre[31:0]
5/46: $39\iomem_rdata_pre[31:0]
6/46: $38\iomem_rdata_pre[31:0]
7/46: $37\iomem_rdata_pre[31:0]
8/46: $36\iomem_rdata_pre[31:0]
9/46: $35\iomem_rdata_pre[31:0]
10/46: $34\iomem_rdata_pre[31:0]
11/46: $33\iomem_rdata_pre[31:0]
12/46: $32\iomem_rdata_pre[31:0]
13/46: $31\iomem_rdata_pre[31:0]
14/46: $30\iomem_rdata_pre[31:0]
15/46: $29\iomem_rdata_pre[31:0]
16/46: $28\iomem_rdata_pre[31:0]
17/46: $27\iomem_rdata_pre[31:0]
18/46: $26\iomem_rdata_pre[31:0]
19/46: $25\iomem_rdata_pre[31:0]
20/46: $24\iomem_rdata_pre[31:0]
21/46: $23\iomem_rdata_pre[31:0]
22/46: $22\iomem_rdata_pre[31:0]
23/46: $21\iomem_rdata_pre[31:0]
24/46: $20\iomem_rdata_pre[31:0]
25/46: $19\iomem_rdata_pre[31:0]
26/46: $18\iomem_rdata_pre[31:0]
27/46: $17\iomem_rdata_pre[31:0]
28/46: $16\iomem_rdata_pre[31:0]
29/46: $15\iomem_rdata_pre[31:0]
30/46: $14\iomem_rdata_pre[31:0]
31/46: $13\iomem_rdata_pre[31:0]
32/46: $12\iomem_rdata_pre[31:0]
33/46: $11\iomem_rdata_pre[31:0]
34/46: $10\iomem_rdata_pre[31:0]
35/46: $9\iomem_rdata_pre[31:0]
36/46: $8\iomem_rdata_pre[31:0]
37/46: $7\iomem_rdata_pre[31:0]
38/46: $6\iomem_rdata_pre[31:0]
39/46: $5\iomem_rdata_pre[31:0]
40/46: $4\iomem_rdata_pre[31:0]
41/46: $3\j[31:0]
42/46: $3\iomem_rdata_pre[31:0]
43/46: $2\iomem_rdata_pre[31:0]
44/46: $2\j[31:0]
45/46: $1\iomem_rdata_pre[31:0]
46/46: $1\j[31:0]
Creating decoders for process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
1/9: $0\state[1:0]
2/9: $0\wbm_cyc_o[0:0]
3/9: $0\wbm_stb_o[0:0]
4/9: $0\wbm_sel_o[3:0]
5/9: $0\wbm_we_o[0:0]
6/9: $0\wbm_dat_o[31:0]
7/9: $0\wbm_adr_o[31:0]
8/9: $0\mem_rdata[31:0]
9/9: $0\mem_ready[0:0]
Creating decoders for process `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'.
1/2: $0\wb_ack_o[0:0]
2/2: $0\wb_ack_read[0:0]
Creating decoders for process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
1/8: $0\value_cur[31:0] [31:24]
2/8: $0\value_cur[31:0] [7:0]
3/8: $0\value_cur[31:0] [15:8]
4/8: $0\value_cur[31:0] [23:16]
5/8: $0\lastenable[0:0]
6/8: $0\stop_out[0:0]
7/8: $0\strobe[0:0]
8/8: $0\irq_out[0:0]
Creating decoders for process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'.
1/4: $0\value_reset[31:0] [15:8]
2/4: $0\value_reset[31:0] [7:0]
3/4: $0\value_reset[31:0] [23:16]
4/4: $0\value_reset[31:0] [31:24]
Creating decoders for process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
1/5: $0\chain[0:0]
2/5: $0\irq_ena[0:0]
3/5: $0\updown[0:0]
4/5: $0\oneshot[0:0]
5/5: $0\enable[0:0]
Creating decoders for process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
1/7: $0\value_cur[31:0] [31:24]
2/7: $0\value_cur[31:0] [23:16]
3/7: $0\value_cur[31:0] [7:0]
4/7: $0\value_cur[31:0] [15:8]
5/7: $0\lastenable[0:0]
6/7: $0\stop_out[0:0]
7/7: $0\irq_out[0:0]
Creating decoders for process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'.
1/4: $0\value_reset[31:0] [15:8]
2/4: $0\value_reset[31:0] [7:0]
3/4: $0\value_reset[31:0] [23:16]
4/4: $0\value_reset[31:0] [31:24]
Creating decoders for process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
1/5: $0\chain[0:0]
2/5: $0\irq_ena[0:0]
3/5: $0\updown[0:0]
4/5: $0\oneshot[0:0]
5/5: $0\enable[0:0]
Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
1/3: $0\rreg[7:0]
2/3: $0\treg[7:0]
3/3: $0\isdo[0:0]
Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'.
1/1: $0\isck[0:0]
Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'.
1/2: $0\count[7:0]
2/2: $0\hsck[0:0]
Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
1/4: $0\nbit[2:0]
2/4: $0\icsb[0:0]
3/4: $0\done[0:0]
4/4: $0\state[1:0]
Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
1/4: $0\r_latched[0:0]
2/4: $0\w_latched[0:0]
3/4: $0\d_latched[7:0]
4/4: $0\err_out[0:0]
Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
1/9: $0\hkconn[0:0]
2/9: $0\mode[0:0]
3/9: $0\stream[0:0]
4/9: $0\irqena[0:0]
5/9: $0\mlb[0:0]
6/9: $0\invcsb[0:0]
7/9: $0\invsck[0:0]
8/9: $0\prescaler[7:0]
9/9: $0\enable[0:0]
Creating decoders for process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
1/4: $0\send_divcnt[31:0]
2/4: $0\send_dummy[0:0]
3/4: $0\send_bitcnt[3:0]
4/4: $0\send_pattern[9:0]
Creating decoders for process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
1/5: $0\recv_divcnt[31:0]
2/5: $0\recv_buf_valid[0:0]
3/5: $0\recv_buf_data[7:0]
4/5: $0\recv_pattern[7:0]
5/5: $0\recv_state[3:0]
Creating decoders for process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'.
1/5: $0\cfg_divider[31:0] [31:24]
2/5: $0\cfg_divider[31:0] [23:16]
3/5: $0\cfg_divider[31:0] [15:8]
4/5: $0\cfg_divider[31:0] [7:0]
5/5: $0\enabled[0:0]
Creating decoders for process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
1/14: $0\last_fetch[0:0]
2/14: $0\fetch[0:0]
3/14: $0\xfer_tag[3:0]
4/14: $0\xfer_rd[0:0]
5/14: $0\xfer_qspi[0:0]
6/14: $0\xfer_cont[0:0]
7/14: $0\dummy_count[3:0]
8/14: $0\count[3:0]
9/14: $0\ibuffer[7:0]
10/14: $0\obuffer[7:0]
11/14: $0\xfer_ddr[0:0]
12/14: $0\xfer_dspi[0:0]
13/14: $0\flash_clk[0:0]
14/14: $0\flash_csb[0:0]
Creating decoders for process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
1/33: $5\next_count[3:0]
2/33: $5\next_obuffer[7:0]
3/33: $5\next_ibuffer[7:0]
4/33: $4\next_count[3:0]
5/33: $4\next_obuffer[7:0]
6/33: $4\next_ibuffer[7:0]
7/33: $3\next_count[3:0]
8/33: $3\next_obuffer[7:0]
9/33: $3\next_ibuffer[7:0]
10/33: $2\next_fetch[0:0]
11/33: $2\next_count[3:0]
12/33: $2\next_ibuffer[7:0]
13/33: $2\next_obuffer[7:0]
14/33: $2\flash_io0_do[0:0]
15/33: $2\flash_io0_oe[0:0]
16/33: $2\flash_io3_oe[0:0]
17/33: $2\flash_io2_oe[0:0]
18/33: $2\flash_io1_oe[0:0]
19/33: $2\flash_io3_do[0:0]
20/33: $2\flash_io2_do[0:0]
21/33: $2\flash_io1_do[0:0]
22/33: $1\next_fetch[0:0]
23/33: $1\next_count[3:0]
24/33: $1\next_ibuffer[7:0]
25/33: $1\next_obuffer[7:0]
26/33: $1\flash_io3_oe[0:0]
27/33: $1\flash_io2_oe[0:0]
28/33: $1\flash_io1_oe[0:0]
29/33: $1\flash_io0_oe[0:0]
30/33: $1\flash_io3_do[0:0]
31/33: $1\flash_io2_do[0:0]
32/33: $1\flash_io1_do[0:0]
33/33: $1\flash_io0_do[0:0]
Creating decoders for process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:598$1235'.
Creating decoders for process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
1/17: $0\buffer[23:0] [23:16]
2/17: $0\buffer[23:0] [15:8]
3/17: $0\buffer[23:0] [7:0]
4/17: $0\xfer_resetn[0:0]
5/17: $0\rd_inc[0:0]
6/17: $0\rd_wait[0:0]
7/17: $0\rd_valid[0:0]
8/17: $0\rd_addr[23:0]
9/17: $0\din_valid[0:0]
10/17: $0\din_rd[0:0]
11/17: $0\din_ddr[0:0]
12/17: $0\din_qspi[0:0]
13/17: $0\din_cont[0:0]
14/17: $0\din_tag[3:0]
15/17: $0\din_data[7:0]
16/17: $0\rdata[31:0]
17/17: $0\state[3:0]
Creating decoders for process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'.
Creating decoders for process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
1/10: $0\softreset[0:0]
2/10: $0\config_do[3:0]
3/10: $0\config_clk[0:0]
4/10: $0\config_csb[0:0]
5/10: $0\config_oe[3:0]
6/10: $0\config_dummy[3:0]
7/10: $0\config_cont[0:0]
8/10: $0\config_qspi[0:0]
9/10: $0\config_ddr[0:0]
10/10: $0\config_en[0:0]
Creating decoders for process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:84$4518'.
Creating decoders for process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'.
1/2: $0\wb_ack_o[1:0]
2/2: $0\wb_ack_read[1:0]
Creating decoders for process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:52$3512'.
Creating decoders for process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
1/9: $0\pcpi_rd[31:0]
2/9: $0\pcpi_wr[0:0]
3/9: $0\pcpi_ready[0:0]
4/9: $0\outsign[0:0]
5/9: $0\running[0:0]
6/9: $0\quotient_msk[31:0]
7/9: $0\quotient[31:0]
8/9: $0\divisor[62:0]
9/9: $0\dividend[31:0]
Creating decoders for process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
1/4: $0\instr_remu[0:0]
2/4: $0\instr_rem[0:0]
3/4: $0\instr_divu[0:0]
4/4: $0\instr_div[0:0]
Creating decoders for process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'.
1/2: $0\syncN[2:0]
2/2: $0\syncNp[2:0]
Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'.
1/3: $0\pcpi_ready[0:0]
2/3: $0\pcpi_wr[0:0]
3/3: $0\pcpi_rd[31:0]
Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
1/7: $0\mul_finish[0:0]
2/7: $0\mul_waiting[0:0]
3/7: $0\mul_counter[6:0]
4/7: $0\rdx[63:0]
5/7: $0\rd[63:0]
6/7: $0\rs2[63:0]
7/7: $0\rs1[63:0]
Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
1/4: $0\instr_mulhu[0:0]
2/4: $0\instr_mulhsu[0:0]
3/4: $0\instr_mulh[0:0]
4/4: $0\instr_mul[0:0]
Creating decoders for process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
1/14: $1\pass_thru_user[0:0]
2/14: $0\pre_pass_thru_user[0:0]
3/14: $0\pre_pass_thru_mgmt[0:0]
4/14: $0\predata[6:0]
5/14: $0\fixed[2:0]
6/14: $0\readmode[0:0]
7/14: $0\writemode[0:0]
8/14: $0\pass_thru_user_delay[0:0]
9/14: $0\pass_thru_mgmt_delay[0:0]
10/14: $0\rdstb[0:0]
11/14: $0\count[2:0]
12/14: $0\addr[7:0]
13/14: $0\state[2:0]
14/14: $0\pass_thru_mgmt[0:0]
Creating decoders for process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
1/3: $0\sdoenb[0:0]
2/3: $0\ldata[7:0]
3/3: $0\wrstb[0:0]
Creating decoders for process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
1/12: $0\pll_trim[25:0] [25:24]
2/12: $0\pll_trim[25:0] [23:16]
3/12: $0\pll_trim[25:0] [15:8]
4/12: $0\pll_trim[25:0] [7:0]
5/12: $0\irq[0:0]
6/12: $0\pll_bypass[0:0]
7/12: $0\reset_reg[0:0]
8/12: $0\pll_ena[0:0]
9/12: $0\pll_div[4:0]
10/12: $0\pll90_sel[2:0]
11/12: $0\pll_sel[2:0]
12/12: $0\pll_dco_ena[0:0]
Creating decoders for process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263'.
1/1: $0\reset_delay[2:0]
Creating decoders for process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
1/4: $0\ext_clk_syncd[0:0]
2/4: $0\use_pll_second[0:0]
3/4: $0\use_pll_first[0:0]
4/4: $0\ext_clk_syncd_pre[0:0]
Creating decoders for process `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'.
1/2: $0\out_counter[0:0]
2/2: $0\counter[2:0]
Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:146$247'.
Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244'.
1/1: $0\rst_pulse[0:0]
Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
1/3: $0\initial_begin[2:0]
2/3: $0\out_counter2[0:0]
3/3: $0\counter2[2:0]
Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'.
1/2: $0\out_counter[0:0]
2/2: $0\counter[2:0]
Creating decoders for process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'.
1/3: $0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936
2/3: $0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_DATA[31:0]$2935
3/3: $0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_ADDR[4:0]$2934
Creating decoders for process `\mgmt_soc.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:333$2926'.
13.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_rs1' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_rs2' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rs' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_write' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_wrdata' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\clear_prefetched_high_word' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out_0' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_ascii_state' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_opcode' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_ascii_instr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_imm' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_rs1' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_rs2' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_rd' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\new_ascii_instr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_add_sub' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_shl' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_shr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_eq' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_ltu' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_lts' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_wdata' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_wstrb' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_rdata_word' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_wr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_rd' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_wait' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_ready' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_data_arr[0]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_data_arr[1]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[0]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[1]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[2]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[3]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[4]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[5]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[6]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[7]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[8]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[9]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[10]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[11]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[12]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[13]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[14]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[15]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[16]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[17]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[18]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[19]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[20]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[21]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[22]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[23]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[24]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[25]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[26]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[27]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[28]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[29]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[30]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[31]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[32]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[33]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[34]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[35]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[36]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[37]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6238' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6602'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6236' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6597'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6234' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6592'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6232' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6587'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6230' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6582'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6228' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6577'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6226' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6572'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6224' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6567'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6222' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6562'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6220' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6557'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6218' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6552'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6216' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6547'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6214' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6542'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6212' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6537'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6210' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6532'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6208' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6527'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6206' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6522'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6204' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6517'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6202' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6512'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6200' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6507'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6198' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6502'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6196' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6497'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6194' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6492'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6192' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6487'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6190' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6482'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6188' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6477'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6186' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6472'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6184' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6467'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6182' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6462'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6180' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6457'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6178' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6452'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6176' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6447'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6174' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6442'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6172' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6437'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6170' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6432'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6168' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6427'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6166' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6422'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6164' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6417'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:141$6160' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6412'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:140$6159' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6410'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\iomem_rdata_pre' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367'.
Latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\j' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367': $auto$proc_dlatch.cc:430:proc_dlatch$14650
No latch inferred for signal `\spimemio_xfer.\flash_io0_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io1_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io2_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io3_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io0_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io1_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io2_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io3_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\next_obuffer' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\next_ibuffer' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\next_count' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\next_fetch' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.\wb_rw_dat_o' from process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:84$4518'.
No latch inferred for signal `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.\i' from process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:84$4518'.
No latch inferred for signal `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.\i' from process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:52$3512'.
No latch inferred for signal `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.\wbm_dat_o' from process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:52$3512'.
No latch inferred for signal `\picorv32_pcpi_mul.\i' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\next_rs1' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\next_rs2' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\this_rs2' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\next_rd' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\next_rdx' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\next_rdt' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\j' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\mgmt_soc.\irq' from process `\mgmt_soc.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:333$2926'.
13.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\trap' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14651' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14652' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\eoi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14653' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\trace_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14654' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\trace_data' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14655' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\count_cycle' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14656' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\count_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14657' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_pc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14658' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_next_pc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14659' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_op1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14660' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_op2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14661' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_out' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14662' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_sh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14663' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_delay' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14664' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_active' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14665' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_mask' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14666' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_pending' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14667' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\timer' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14668' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_wordsize' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14669' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_prefetch' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14670' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_rinst' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14671' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_rdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14672' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_wdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14673' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_trigger' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14674' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_trigger_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14675' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_pseudo_trigger' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14676' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_pseudo_trigger_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14677' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs1val' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14678' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs2val' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14679' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs1val_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14680' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs2val_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14681' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpu_state' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14682' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_state' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14683' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\set_mem_do_rinst' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14684' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\set_mem_do_rdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14685' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\set_mem_do_wdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14686' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_store' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14687' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_stalu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14688' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_branch' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14689' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_compr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14690' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_trace' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14691' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_is_lu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14692' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_is_lh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14693' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_is_lb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14694' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14695' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\current_pc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14696' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_timeout_counter' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14697' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_timeout' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14698' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\next_irq_pending' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14699' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\do_waitirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14700' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14701' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out_0_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14702' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_wait' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14703' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_wait_2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
created $dff cell `$procdff$14704' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\clear_prefetched_high_word_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1288$7327'.
created $dff cell `$procdff$14705' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_insn' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14706' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lui' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14707' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_auipc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14708' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_jal' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14709' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_jalr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14710' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_beq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14711' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bne' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14712' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_blt' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14713' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bge' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14714' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bltu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14715' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bgeu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14716' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14717' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14718' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14719' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lbu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14720' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lhu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14721' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14722' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14723' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14724' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_addi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14725' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_slti' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14726' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sltiu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14727' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_xori' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14728' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_ori' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14729' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_andi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14730' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_slli' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14731' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_srli' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14732' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_srai' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14733' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_add' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14734' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sub' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14735' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sll' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14736' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_slt' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14737' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sltu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14738' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_xor' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14739' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_srl' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14740' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sra' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14741' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_or' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14742' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_and' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14743' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdcycle' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14744' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdcycleh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14745' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdinstr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14746' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdinstrh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14747' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_ecall_ebreak' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14748' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_getq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14749' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_setq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14750' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_retirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14751' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_maskirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14752' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_waitirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14753' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_timer' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14754' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14755' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rs1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14756' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rs2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14757' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14758' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_imm_j' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14759' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\compressed_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14760' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lui_auipc_jal' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14761' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lb_lh_lw_lbu_lhu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14762' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_slli_srli_srai' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14763' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_jalr_addi_slti_sltiu_xori_ori_andi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14764' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_sb_sh_sw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14765' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_sll_srl_sra' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14766' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lui_auipc_jal_jalr_addi_add_sub' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14767' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_slti_blt_slt' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14768' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_sltiu_bltu_sltu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14769' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_beq_bne_blt_bge_bltu_bgeu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14770' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lbu_lhu_lw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14771' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_alu_reg_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14772' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_alu_reg_reg' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14773' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_compare' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
created $dff cell `$procdff$14774' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_addr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
created $dff cell `$procdff$14775' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_ascii_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
created $dff cell `$procdff$14776' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
created $dff cell `$procdff$14777' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_opcode' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
created $dff cell `$procdff$14778' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_rs1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
created $dff cell `$procdff$14779' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_rs2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
created $dff cell `$procdff$14780' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
created $dff cell `$procdff$14781' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_next' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
created $dff cell `$procdff$14782' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_valid_insn' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
created $dff cell `$procdff$14783' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_ascii_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
created $dff cell `$procdff$14784' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
created $dff cell `$procdff$14785' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_opcode' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
created $dff cell `$procdff$14786' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_rs1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
created $dff cell `$procdff$14787' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_rs2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
created $dff cell `$procdff$14788' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
created $dff cell `$procdff$14789' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
created $dff cell `$procdff$14790' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
created $dff cell `$procdff$14791' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_addr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
created $dff cell `$procdff$14792' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_wdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
created $dff cell `$procdff$14793' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_wstrb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
created $dff cell `$procdff$14794' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_state' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
created $dff cell `$procdff$14795' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_secondword' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
created $dff cell `$procdff$14796' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\prefetched_high_word' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
created $dff cell `$procdff$14797' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_16bit_buffer' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
created $dff cell `$procdff$14798' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\next_insn_opcode' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'.
created $dff cell `$procdff$14799' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_rdata_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'.
created $dff cell `$procdff$14800' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_firstword_reg' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'.
created $dff cell `$procdff$14801' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\last_mem_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'.
created $dff cell `$procdff$14802' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\iomem_rdata' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
created $dff cell `$procdff$14803' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\iomem_ready' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
created $dff cell `$procdff$14804' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_0' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
created $dff cell `$procdff$14805' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_1' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
created $dff cell `$procdff$14806' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_2' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
created $dff cell `$procdff$14807' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_3' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
created $dff cell `$procdff$14808' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_0' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
created $dff cell `$procdff$14809' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_1' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
created $dff cell `$procdff$14810' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_2' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
created $dff cell `$procdff$14811' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_3' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
created $dff cell `$procdff$14812' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\iomem_rdata' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
created $dff cell `$procdff$14813' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\iomem_ready' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
created $dff cell `$procdff$14814' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\clk1_output_dest' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
created $dff cell `$procdff$14815' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\clk2_output_dest' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
created $dff cell `$procdff$14816' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\trap_output_dest' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
created $dff cell `$procdff$14817' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\irq_7_inputsrc' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
created $dff cell `$procdff$14818' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\irq_8_inputsrc' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
created $dff cell `$procdff$14819' with positive edge clock.
Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
created $dff cell `$procdff$14820' with positive edge clock.
Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio_oeb' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
created $dff cell `$procdff$14821' with positive edge clock.
Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio_pu' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
created $dff cell `$procdff$14822' with positive edge clock.
Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio_pd' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
created $dff cell `$procdff$14823' with positive edge clock.
Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\iomem_rdata' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
created $dff cell `$procdff$14824' with positive edge clock.
Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\iomem_ready' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
created $dff cell `$procdff$14825' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[37]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'.
created $dff cell `$procdff$14826' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[36]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'.
created $dff cell `$procdff$14827' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[35]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'.
created $dff cell `$procdff$14828' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[34]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'.
created $dff cell `$procdff$14829' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[33]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'.
created $dff cell `$procdff$14830' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[32]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'.
created $dff cell `$procdff$14831' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[31]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'.
created $dff cell `$procdff$14832' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[30]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'.
created $dff cell `$procdff$14833' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[29]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'.
created $dff cell `$procdff$14834' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[28]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'.
created $dff cell `$procdff$14835' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[27]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'.
created $dff cell `$procdff$14836' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[26]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'.
created $dff cell `$procdff$14837' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[25]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'.
created $dff cell `$procdff$14838' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[24]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'.
created $dff cell `$procdff$14839' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[23]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'.
created $dff cell `$procdff$14840' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[22]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'.
created $dff cell `$procdff$14841' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[21]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'.
created $dff cell `$procdff$14842' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[20]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'.
created $dff cell `$procdff$14843' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[19]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'.
created $dff cell `$procdff$14844' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[18]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'.
created $dff cell `$procdff$14845' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[17]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'.
created $dff cell `$procdff$14846' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[16]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'.
created $dff cell `$procdff$14847' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[15]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'.
created $dff cell `$procdff$14848' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[14]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'.
created $dff cell `$procdff$14849' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[13]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'.
created $dff cell `$procdff$14850' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[12]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'.
created $dff cell `$procdff$14851' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[11]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'.
created $dff cell `$procdff$14852' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[10]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'.
created $dff cell `$procdff$14853' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[9]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'.
created $dff cell `$procdff$14854' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[8]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'.
created $dff cell `$procdff$14855' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[7]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'.
created $dff cell `$procdff$14856' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[6]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'.
created $dff cell `$procdff$14857' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[5]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'.
created $dff cell `$procdff$14858' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[4]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'.
created $dff cell `$procdff$14859' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[3]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'.
created $dff cell `$procdff$14860' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[2]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'.
created $dff cell `$procdff$14861' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[1]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'.
created $dff cell `$procdff$14862' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[0]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'.
created $dff cell `$procdff$14863' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\mgmt_gpio_outr [37:32]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612'.
created $dff cell `$procdff$14864' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\mgmt_gpio_outr [31:0]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606'.
created $dff cell `$procdff$14865' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\serial_clock' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
created $adff cell `$procdff$14866' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\serial_resetn' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
created $adff cell `$procdff$14867' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\xfer_count' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
created $adff cell `$procdff$14868' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\pad_count' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
created $adff cell `$procdff$14869' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\xfer_state' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
created $adff cell `$procdff$14870' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\serial_data_staging' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
created $dff cell `$procdff$14871' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_ADDR' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
created $adff cell `$procdff$14872' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
created $adff cell `$procdff$14873' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\pwr_ctrl_out' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'.
created $dff cell `$procdff$14874' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\xfer_ctrl' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'.
created $dff cell `$procdff$14875' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\iomem_rdata' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'.
created $dff cell `$procdff$14876' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\iomem_ready' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'.
created $dff cell `$procdff$14877' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\mem_ready' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
created $dff cell `$procdff$14878' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\mem_rdata' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
created $dff cell `$procdff$14879' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_adr_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
created $dff cell `$procdff$14880' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_dat_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
created $dff cell `$procdff$14881' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_we_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
created $dff cell `$procdff$14882' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_sel_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
created $dff cell `$procdff$14883' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_stb_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
created $dff cell `$procdff$14884' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_cyc_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
created $dff cell `$procdff$14885' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\state' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
created $dff cell `$procdff$14886' with positive edge clock.
Creating register for signal `\mem_wb.\wb_ack_o' using process `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'.
created $dff cell `$procdff$14887' with positive edge clock.
Creating register for signal `\mem_wb.\wb_ack_read' using process `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'.
created $dff cell `$procdff$14888' with positive edge clock.
Creating register for signal `\counter_timer_low.\irq_out' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
created $adff cell `$procdff$14889' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\strobe' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
created $adff cell `$procdff$14890' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\stop_out' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
created $adff cell `$procdff$14891' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\value_cur' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
created $adff cell `$procdff$14892' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\lastenable' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
created $adff cell `$procdff$14893' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\value_reset' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'.
created $adff cell `$procdff$14894' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\enable' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
created $adff cell `$procdff$14895' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\oneshot' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
created $adff cell `$procdff$14896' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\updown' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
created $adff cell `$procdff$14897' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\irq_ena' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
created $adff cell `$procdff$14898' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\chain' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
created $adff cell `$procdff$14899' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\irq_out' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
created $adff cell `$procdff$14900' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\stop_out' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
created $adff cell `$procdff$14901' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\value_cur' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
created $adff cell `$procdff$14902' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\lastenable' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
created $adff cell `$procdff$14903' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\value_reset' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'.
created $adff cell `$procdff$14904' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\enable' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
created $adff cell `$procdff$14905' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\oneshot' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
created $adff cell `$procdff$14906' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\updown' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
created $adff cell `$procdff$14907' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\irq_ena' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
created $adff cell `$procdff$14908' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\chain' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
created $adff cell `$procdff$14909' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\isdo' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
created $adff cell `$procdff$14910' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\treg' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
created $adff cell `$procdff$14911' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\rreg' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
created $adff cell `$procdff$14912' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\isck' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'.
created $adff cell `$procdff$14913' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\count' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'.
created $adff cell `$procdff$14914' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\hsck' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'.
created $adff cell `$procdff$14915' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\state' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
created $adff cell `$procdff$14916' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\done' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
created $adff cell `$procdff$14917' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\icsb' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
created $adff cell `$procdff$14918' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\nbit' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
created $adff cell `$procdff$14919' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\err_out' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
created $adff cell `$procdff$14920' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\d_latched' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
created $adff cell `$procdff$14921' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\w_latched' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
created $adff cell `$procdff$14922' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\r_latched' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
created $adff cell `$procdff$14923' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\enable' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
created $adff cell `$procdff$14924' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\prescaler' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
created $adff cell `$procdff$14925' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\invsck' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
created $adff cell `$procdff$14926' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\invcsb' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
created $adff cell `$procdff$14927' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\mlb' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
created $adff cell `$procdff$14928' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\irqena' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
created $adff cell `$procdff$14929' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\stream' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
created $adff cell `$procdff$14930' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\mode' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
created $adff cell `$procdff$14931' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\hkconn' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
created $adff cell `$procdff$14932' with positive edge clock and negative level reset.
Creating register for signal `\simpleuart.\send_pattern' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
created $dff cell `$procdff$14933' with positive edge clock.
Creating register for signal `\simpleuart.\send_bitcnt' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
created $dff cell `$procdff$14934' with positive edge clock.
Creating register for signal `\simpleuart.\send_divcnt' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
created $dff cell `$procdff$14935' with positive edge clock.
Creating register for signal `\simpleuart.\send_dummy' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
created $dff cell `$procdff$14936' with positive edge clock.
Creating register for signal `\simpleuart.\recv_state' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
created $dff cell `$procdff$14937' with positive edge clock.
Creating register for signal `\simpleuart.\recv_divcnt' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
created $dff cell `$procdff$14938' with positive edge clock.
Creating register for signal `\simpleuart.\recv_pattern' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
created $dff cell `$procdff$14939' with positive edge clock.
Creating register for signal `\simpleuart.\recv_buf_data' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
created $dff cell `$procdff$14940' with positive edge clock.
Creating register for signal `\simpleuart.\recv_buf_valid' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
created $dff cell `$procdff$14941' with positive edge clock.
Creating register for signal `\simpleuart.\enabled' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'.
created $dff cell `$procdff$14942' with positive edge clock.
Creating register for signal `\simpleuart.\cfg_divider' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'.
created $dff cell `$procdff$14943' with positive edge clock.
Creating register for signal `\spimemio_xfer.\flash_csb' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
created $dff cell `$procdff$14944' with positive edge clock.
Creating register for signal `\spimemio_xfer.\flash_clk' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
created $dff cell `$procdff$14945' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_dspi' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
created $dff cell `$procdff$14946' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_ddr' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
created $dff cell `$procdff$14947' with positive edge clock.
Creating register for signal `\spimemio_xfer.\obuffer' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
created $dff cell `$procdff$14948' with positive edge clock.
Creating register for signal `\spimemio_xfer.\ibuffer' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
created $dff cell `$procdff$14949' with positive edge clock.
Creating register for signal `\spimemio_xfer.\count' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
created $dff cell `$procdff$14950' with positive edge clock.
Creating register for signal `\spimemio_xfer.\dummy_count' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
created $dff cell `$procdff$14951' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_cont' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
created $dff cell `$procdff$14952' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_qspi' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
created $dff cell `$procdff$14953' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_rd' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
created $dff cell `$procdff$14954' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_tag' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
created $dff cell `$procdff$14955' with positive edge clock.
Creating register for signal `\spimemio_xfer.\fetch' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
created $dff cell `$procdff$14956' with positive edge clock.
Creating register for signal `\spimemio_xfer.\last_fetch' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
created $dff cell `$procdff$14957' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_ddr_q' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:598$1235'.
created $dff cell `$procdff$14958' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_tag_q' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:598$1235'.
created $dff cell `$procdff$14959' with positive edge clock.
Creating register for signal `\spimemio.\state' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
created $dff cell `$procdff$14960' with positive edge clock.
Creating register for signal `\spimemio.\rdata' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
created $dff cell `$procdff$14961' with positive edge clock.
Creating register for signal `\spimemio.\xfer_resetn' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
created $dff cell `$procdff$14962' with positive edge clock.
Creating register for signal `\spimemio.\din_valid' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
created $dff cell `$procdff$14963' with positive edge clock.
Creating register for signal `\spimemio.\din_data' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
created $dff cell `$procdff$14964' with positive edge clock.
Creating register for signal `\spimemio.\din_tag' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
created $dff cell `$procdff$14965' with positive edge clock.
Creating register for signal `\spimemio.\din_cont' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
created $dff cell `$procdff$14966' with positive edge clock.
Creating register for signal `\spimemio.\din_qspi' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
created $dff cell `$procdff$14967' with positive edge clock.
Creating register for signal `\spimemio.\din_ddr' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
created $dff cell `$procdff$14968' with positive edge clock.
Creating register for signal `\spimemio.\din_rd' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
created $dff cell `$procdff$14969' with positive edge clock.
Creating register for signal `\spimemio.\buffer' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
created $dff cell `$procdff$14970' with positive edge clock.
Creating register for signal `\spimemio.\rd_addr' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
created $dff cell `$procdff$14971' with positive edge clock.
Creating register for signal `\spimemio.\rd_valid' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
created $dff cell `$procdff$14972' with positive edge clock.
Creating register for signal `\spimemio.\rd_wait' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
created $dff cell `$procdff$14973' with positive edge clock.
Creating register for signal `\spimemio.\rd_inc' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
created $dff cell `$procdff$14974' with positive edge clock.
Creating register for signal `\spimemio.\xfer_io0_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'.
created $dff cell `$procdff$14975' with negative edge clock.
Creating register for signal `\spimemio.\xfer_io1_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'.
created $dff cell `$procdff$14976' with negative edge clock.
Creating register for signal `\spimemio.\xfer_io2_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'.
created $dff cell `$procdff$14977' with negative edge clock.
Creating register for signal `\spimemio.\xfer_io3_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'.
created $dff cell `$procdff$14978' with negative edge clock.
Creating register for signal `\spimemio.\softreset' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
created $dff cell `$procdff$14979' with positive edge clock.
Creating register for signal `\spimemio.\config_en' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
created $dff cell `$procdff$14980' with positive edge clock.
Creating register for signal `\spimemio.\config_ddr' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
created $dff cell `$procdff$14981' with positive edge clock.
Creating register for signal `\spimemio.\config_qspi' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
created $dff cell `$procdff$14982' with positive edge clock.
Creating register for signal `\spimemio.\config_cont' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
created $dff cell `$procdff$14983' with positive edge clock.
Creating register for signal `\spimemio.\config_dummy' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
created $dff cell `$procdff$14984' with positive edge clock.
Creating register for signal `\spimemio.\config_oe' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
created $dff cell `$procdff$14985' with positive edge clock.
Creating register for signal `\spimemio.\config_csb' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
created $dff cell `$procdff$14986' with positive edge clock.
Creating register for signal `\spimemio.\config_clk' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
created $dff cell `$procdff$14987' with positive edge clock.
Creating register for signal `\spimemio.\config_do' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
created $dff cell `$procdff$14988' with positive edge clock.
Creating register for signal `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.\wb_ack_o' using process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'.
created $dff cell `$procdff$14989' with positive edge clock.
Creating register for signal `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.\wb_ack_read' using process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'.
created $dff cell `$procdff$14990' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\pcpi_wr' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
created $dff cell `$procdff$14991' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\pcpi_rd' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
created $dff cell `$procdff$14992' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\pcpi_ready' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
created $dff cell `$procdff$14993' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\dividend' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
created $dff cell `$procdff$14994' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\divisor' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
created $dff cell `$procdff$14995' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\quotient' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
created $dff cell `$procdff$14996' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\quotient_msk' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
created $dff cell `$procdff$14997' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\running' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
created $dff cell `$procdff$14998' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\outsign' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
created $dff cell `$procdff$14999' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\pcpi_wait' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
created $dff cell `$procdff$15000' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\pcpi_wait_q' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
created $dff cell `$procdff$15001' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\instr_div' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
created $dff cell `$procdff$15002' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\instr_divu' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
created $dff cell `$procdff$15003' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\instr_rem' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
created $dff cell `$procdff$15004' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\instr_remu' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
created $dff cell `$procdff$15005' with positive edge clock.
Creating register for signal `$paramod\clock_div\SIZE=3.\syncN' using process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'.
created $adff cell `$procdff$15006' with positive edge clock and negative level reset.
Creating register for signal `$paramod\clock_div\SIZE=3.\syncNp' using process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'.
created $adff cell `$procdff$15007' with positive edge clock and negative level reset.
Creating register for signal `\picorv32_pcpi_mul.\pcpi_wr' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'.
created $dff cell `$procdff$15008' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\pcpi_rd' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'.
created $dff cell `$procdff$15009' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\pcpi_ready' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'.
created $dff cell `$procdff$15010' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\rs1' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
created $dff cell `$procdff$15011' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\rs2' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
created $dff cell `$procdff$15012' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\rd' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
created $dff cell `$procdff$15013' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\rdx' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
created $dff cell `$procdff$15014' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\mul_counter' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
created $dff cell `$procdff$15015' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\mul_waiting' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
created $dff cell `$procdff$15016' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\mul_finish' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
created $dff cell `$procdff$15017' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\pcpi_wait' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
created $dff cell `$procdff$15018' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\instr_mul' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
created $dff cell `$procdff$15019' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\instr_mulh' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
created $dff cell `$procdff$15020' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\instr_mulhsu' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
created $dff cell `$procdff$15021' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\instr_mulhu' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
created $dff cell `$procdff$15022' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\pcpi_wait_q' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
created $dff cell `$procdff$15023' with positive edge clock.
Creating register for signal `\housekeeping_spi_slave.\pass_thru_mgmt' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
created $adff cell `$procdff$15024' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\state' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
created $adff cell `$procdff$15025' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\addr' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
created $adff cell `$procdff$15026' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\count' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
created $adff cell `$procdff$15027' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\rdstb' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
created $adff cell `$procdff$15028' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\pass_thru_mgmt_delay' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
created $adff cell `$procdff$15029' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\pass_thru_user' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
created $adff cell `$procdff$15030' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\pass_thru_user_delay' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
created $adff cell `$procdff$15031' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\writemode' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
created $adff cell `$procdff$15032' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\readmode' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
created $adff cell `$procdff$15033' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\fixed' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
created $adff cell `$procdff$15034' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\predata' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
created $adff cell `$procdff$15035' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\pre_pass_thru_mgmt' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
created $adff cell `$procdff$15036' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\pre_pass_thru_user' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
created $adff cell `$procdff$15037' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\sdoenb' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
created $adff cell `$procdff$15038' with negative edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\wrstb' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
created $adff cell `$procdff$15039' with negative edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\ldata' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
created $adff cell `$procdff$15040' with negative edge clock and positive level reset.
Creating register for signal `\housekeeping_spi.\pll_dco_ena' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
created $adff cell `$procdff$15041' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\pll_sel' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
created $adff cell `$procdff$15042' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\pll90_sel' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
created $adff cell `$procdff$15043' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\pll_div' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
created $adff cell `$procdff$15044' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\pll_ena' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
created $adff cell `$procdff$15045' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\pll_trim' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
created $adff cell `$procdff$15046' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\pll_bypass' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
created $adff cell `$procdff$15047' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\irq' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
created $adff cell `$procdff$15048' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\reset_reg' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
created $adff cell `$procdff$15049' with positive edge clock and negative level reset.
Creating register for signal `\caravel_clocking.\reset_delay' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263'.
created $adff cell `$procdff$15050' with positive edge clock and negative level reset.
Creating register for signal `\caravel_clocking.\use_pll_first' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
created $adff cell `$procdff$15051' with positive edge clock and negative level reset.
Creating register for signal `\caravel_clocking.\use_pll_second' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
created $adff cell `$procdff$15052' with positive edge clock and negative level reset.
Creating register for signal `\caravel_clocking.\ext_clk_syncd_pre' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
created $dff cell `$procdff$15053' with positive edge clock.
Creating register for signal `\caravel_clocking.\ext_clk_syncd' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
created $adff cell `$procdff$15054' with positive edge clock and negative level reset.
Creating register for signal `\even.\counter' using process `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'.
created $adff cell `$procdff$15055' with positive edge clock and negative level reset.
Creating register for signal `\even.\out_counter' using process `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'.
created $adff cell `$procdff$15056' with positive edge clock and negative level reset.
Creating register for signal `\odd.\old_N' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:146$247'.
created $dff cell `$procdff$15057' with positive edge clock.
Creating register for signal `\odd.\rst_pulse' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244'.
created $adff cell `$procdff$15058' with positive edge clock and negative level reset.
Creating register for signal `\odd.\counter2' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
Warning: Async reset value `\N' is not constant!
created $dffsr cell `$procdff$15059' with negative edge clock and negative level non-const reset.
Creating register for signal `\odd.\out_counter2' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
created $adff cell `$procdff$15066' with negative edge clock and negative level reset.
Creating register for signal `\odd.\initial_begin' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
Warning: Async reset value `$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235_Y [3:1]' is not constant!
created $dffsr cell `$procdff$15067' with negative edge clock and negative level non-const reset.
Creating register for signal `\odd.\counter' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'.
Warning: Async reset value `\N' is not constant!
created $dffsr cell `$procdff$15074' with positive edge clock and negative level non-const reset.
Creating register for signal `\odd.\out_counter' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'.
created $adff cell `$procdff$15081' with positive edge clock and negative level reset.
Creating register for signal `\mgmt_soc_regs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_ADDR' using process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'.
created $dff cell `$procdff$15082' with positive edge clock.
Creating register for signal `\mgmt_soc_regs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_DATA' using process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'.
created $dff cell `$procdff$15083' with positive edge clock.
Creating register for signal `\mgmt_soc_regs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN' using process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'.
created $dff cell `$procdff$15084' with positive edge clock.
13.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 61 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'.
Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'.
Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1288$7327'.
Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'.
Found and cleaned up 8 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293'.
Found and cleaned up 22 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
Found and cleaned up 3 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
Found and cleaned up 5 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
Found and cleaned up 47 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026'.
Found and cleaned up 16 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
Found and cleaned up 19 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'.
Found and cleaned up 3 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'.
Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'.
Found and cleaned up 1 empty switch in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
Found and cleaned up 42 empty switches in `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
Removing empty process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
Found and cleaned up 9 empty switches in `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
Removing empty process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
Found and cleaned up 10 empty switches in `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
Removing empty process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6602'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6597'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6592'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6587'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6582'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6577'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6572'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6567'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6562'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6557'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6552'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6547'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6542'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6537'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6532'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6527'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6522'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6517'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6512'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6507'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6502'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6497'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6492'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6487'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6482'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6477'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6472'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6467'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6462'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6457'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6452'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6447'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6442'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6437'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6432'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6427'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6422'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6417'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6412'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6410'.
Found and cleaned up 13 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
Found and cleaned up 6 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'.
Found and cleaned up 3 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'.
Found and cleaned up 43 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367'.
Found and cleaned up 4 empty switches in `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
Removing empty process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
Found and cleaned up 1 empty switch in `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'.
Removing empty process `mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'.
Found and cleaned up 25 empty switches in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
Removing empty process `counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
Found and cleaned up 4 empty switches in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'.
Removing empty process `counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'.
Found and cleaned up 1 empty switch in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
Removing empty process `counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
Found and cleaned up 26 empty switches in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
Removing empty process `counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
Found and cleaned up 4 empty switches in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'.
Removing empty process `counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'.
Found and cleaned up 1 empty switch in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
Removing empty process `counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
Found and cleaned up 6 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
Found and cleaned up 1 empty switch in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'.
Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'.
Found and cleaned up 2 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'.
Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'.
Found and cleaned up 6 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
Found and cleaned up 9 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
Found and cleaned up 2 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
Found and cleaned up 5 empty switches in `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
Removing empty process `simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
Found and cleaned up 7 empty switches in `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
Removing empty process `simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
Found and cleaned up 6 empty switches in `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'.
Removing empty process `simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'.
Found and cleaned up 4 empty switches in `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
Removing empty process `spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
Found and cleaned up 5 empty switches in `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
Removing empty process `spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
Removing empty process `spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:598$1235'.
Found and cleaned up 25 empty switches in `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
Removing empty process `spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
Removing empty process `spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'.
Found and cleaned up 5 empty switches in `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
Removing empty process `spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
Removing empty process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:84$4518'.
Found and cleaned up 1 empty switch in `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'.
Removing empty process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'.
Removing empty process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:52$3512'.
Found and cleaned up 5 empty switches in `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
Removing empty process `picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
Found and cleaned up 2 empty switches in `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
Removing empty process `picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
Removing empty process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'.
Found and cleaned up 1 empty switch in `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'.
Removing empty process `picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'.